US20070290729A1 - PWM circuit and PWM integrated circuit for use in PWM circuit - Google Patents
PWM circuit and PWM integrated circuit for use in PWM circuit Download PDFInfo
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- US20070290729A1 US20070290729A1 US11/454,459 US45445906A US2007290729A1 US 20070290729 A1 US20070290729 A1 US 20070290729A1 US 45445906 A US45445906 A US 45445906A US 2007290729 A1 US2007290729 A1 US 2007290729A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K7/00—Modulating pulses with a continuously-variable modulating signal
- H03K7/08—Duration or width modulation ; Duty cycle modulation
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Abstract
Description
- 1. Field of the Invention
- The present invention relates to a PWM (Pulse Width Modulation) circuit, and in particular to a PWM integrated circuit capable of receiving an external programming signal without any extra pin, and a PWM integrated circuit for use in such a PWM circuit.
- 2. Description of the Related Art
- As shown in
FIG. 1 , a conventional PWM circuit comprises acomparator 10. An output voltage at the output terminal Vo is sampled by avoltage sampler circuit 20, and compensated by acompensation circuit 30; the output of thecompensation circuit 30 is sent to an input terminal of thecomparator 10, to be compared with a reference sawtooth wave and generate comparison output signals thereby, for controlling the operations of a control switch CTL_SW and a synchronous switch SYN_SW. The output voltage at the terminal Vo, after sampled by thevoltage sampler circuit 20, is also fed back and compared with a reference voltage Vr, to more accurately control the positive input of thecomparator 10. The operations of the switches CTL_SW and SYN_SW, through an inductor L, control the duty cycle (i.e., the pulse width) of an output square wave generated at the output terminal Vo. The output voltage may be used to support either or both of loads U_Load and L_Load (schematically shown for purpose of illustration only), according to circuit design requirements. The details of a PWM circuit are well known to one skilled in this art, and therefore are not further explained here. - In the above-mentioned circuit, the circuit elements encompassed by the
dash line 100 are usually integrated in an integrated circuit, while the elements outside thedash line 100 are usually made from discrete devices. In the present invention, the complete circuit is referred to as “a PWM circuit”, while the partial circuit integrated into an integrated circuit is referred to as “a PWM integrated circuit”, which constitutes an essential part of a PWM circuit. The PWM integratedcircuit 100 communicates with external circuit elements through pins. As shown in the figure, the integratedcircuit 100 requires at least six pins P1-P6 to communicate with external circuit elements, including: a pin P1 electrically connecting with a voltage source Vs for supplying a relatively high voltage to thecomparator 10; a pin P2 electrically connecting an output of thecomparator 10 to the control switch CTL_SW for controlling its operation; a pin P3 receiving a voltage level from the node SW between the switches CTL_SW and SYN_SW, for supplying a reference voltage level to thecomparator 10; a pin P4 electrically connecting another output of thecomparator 10 to the synchronous switch SYN_SW for controlling its operation; a pin P5 for receiving the output from thecompensation circuit 30; and a pin P6 for receiving the feedback signal from thevoltage sampler circuit 20. - In addition to the above-mentioned pins, in a PWM circuit, it is usually required to avoid over current at the node SW, and therefore it is required to detect the current status at the node SW and provide a corresponding feedback control based thereon. There are two conventional ways to do so. As shown in
FIG. 1 , one conventional way is to provide a constant current source Ioc inside the PWM integratedcircuit 100, and a resistor R1 outside the PWM integrated circuit. The resistance of the resistor R1 may be determined according to an over current threshold given by a user of the PWM circuit. By means of the constant current source Ioc and the resistor R1, a predetermined voltage is provided at the node Voc1. As shown in the figure, the predetermined voltage, after properly adjusted, is compared with the voltage level at the node SW by acomparator 40. (Thus, the so-called “over current threshold” is actually embodied in the form of a voltage comparison.) The comparison by thecomparator 40 generates an output signal OCP which may be used to trigger over current protection, such as turning off certain switches. - Another conventional way is shown in
FIG. 2 . Theintegrated circuit 100 internally generates a reference voltage Voc2, which is input to acomparator 50. The voltage level at the node SW, minus a voltage drop by the resistor R2 (whose resistance may similarly be determined based on the over current threshold given by a user), is provided to another input terminal of thecomparator 50. The comparison by thecomparator 50 similarly generates an output signal OCP to trigger over current protection. - The above-mentioned conventional PWM circuits have a drawback that an additional pin P7 is required for over current protection, which is not desired. The pin number of an integrated circuit should be as few as possible.
- Another drawback of the conventional PWM circuit is that, it is not possible to program the internal circuit inside the PWM integrated circuit unless an additional pin is provided.
- In view of the foregoing drawbacks, the present invention proposes a PWM circuit and a PWM integrated circuit, which are capable of receiving an over current threshold setting, or other external programming signals, without any extra pin.
- A first objective of the present invention is to provide a PWM circuit capable of receiving an external programming signal without any extra pin.
- A second objective of the present invention is to provide a PWM integrated circuit for use in the PWM circuit.
- To achieve the foregoing objectives, according to an aspect of the present invention, a PWM circuit comprises: (1) a first and a second switches electrically connected with each other through a node between them, the node being capable of providing a voltage signal; (2) a PWM integrated circuit, including (2a) a plurality of pins including a first pin for controlling the first switch, a second pin for controlling the second switch, and a third pin for receiving the voltage signal from the node; and (2b) a programming unit electrically connected with one of the first or second pin for receiving a programming signal transmitted through the one pin to program a parameter of the PWM circuit; and (3) a parameter setting circuit electrically connected with the one pin.
- According to another aspect of the present invention, a PWM circuit comprises: (1) a first and a second switches electrically connected with each other through a node between them, the node being capable of providing a voltage signal; (2) a PWM integrated circuit, including (2a) a plurality of pins including a first pin for controlling the first switch, a second pin for controlling the second switch, and a third pin for receiving the voltage signal from the node; and (2b) a programming unit electrically connected with the first and second pins for receiving a programming signal transmitted through one of the first or second pin to program a parameter of the PWM circuit; and (3) a parameter setting circuit electrically connected between the first and second pins.
- According to a further aspect of the present invention, a PWM integrated circuit comprises: (1) a comparator generating at least two outputs; (2) at least two pins electrically connected with the two outputs, respectively; and (3) a programming unit electrically connected with at least one of the first and second pins for receiving an external programming signal to program a parameter of the PWM integrated circuit.
- The programming unit described in the foregoing paragraphs is capable of switching between an normal operation mode and a programming mode. In the normal operation mode, the programming unit transmits internal signals in the PWM integrated circuit to the pin connected with the programming unit, while in the programming mode, the programming unit receives an external programming signal.
- Preferably, the programming unit comprises a storage circuit to store the programming signal and to output the stored programming signal for parameter setting. Before storage, preferably, the analogue programming signal is first converted into a digital signal.
- For better understanding the objects, characteristics, and effects of the present invention, the present invention will be described below in detail by illustrative embodiments with reference to the attached drawings.
-
FIG. 1 is a circuit diagram schematically showing a conventional PWM circuit. -
FIG. 2 is a circuit diagram schematically showing another conventional PWM circuit. -
FIG. 3 is a circuit diagram schematically showing a PWM circuit according to a preferred embodiment of the present invention. -
FIG. 4 is a circuit diagram schematically showing a PWM circuit according to another preferred embodiment of the present invention. -
FIG. 5 is a circuit diagram schematically showing the programming unit in the embodiments shown inFIGS. 3 and 4 . -
FIG. 6 is a circuit diagram schematically showing a PWM circuit according to a still other preferred embodiment of the present invention. -
FIGS. 7 and 8 are circuit diagrams schematically showing the programming unit in the embodiment shown inFIG. 6 . - Referring to
FIG. 3 which schematically shows a preferred embodiment according to the present invention, a PWM integratedcircuit 200 comprises aprogramming unit 70 electrically connected between the lower output of thecomparator 10 and the pin P4 for controlling the synchronous switch SYN_SW. (In this paragraph, we first explain the function of theprogramming unit 70, while the detailed circuit structure of theprogramming unit 70 will be described later with respect toFIG. 5 .) Theprogramming unit 70 has two modes: a programming mode and an normal operation mode. In the programming mode, theprogramming unit 70 serves to set/program a parameter, such as an over current threshold or other programmable parameters, in theintegrated circuit 200. After the setting/programming is done, theprogramming unit 70 may be switched to the normal operation mode wherein theprogramming unit 70 becomes a normal driver gate transmitting the output of thecomparator 10 to the synchronous switch SYN_SW. - From outside the PWM integrated
circuit 200, a user sets an over current threshold or programs other parameters by determining the resistance of the resistor Roc. However, there is a significant difference between this embodiment and the conventional PWM circuit in that no additional pin is required; the setting/programming is achieved by means of the existing pin P4. -
FIG. 4 shows another embodiment according to the present invention. As shown in the figure, theprogramming unit 70 is electrically connected between the upper output of thecomparator 10 and the pin P2 for controlling the control switch CTL_SW. In this embodiment, no additional pin is required; the setting/programming is achieved by means of the existing pin P2. - The detailed circuit structure of the
programming unit 70 is now described with respect toFIG. 5 . As shown in the figure, theprogramming unit 70 includes a tri-statedriver gate 71, which receives an output of the comparator 10 (which could be the upper output or lower output of thecomparator 10, depending on which embodiment theprogramming unit 70 is applied to) and transmits the output to a pin PIN, which could be the pin P4 inFIG. 3 , or the pin P2 inFIG. 4 . The tri-statedriver gate 71 is controlled by an enable signal EN. When the enable signal EN is in an “enable” state, theprogramming unit 70 is set to the normal operation mode wherein thetri-state driver gate 71 allows the output from thecomparator 10 to pass through it and reach the pin PIN. When the enable signal EN is in a “disable” state, theprogramming unit 70 is set to the programming mode wherein the output terminal of thetri-state driver gate 71 is floating, i.e., the node A is not affected by thetri-state driver gate 71, but is controlled by the other part of the circuit. - When the
programming unit 70 is set to the programming mode, a constantcurrent source 72 provides a constant current which flows to ground through the path: node A—pin PIN—resistor Roc—ground. Thus, a voltage across the resistor Roc is generated, which is the voltage at the node A. - The voltage across the resistor Roc is for use to compare with the voltage at the node SW and to generate an over current protection signal thereby. However, during normal operation mode, the
tri-state driver gate 71 is required to transmit the output from thecomparator 10, whereas the voltage at the node A should thus be controlled by the output of thetri-state driver gate 71. Therefore, it is not preferred to directly compare the voltage at the node A with the voltage at the node SW by acomparator 76, for the reason that the voltage value set by the constantcurrent source 72 and the resistor Roc would be lost during normal operation mode. It is preferred that the voltage value set by the constantcurrent source 72 and the resistor Roc in the programming mode is first stored, and the stored voltage value may then be used for comparison. There are many possible ways to store a voltage value, as well known to one killed in this art; for example, a voltage value may be stored in its analogue form. According to a preferred embodiment of the present invention, as shown in the figure, the voltage at the node A is first converted into a digital value by an ADC (Analogue-to-Digital Converter)circuit 73, and next stored in astorage circuit 74. Thestorage circuit 74 receives the same enable signal EN as thetri-state driver gate 71; when the enable signal EN is in a “disable” state, thestorage circuit 74 receives data input, but when the enable signal EN is in an “enable” state, thestorage circuit 74 latches data and does not accept any new data input from theADC circuit 73. The digital data stored in thestorage circuit 74 is output to a DAC (Digital-to-Analogue Converter)circuit 75 and converted into an analogue signal thereby. The output of theDAC circuit 75 is input to the positive terminal of acomparator 76 to be compared with the voltage at the node SW, for generating an over current protection signal OCP. - In the above-mentioned embodiment, the
ADC circuit 73 and theDAC circuit 75 may be a very simple circuit providing conversion of only one bit, or a relatively complex circuit capable of providing conversion of N bits (N being an integer), depending on the requirements of the PWM circuit. There are many possible ways to embody theADC circuit 73 andDAC circuit 75; as an example, one may refer to the circuit described in U.S. Pat. No. 7,042,773. The details thereof are omitted here. - In comparison with direct storage of an analogue voltage value, the foregoing embodiment which converts the analogue voltage value at the node A into a digital data, and next stores the data in digital form, provides an advantage that the stored data will not be lost after a long time. In addition, there is another advantage. The voltage at the node A is not input to the
comparator 76 directly, but instead, it has to be A-to-D converted, stored, and D-to-A converted. Thus, the voltage across the resistor Roc does not has to be exactly the same as or substantially have an 1:1 correspondence with the voltage to be input to thecomparator 76. The voltage at the node A and the voltage to be input to thecomparator 76 may be arranged to be any ratio, by properly designing the conversion ratio of theADC circuit 73 andDAC circuit 75. This provides an advantage that the error tolerance of the resistor Roc is enlarged. For example, if the voltage across the resistor Roc has an 2:1 correspondence with the voltage to be input to thecomparator 76, the error tolerance for the resistor Roc becomes two times. - In addition to the above, in comparison with the conventional PWM circuits shown in
FIGS. 1 and 2 , the present invention provides a further advantage that the PWM circuit according to the present invention may provide a programming function that is not provided in the conventional PWM circuits. More specifically, the digital data stored in thestorage circuit 74 may be used in other ways than setting the over current threshold. For example, assuming the PWMintegrated circuit 200 has two or more operation modes, thedigital output 77 of thestorage circuit 74 may be used to determine the operation made. That is, by setting the resistance of the resistor Roc, a user of the PWM circuit may determine the operation mode of the PWM integrated circuit. Other types of programming/setting are also possible by means of thedigital output 77. Moreover, since theADC converter circuit 73 may be an N-bit conversion circuit, a user may achieve a rather complex programming function with 2N possibilities by properly determining the resistance of the resistor Roc. The programming function may be combined with the setting of the over current threshold, or may be a stand-alone function. In the former case, as an example, assuming N=4, the two most significant bits may be used to set the over current threshold, while the two least significant bits may be used for other programming functions. In the latter case, theDAC circuit 75 and thecomparator 76 may be omitted; the resistance of the resistor Roc is determined solely for the purpose of programming. The over current protection may be achieved by another circuit, such as, by providing twoprogramming units 70 respectively electrically connected with the pins P2 and P4 of the PWMintegrated circuit 200, one of whichprogramming units 70 is for programming, and the other of which is for over current threshold setting. -
FIG. 6 shows another embodiment according to the present invention. As shown in the figure, the resistor Roc for setting the over current threshold is connected between the pins P2 and P4. Two embodiments of theprogramming unit 80 corresponding to such an arrangement are shown respectively inFIGS. 7 and 8 . - As shown in
FIG. 7 , theprogramming unit 80 comprises twotri-state driver gates comparator 10. The rest of theprogramming unit 80 is similar to that of theprogramming unit 70. When the enable signal EN is in an “enable” state, thetri-state driver gates comparator 10 to the pins P2 and P4. When the enable signal EN is in a “disable” state, theprogramming unit 80 is set to the programming mode; the output terminal of thetri-state driver gate 81U is set to a low level, while the output terminal of thetri-state driver gate 81L is floating. The current provided by a constantcurrent source 82 flows to ground through the path: node B—pin P4—resistor Roc—pin P2—ground path of thetri-state driver gate 81U-ground. Thus, a voltage across the resistor Roc is generated, which is the voltage at the node B. Similar to theprogramming unit 70, the voltage at the node B is converted by anADC circuit 83, stored by astorage circuit 84, converted by aDAC circuit 85, and finally input to acomparator 86, to be compared with the voltage at the node SW for generating an over current protection signal OCP. - It is readily conceivable by one skilled in this art that the embodiment shown in
FIG. 7 may be modified as the one shown inFIG. 8 . In this embodiment, when the enable signal EN is in a “disable” state, theprogramming unit 80 is set to the programming mode; the output terminal of thetri-state driver gate 91U is floating, while the output terminal of thetri-state driver gate 91L is set to a low level. The current provided by a constant current source 92 flows to ground through the path: node C—pin P2—resistor Roc—pin P4—ground path of thetri-state driver gate 91L—ground. Thus, a voltage across the resistor Roc is generated, which is the voltage at the node C that may be used to generate an over current protection signal OCP in a manner similar to the foregoing embodiments. - The features, characteristics and effects of the present invention have been described with reference to its preferred embodiments, which are illustrative of the invention rather than limiting of the invention. Various other substitutions and modifications will occur to those skilled in the art, without departing from the spirit of the present invention. For example, in the described embodiments, the
comparators comparators digital signals
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080106302A1 (en) * | 2006-11-08 | 2008-05-08 | Kin Yip Sit | Domino circuit with disable feature |
US20100066323A1 (en) * | 2008-09-18 | 2010-03-18 | Intersil Americas Inc. | System and method for providing pulse frequency modulation mode |
US20110267128A1 (en) * | 2010-04-28 | 2011-11-03 | Richtek Technology Corp. | Parameter setting circuit and method for integrated circuits |
CN102255613A (en) * | 2010-05-18 | 2011-11-23 | 立锜科技股份有限公司 | Parameter setting circuit and method for integrated circuit |
CN106329929A (en) * | 2015-07-03 | 2017-01-11 | 立锜科技股份有限公司 | Voltage converting circuit and voltage converting controller |
US20170222629A1 (en) * | 2015-12-16 | 2017-08-03 | Cirrus Logic, Inc. | Adjustable time duration for driving pulse-width modulation (pwm) output to reduce thermal noise |
US20170257032A1 (en) * | 2016-03-03 | 2017-09-07 | Chengdu Monolithic Power Systems Co., Ltd. | Synchronous switching converter and associated integrated semiconductor device |
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Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5075634A (en) * | 1990-11-23 | 1991-12-24 | Blade Technologies Inc. | Composite bridge amplifier |
US6147526A (en) * | 1997-12-23 | 2000-11-14 | Texas Instruments Incorporated | Ripple regulator with improved initial accuracy and noise immunity |
US20030174005A1 (en) * | 2002-03-14 | 2003-09-18 | Latham Paul W. | Cmos digital pulse width modulation controller |
US20060022732A1 (en) * | 2004-07-27 | 2006-02-02 | Kafai Leung | DPWM with leading edge blanker circuit |
US20060028257A1 (en) * | 2004-08-03 | 2006-02-09 | Hong Huang | System and method for over-temperature protection sensing employing MOSFET on-resistance Rds_on |
US7026851B2 (en) * | 2004-05-12 | 2006-04-11 | System General Corp. | PWM controller having frequency jitter for power supplies |
US20060097765A1 (en) * | 2004-11-10 | 2006-05-11 | Autonetworks Technologies, Ltd. | PWM signal generation circuit and PWM control circuit |
US7199643B2 (en) * | 2003-09-26 | 2007-04-03 | Maxim Integrated Products, Inc. | Hot swappable pulse width modulation power supply circuits |
-
2006
- 2006-06-16 US US11/454,459 patent/US7315190B1/en active Active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5075634A (en) * | 1990-11-23 | 1991-12-24 | Blade Technologies Inc. | Composite bridge amplifier |
US6147526A (en) * | 1997-12-23 | 2000-11-14 | Texas Instruments Incorporated | Ripple regulator with improved initial accuracy and noise immunity |
US20030174005A1 (en) * | 2002-03-14 | 2003-09-18 | Latham Paul W. | Cmos digital pulse width modulation controller |
US7199643B2 (en) * | 2003-09-26 | 2007-04-03 | Maxim Integrated Products, Inc. | Hot swappable pulse width modulation power supply circuits |
US7026851B2 (en) * | 2004-05-12 | 2006-04-11 | System General Corp. | PWM controller having frequency jitter for power supplies |
US20060022732A1 (en) * | 2004-07-27 | 2006-02-02 | Kafai Leung | DPWM with leading edge blanker circuit |
US20060028257A1 (en) * | 2004-08-03 | 2006-02-09 | Hong Huang | System and method for over-temperature protection sensing employing MOSFET on-resistance Rds_on |
US20060097765A1 (en) * | 2004-11-10 | 2006-05-11 | Autonetworks Technologies, Ltd. | PWM signal generation circuit and PWM control circuit |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080106302A1 (en) * | 2006-11-08 | 2008-05-08 | Kin Yip Sit | Domino circuit with disable feature |
US7592840B2 (en) * | 2006-11-08 | 2009-09-22 | Intel Corporation | Domino circuit with disable feature |
US20100066323A1 (en) * | 2008-09-18 | 2010-03-18 | Intersil Americas Inc. | System and method for providing pulse frequency modulation mode |
US20110267128A1 (en) * | 2010-04-28 | 2011-11-03 | Richtek Technology Corp. | Parameter setting circuit and method for integrated circuits |
US8904317B2 (en) * | 2010-04-28 | 2014-12-02 | Richtek Technology Corp. | Parameter setting circuit and method for integrated circuits |
CN102255613A (en) * | 2010-05-18 | 2011-11-23 | 立锜科技股份有限公司 | Parameter setting circuit and method for integrated circuit |
CN106329929A (en) * | 2015-07-03 | 2017-01-11 | 立锜科技股份有限公司 | Voltage converting circuit and voltage converting controller |
US20170222629A1 (en) * | 2015-12-16 | 2017-08-03 | Cirrus Logic, Inc. | Adjustable time duration for driving pulse-width modulation (pwm) output to reduce thermal noise |
US9847773B2 (en) * | 2015-12-16 | 2017-12-19 | Cirrus Logic, Inc. | Adjustable time duration for driving pulse-width modulation (PWM) output to reduce thermal noise |
US20170257032A1 (en) * | 2016-03-03 | 2017-09-07 | Chengdu Monolithic Power Systems Co., Ltd. | Synchronous switching converter and associated integrated semiconductor device |
US10069422B2 (en) * | 2016-03-03 | 2018-09-04 | Chengdu Monolithic Power Systems Co., Ltd. | Synchronous switching converter and associated integrated semiconductor device |
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