US20070267744A1 - Manufacturing a bump electrode with roughened face - Google Patents
Manufacturing a bump electrode with roughened face Download PDFInfo
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- US20070267744A1 US20070267744A1 US11/798,506 US79850607A US2007267744A1 US 20070267744 A1 US20070267744 A1 US 20070267744A1 US 79850607 A US79850607 A US 79850607A US 2007267744 A1 US2007267744 A1 US 2007267744A1
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- bump
- semiconductor chip
- face
- prominences
- chip according
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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Definitions
- the present invention relates to a semiconductor device and a method for making the same, and particularly to a semiconductor chip mounted onto a tape substrate.
- FIG. 5 is a schematic view of a film tape carrier.
- the film tape carrier 30 is generally formed by laminating a copper foil onto a polyimide resin film, forming a circuit onto the copper foil, and plating thereon using Sn or Au, as an oblong product before the product is processed together with semiconductor devices.
- the lead comprises inner leads 20 bonded to an Au bump formed on an electrode pad of the semiconductor chip, and outer leads 36 integratedly formed with the inner leads 20 and used for connection to an exterior.
- a method for making a TCP by a gang bonding process which simultaneously bonds all bumps to inner leads will now be described with reference to FIG. 6 .
- a semiconductor chip is placed in a position surrounded by a device hole 32 on a stage (not shown in the drawing), and each bump of the semiconductor chip and the corresponding inner lead are aligned so that they are exactly bonded to each other.
- a heating unit 52 which is preliminarily heated to about 500° C., is lowered toward the bumps and the inner leads 20 so that the heating unit 52 presses the bumps and the inner leads 20 on the stage.
- the heat from the heating unit facilitates the formation of an Au/Sn eutectic alloy 46 shown in FIG. 6 ( 2 ) by alloying the Au and the Sn plated on the inner leads 20 .
- the mounting of the semiconductor chip 40 onto the film tape carrier 30 is completed by bonding the bumps to the inner leads 20 via the eutectic alloy 46 .
- unnecessary portions of the film tape carrier 30 are removed by punching to prepare a TCP.
- FIG. 4 is a schematic view showing a problem which occurs during mounting a semiconductor chip by a conventional technique.
- a bump 10 is formed on an electrode pad 42 of a semiconductor chip 40 . Since the periphery of the electrode pad 42 is covered by a passivation film 44 and protrudes, the bump 10 formed on the passivation film 44 also protrudes at the periphery and has an indented flat surface in the central portion.
- the inner lead 20 is put into contact with the bump 10 , a gap 18 is formed between the bump 10 and the inner lead 20 due to the protrusion.
- the central portion of the bump 10 does not contribute to the bonding of the bump 10 to the inner lead 20 , in this state.
- the present invention includes a semiconductor device that includes a tape substrate provided with a lead, and a semiconductor chip mounted onto the tape substrate by thermal welding a bump formed on an active face of the semiconductor chip with the lead. The upper face of the bump is roughened.
- the upper face of the bump is roughened so that the surface area increases compared to a case of a flat upper face of the bump.
- the area contributing to the formation of an Au/Sn eutectic alloy increases and the melted eutectic alloy penetrates the gap between prominences by a capillary phenomenon, ensuring bonding between the bump and the lead.
- high load and high temperature are not required for bonding, and the occurrence of inner lead cracking can be prevented.
- prominences having a height of 1 to 5 ⁇ m are continuously formed on the upper face of the bump.
- the height of the prominences formed by roughening the upper face of the bump is controlled within a range which increases the surface area of the upper face of the bump so as to contribute to the formation of the Au/Sn eutectic alloy and to ensure sufficient bonding strength between the bump and the lead.
- thermal welding between the bump and the lead are ensured.
- the heights of the prominences on the upper face of the bump be the same so that the prominences securely come into contact with the lead to facilitate the formation of the Au/Sn eutectic alloy between the prominences and the lead.
- a method for making a semiconductor device that includes a tape substrate provided with a lead, and a semiconductor chip mounted onto the tape substrate by thermal welding a bump formed on an active face of the semiconductor chip with the lead, includes the steps of roughening the upper face of the bump, and thermally welding the bump to the lead.
- the bump and the lead are thermally welded after the upper face of the bump is roughened.
- the surface area can be increased compared to a case of a flat upper face of the bump.
- reliability of bonding between the bump and the lead can be enhanced.
- the step for roughening is performed while a barrier metal formed on a semiconductor wafer provided with the semiconductor chip is simultaneously removed.
- the roughening step and the step for removing the barrier metal in the wafer process are simultaneously performed, and no additional process is required for roughening.
- the roughening treatment is performed by etching the upper face of the bump with an iodide compound.
- the iodine compound is potassium iodide or ammonium iodide.
- FIG. 1 includes illustrative views of a method for making a semiconductor device in accordance with an embodiment of the present invention, wherein FIG. 1 ( 1 ) is an illustrative view of the semiconductor chip before roughening a bump of a semiconductor chip, and FIG. 1 ( 2 ) is an illustrative view after roughening.
- FIG. 2 is an illustrative view of a bump after roughening treatment.
- FIG. 3 is an illustrative chart showing the relationship between the height of the prominence and the bonding strength of the bump and the inner lead.
- FIG. 4 is a schematic view showing a problem which occurs during mounting of a semiconductor chip by a conventional technique.
- FIG. 5 is a schematic view of a film tape carrier.
- FIG. 6 includes illustrative views of a method for thermally welding a bump of a semiconductor chip to an inner lead of a film tape carrier, wherein FIG. 6 ( 1 ) is an illustrative view of a state of the bump and the inner lead before thermal welding, and
- FIG. 6 ( 2 ) is an illustrative view of a state of the bump and the inner lead after thermal welding.
- FIG. 1 includes illustrative views of a method for making a semiconductor device in accordance with an embodiment of the present invention, wherein FIG. 1 ( 1 ) is an illustrative view of the semiconductor chip before roughening a bump of a semiconductor chip, and FIG. 1 ( 2 ) is an illustrative view after roughening. Moreover, FIG. 2 is an illustrative view of a bump after roughening treatment. FIG. 3 is an illustrative chart showing the relationship between the height of the prominence and the bonding strength of the bump and the inner lead.
- prominences are formed on the upper face of the bump to increase the surface area of the upper face so that the Au/Sn eutectic alloy is readily formed by thermal welding using a gang bonding apparatus.
- FIG. 1 ( 1 ) shows a halfway stage of the wafer process.
- a passivation film 44 is formed on a semiconductor wafer 50 that is provided with a semiconductor chip in a region other than an electrode pad 42 .
- a barrier metal layer 48 is formed over the passivation film 44 and the electrode pad 42 above the entire semiconductor wafer 50 .
- the barrier metal layer 48 includes two sub-layers. That is, a TiW sub-layer 48 a is formed by sputtering on the passivation film 44 , and then an Au sub-layer 48 b is formed by plating on the TiW sub-layer 48 a.
- a bump 10 is formed on the electrode pad 42 .
- the bump 10 is formed by applying a photoresist on the entire surface of the semiconductor wafer 50 , and by removing the photoresist in a bump-forming portion by exposure and development to form an opening, and then by plating Au in the opening.
- the upper face of the bump 10 in this stage is slightly indented in the central portion, as described above with reference to FIG. 3 .
- the semiconductor wafer 50 is etched using a potassium iodide or ammonium iodide solution.
- the etching as shown in FIG. 1 ( 2 ), removes the barrier metal layer 48 and roughens the upper face of the bump 10 to form many prominences 12 .
- the surface area of the bump 10 significantly increases compared to the surface area before etching. The difference in height between the periphery and the central portion of the bump 10 is considerably decreased due to the formation of the prominences 12 .
- the area contributing to the formation of the Au/Sn eutectic alloy significantly increases, and the formation of the eutectic alloy is facilitated.
- the melt eutectic alloy penetrates the gap of the prominences 12 by a capillary phenomenon and adheres onto sloping faces 14 of the prominences 12 so as to enhance the bonding between the bump 10 and the inner lead 20 .
- the bonding between the bump 10 and the inner lead 20 can be ensured even if the heating unit 52 is set at a lower temperature compared to conventional temperatures.
- the difference in the height on the upper face of the bump 10 is considerably decreased.
- the pressure of the heating unit 52 can be reduced compared to the conventional cases.
- the etching solution may be a solution containing an iodine compound or any compound other than potassium iodide and ammonium iodide, as long as the solution exhibits etching ability.
- the bump 10 may be formed of any material, such as Ni, in which Au is adhered to the surface of the prominence.
- the prominences 12 may be formed by a mechanical process, if possible, for example, by pressing the upper face of the bump 10 using a tool having an uneven surface or by buffing the upper face of the bump 10 using such a tool. According to the mechanical process, the heights of the prominences can be controlled within a predetermined range, and the formation of the Au/Sn eutectic alloy is further facilitated for the reasons described below.
- the height of the prominence 12 depends on the type of the etching solution used and the etching time. As shown in FIG. 2 , individual heights are also different, as shown by the lowest prominence 12 a and the highest prominence 12 b . It is preferable that the difference in the height be small as much as possible, because the formation of the An/Sn eutectic alloy is promoted in proportion to the contact area during thermal welding between the bump and the inner lead. In the case of a large difference in the height of the prominences 12 , prominences having lower heights are still distant from the inner lead and thus do not contribute to the formation of the Au/Sn eutectic alloy, even when the inner lead is pressed by the heating unit.
- the present inventor has performed experiments regarding the relationship between the heights of the prominences and the bonding strength of the bump and the inner lead, and has obtained the data confirming the effects. The results will now be described based on FIG. 3 .
- Term 1 in the table represents the surface roughness of the bump, that is, the heights of the prominences on the upper face of the bump.
- the description “0 to less than 1” represents all the heights of the prominences lie within the range of 0 to 1.
- Term 2 represents the state of the formation of the Au/Sn eutectic alloy, in which ⁇ indicates that the formation is satisfactory, ⁇ indicates that the formation is not so satisfactory, and X indicates that the formation is unsatisfactory.
- Item 3 represents the bonding strength between the bump and the inner liner, in which ⁇ indicates that reliable strength is obtained, ⁇ indicates that strength is slightly insufficient, and X indicates that strength is insufficient.
- Item 4 represents the comprehensive determination, in which ⁇ indicates that the reliable results are obtainable in the semiconductor device, ⁇ indicates that the slightly unreliable results are obtainable in the semiconductor device, and X indicates that the unreliable results are obtainable in the semiconductor device.
- the height of the most preferable height of the prominence is within a range of 1 ⁇ m to less than 5 ⁇ m.
- a height of the prominence of 0 ⁇ m to less than 1 ⁇ m is not substantially different from a flat face of the bump, and thus, advantages by providing the prominence are insufficient.
- a height of prominence of 5 pm or more results in a large distance between the base portion of the prominence and the inner lead.
- the melted Au/Sn eutectic alloy is not adhered to the vicinity of the base portion of the prominence and will not contribute to an improvement in bonding strength.
- the upper face of the bump of the semiconductor chip is roughened to form prominences. If the temperature and the pressure of the heating unit are set to be lower than those in conventional processes, sufficient bonding strength is achieved between the bump and the inner lead. Since the removal of the barrier metal and the roughening of the upper face of the bump are simultaneously performed, no additional step is required.
- a semiconductor device in accordance with the invention includes a tape substrate provided with a lead, and a semiconductor chip mounted onto the tape substrate by thermal welding a bump formed on an active face of the semiconductor chip with the lead.
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Abstract
A semiconductor device and a method for making the same, wherein bumps of a semiconductor chip and inner leads of a film tape carrier can be securely bonded to each other by thermal welding using a heating unit.
Description
- This is a Divisional of application Ser. No. 10/988,553, filed Nov. 16, 2004, which is a Divisional of application Ser. No. 10/445,188 filed May 27, 2003 (now U.S. Pat. No. 6,872,651), which is a Divisional of application Ser. No. 09/714,944 filed Nov. 20, 2000. The entire disclosure of the prior applications is hereby incorporated by reference herein in its entirety.
- 1. Field of Invention
- The present invention relates to a semiconductor device and a method for making the same, and particularly to a semiconductor chip mounted onto a tape substrate.
- 2. Description of Related Art
- In the field of semiconductor devices, tape carrier packages (TCPs) are well known as one type of bare-chip-mounted packages.
FIG. 5 is a schematic view of a film tape carrier. As shown inFIG. 5 , thefilm tape carrier 30 is generally formed by laminating a copper foil onto a polyimide resin film, forming a circuit onto the copper foil, and plating thereon using Sn or Au, as an oblong product before the product is processed together with semiconductor devices. The lead comprisesinner leads 20 bonded to an Au bump formed on an electrode pad of the semiconductor chip, andouter leads 36 integratedly formed with theinner leads 20 and used for connection to an exterior. - A method for making a TCP by a gang bonding process which simultaneously bonds all bumps to inner leads will now be described with reference to
FIG. 6 . A semiconductor chip is placed in a position surrounded by adevice hole 32 on a stage (not shown in the drawing), and each bump of the semiconductor chip and the corresponding inner lead are aligned so that they are exactly bonded to each other. As shown inFIG. 6 (1), aheating unit 52, which is preliminarily heated to about 500° C., is lowered toward the bumps and the inner leads 20 so that theheating unit 52 presses the bumps and the inner leads 20 on the stage. - The heat from the heating unit facilitates the formation of an Au/Sn
eutectic alloy 46 shown inFIG. 6 (2) by alloying the Au and the Sn plated on theinner leads 20. The mounting of thesemiconductor chip 40 onto thefilm tape carrier 30 is completed by bonding the bumps to theinner leads 20 via theeutectic alloy 46. Next, unnecessary portions of thefilm tape carrier 30 are removed by punching to prepare a TCP. - However, the bonding of the bumps to the inner leads of the semiconductor chip using the heating unit has the following problems.
-
FIG. 4 is a schematic view showing a problem which occurs during mounting a semiconductor chip by a conventional technique. As shown inFIG. 4 , abump 10 is formed on anelectrode pad 42 of asemiconductor chip 40. Since the periphery of theelectrode pad 42 is covered by apassivation film 44 and protrudes, thebump 10 formed on thepassivation film 44 also protrudes at the periphery and has an indented flat surface in the central portion. When theinner lead 20 is put into contact with thebump 10, agap 18 is formed between thebump 10 and theinner lead 20 due to the protrusion. Thus, the central portion of thebump 10 does not contribute to the bonding of thebump 10 to theinner lead 20, in this state. - With reference to
FIG. 6 (2), in conventional thermal welding between thebump 10 and theinner lead 20, a high load and a high temperature are applied by the heating unit so that the Au/Sneutectic alloy 46 is also formed in the central portion of thebump 10. - However, the application of the high load and the high temperature causes deforming and cracking of the inner lead and cracking of the passivation film. Such phenomena result in unreliability of the semiconductor devices as a product. Other problems, such as gas evolution from the film tape carrier and a shortened life of the heating unit, also arise.
- Accordingly, it is an object of the present invention to provide a semiconductor device and a method for making the same in which bumps of a semiconductor chip and leads of a tape substrate can be securely bonded to each other by thermal welding using a heating unit.
- The present invention includes a semiconductor device that includes a tape substrate provided with a lead, and a semiconductor chip mounted onto the tape substrate by thermal welding a bump formed on an active face of the semiconductor chip with the lead. The upper face of the bump is roughened.
- In the present invention having such a configuration, the upper face of the bump is roughened so that the surface area increases compared to a case of a flat upper face of the bump. Thus, the area contributing to the formation of an Au/Sn eutectic alloy increases and the melted eutectic alloy penetrates the gap between prominences by a capillary phenomenon, ensuring bonding between the bump and the lead. Thus, high load and high temperature are not required for bonding, and the occurrence of inner lead cracking can be prevented.
- In accordance with the above semiconductor device, prominences having a height of 1 to 5 μm are continuously formed on the upper face of the bump.
- In the present invention having such a configuration, the height of the prominences formed by roughening the upper face of the bump is controlled within a range which increases the surface area of the upper face of the bump so as to contribute to the formation of the Au/Sn eutectic alloy and to ensure sufficient bonding strength between the bump and the lead. Thus, thermal welding between the bump and the lead are ensured.
- It is preferable that the heights of the prominences on the upper face of the bump be the same so that the prominences securely come into contact with the lead to facilitate the formation of the Au/Sn eutectic alloy between the prominences and the lead.
- A method for making a semiconductor device that includes a tape substrate provided with a lead, and a semiconductor chip mounted onto the tape substrate by thermal welding a bump formed on an active face of the semiconductor chip with the lead, includes the steps of roughening the upper face of the bump, and thermally welding the bump to the lead.
- In the present invention having such a configuration, the bump and the lead are thermally welded after the upper face of the bump is roughened. Thus, the surface area can be increased compared to a case of a flat upper face of the bump. Thus, reliability of bonding between the bump and the lead can be enhanced.
- In accordance with the above method for making a semiconductor device, the step for roughening is performed while a barrier metal formed on a semiconductor wafer provided with the semiconductor chip is simultaneously removed.
- In the present invention having a such a configuration, the roughening step and the step for removing the barrier metal in the wafer process are simultaneously performed, and no additional process is required for roughening.
- In accordance with the method for making a semiconductor device, the roughening treatment is performed by etching the upper face of the bump with an iodide compound.
- In the present invention having a such a configuration, soft etching of the upper face of the bump is facilitated.
- In accordance with the method for making a semiconductor device, the iodine compound is potassium iodide or ammonium iodide.
- In the present invention having such a configuration, desired projections can be readily formed on the upper face of the bump.
-
FIG. 1 includes illustrative views of a method for making a semiconductor device in accordance with an embodiment of the present invention, whereinFIG. 1 (1) is an illustrative view of the semiconductor chip before roughening a bump of a semiconductor chip, andFIG. 1 (2) is an illustrative view after roughening. -
FIG. 2 is an illustrative view of a bump after roughening treatment. -
FIG. 3 is an illustrative chart showing the relationship between the height of the prominence and the bonding strength of the bump and the inner lead. -
FIG. 4 is a schematic view showing a problem which occurs during mounting of a semiconductor chip by a conventional technique. -
FIG. 5 is a schematic view of a film tape carrier. -
FIG. 6 includes illustrative views of a method for thermally welding a bump of a semiconductor chip to an inner lead of a film tape carrier, whereinFIG. 6 (1) is an illustrative view of a state of the bump and the inner lead before thermal welding, and -
FIG. 6 (2) is an illustrative view of a state of the bump and the inner lead after thermal welding. - The semiconductor device and the method for making the same in accordance with the present invention will now be described in detail based on the preferred embodiments with reference to the attached drawings. Parts corresponding to the parts described in the above conventional technology are referred to as the same reference numerals, and the description for these parts will be omitted. Moreover, descriptions, which are the same as those in the above conventional technology, will be simplified.
-
FIG. 1 includes illustrative views of a method for making a semiconductor device in accordance with an embodiment of the present invention, whereinFIG. 1 (1) is an illustrative view of the semiconductor chip before roughening a bump of a semiconductor chip, andFIG. 1 (2) is an illustrative view after roughening. Moreover,FIG. 2 is an illustrative view of a bump after roughening treatment.FIG. 3 is an illustrative chart showing the relationship between the height of the prominence and the bonding strength of the bump and the inner lead. - In this embodiment, prominences are formed on the upper face of the bump to increase the surface area of the upper face so that the Au/Sn eutectic alloy is readily formed by thermal welding using a gang bonding apparatus.
-
FIG. 1 (1) shows a halfway stage of the wafer process. Apassivation film 44 is formed on asemiconductor wafer 50 that is provided with a semiconductor chip in a region other than anelectrode pad 42. Abarrier metal layer 48 is formed over thepassivation film 44 and theelectrode pad 42 above theentire semiconductor wafer 50. Thebarrier metal layer 48 includes two sub-layers. That is, aTiW sub-layer 48 a is formed by sputtering on thepassivation film 44, and then anAu sub-layer 48 b is formed by plating on theTiW sub-layer 48 a. - Next, a
bump 10 is formed on theelectrode pad 42. Thebump 10 is formed by applying a photoresist on the entire surface of thesemiconductor wafer 50, and by removing the photoresist in a bump-forming portion by exposure and development to form an opening, and then by plating Au in the opening. The upper face of thebump 10 in this stage is slightly indented in the central portion, as described above with reference toFIG. 3 . - In this embodiment, the
semiconductor wafer 50 is etched using a potassium iodide or ammonium iodide solution. The etching, as shown inFIG. 1 (2), removes thebarrier metal layer 48 and roughens the upper face of thebump 10 to formmany prominences 12. The surface area of thebump 10 significantly increases compared to the surface area before etching. The difference in height between the periphery and the central portion of thebump 10 is considerably decreased due to the formation of theprominences 12. - When the
bump 10 and theinner lead 20 are thermally welded using theheating unit 52, as shown inFIG. 6 (1), the area contributing to the formation of the Au/Sn eutectic alloy significantly increases, and the formation of the eutectic alloy is facilitated. In addition, the melt eutectic alloy penetrates the gap of theprominences 12 by a capillary phenomenon and adheres onto sloping faces 14 of theprominences 12 so as to enhance the bonding between thebump 10 and theinner lead 20. Thus, the bonding between thebump 10 and theinner lead 20 can be ensured even if theheating unit 52 is set at a lower temperature compared to conventional temperatures. Moreover, the difference in the height on the upper face of thebump 10 is considerably decreased. Hence, the pressure of theheating unit 52 can be reduced compared to the conventional cases. - The etching solution may be a solution containing an iodine compound or any compound other than potassium iodide and ammonium iodide, as long as the solution exhibits etching ability. Instead of Au, the
bump 10 may be formed of any material, such as Ni, in which Au is adhered to the surface of the prominence. Theprominences 12 may be formed by a mechanical process, if possible, for example, by pressing the upper face of thebump 10 using a tool having an uneven surface or by buffing the upper face of thebump 10 using such a tool. According to the mechanical process, the heights of the prominences can be controlled within a predetermined range, and the formation of the Au/Sn eutectic alloy is further facilitated for the reasons described below. - The height of the
prominence 12 depends on the type of the etching solution used and the etching time. As shown inFIG. 2 , individual heights are also different, as shown by thelowest prominence 12 a and thehighest prominence 12 b. It is preferable that the difference in the height be small as much as possible, because the formation of the An/Sn eutectic alloy is promoted in proportion to the contact area during thermal welding between the bump and the inner lead. In the case of a large difference in the height of theprominences 12, prominences having lower heights are still distant from the inner lead and thus do not contribute to the formation of the Au/Sn eutectic alloy, even when the inner lead is pressed by the heating unit. - Experimental results have been prepared regarding the heights of the
prominences 12, wherein the height A of the lowest prominence is 1 μm or more, and the height B of the highest prominence is less than 5 μm. The experimental results will now be described. - The present inventor has performed experiments regarding the relationship between the heights of the prominences and the bonding strength of the bump and the inner lead, and has obtained the data confirming the effects. The results will now be described based on
FIG. 3 . -
Term 1 in the table represents the surface roughness of the bump, that is, the heights of the prominences on the upper face of the bump. The description “0 to less than 1” represents all the heights of the prominences lie within the range of 0 to 1.Term 2 represents the state of the formation of the Au/Sn eutectic alloy, in which ◯ indicates that the formation is satisfactory, Δ indicates that the formation is not so satisfactory, and X indicates that the formation is unsatisfactory.Item 3 represents the bonding strength between the bump and the inner liner, in which ◯ indicates that reliable strength is obtained, Δ indicates that strength is slightly insufficient, and X indicates that strength is insufficient.Item 4 represents the comprehensive determination, in which ◯ indicates that the reliable results are obtainable in the semiconductor device, Δ indicates that the slightly unreliable results are obtainable in the semiconductor device, and X indicates that the unreliable results are obtainable in the semiconductor device. - As shown in chart, the height of the most preferable height of the prominence is within a range of 1 μm to less than 5 μm. A height of the prominence of 0 μm to less than 1 μm is not substantially different from a flat face of the bump, and thus, advantages by providing the prominence are insufficient. A height of prominence of 5 pm or more results in a large distance between the base portion of the prominence and the inner lead. Thus, the melted Au/Sn eutectic alloy is not adhered to the vicinity of the base portion of the prominence and will not contribute to an improvement in bonding strength.
- As described above, in the semiconductor device and the method for making the same in accordance with the embodiments of the present invention, the upper face of the bump of the semiconductor chip is roughened to form prominences. If the temperature and the pressure of the heating unit are set to be lower than those in conventional processes, sufficient bonding strength is achieved between the bump and the inner lead. Since the removal of the barrier metal and the roughening of the upper face of the bump are simultaneously performed, no additional step is required.
- As described above, a semiconductor device in accordance with the invention includes a tape substrate provided with a lead, and a semiconductor chip mounted onto the tape substrate by thermal welding a bump formed on an active face of the semiconductor chip with the lead. Thus, reliability of the bonding between the semiconductor chip and the tape substrate can be significantly improved by a simplified treatment in a wafer process. Accordingly, the production cost of the semiconductor device can be reduced.
Claims (19)
1. A semiconductor chip, comprising:
an electrode pad; and
a bump having a first face where a plurality of prominences are formed and a second face.
2. The semiconductor chip according to claim 1 ,
the electrode pad being electrically connected to the bump through the second face.
3. The semiconductor chip according to claim 1 ,
the plurality of prominences including a plurality of first prominences formed in a first area of the first face that overlaps the electrode pad.
4. The semiconductor chip according to claim 3 ,
the plurality of prominences further including a plurality of second prominences formed on a second area of the first face that is located between the first area and an outer circumference of the first face.
5. The semiconductor chip according to claim 1 ,
the first face to be connected to a tape substrate.
6. The semiconductor chip according to claim 1 , further comprising:
at least one metal layer between the electrode pad and the second face.
7. The semiconductor chip according to claim 1 , further comprising:
a passivation film that covers a part of the electrode pad.
8. The semiconductor chip according to claim 4 , further comprising:
a passivation film that covers an outer circumference of the electrode pad, the passivation film overlapping the second area.
9. The semiconductor chip according to claim 7 ,
the passivation film covering the outer circumference of the electrode pad.
10. The semiconductor chip according to claim 1 ,
the plurality of prominences having heights ranging from 1 μm to 3 μm.
11. The semiconductor chip according to claim 1 , further comprising:
a semiconductor element,
the semiconductor element being connected to the electrode pad.
12. The semiconductor chip according to claim 11 ,
the semiconductor element being formed in a silicon wafer.
13. A semiconductor device, comprising:
the semiconductor chip according to claim 1; and
a tape substrate.
14. A semiconductor device, comprising:
the semiconductor chip according to claim 3; and
a tape substrate.
15. A semiconductor device, comprising:
a semiconductor element;
an electrode pad connected to the semiconductor element;
a bump having a first face where a plurality of prominences are formed and a second face; and
a tape substrate that is connected to the bump through the first face.
16. The semiconductor device according to claim 15 ,
the tape substrate including a lead that contacts the first face.
17. The semiconductor device according to claim 15 ,
the tape substrate being connected to the bump through a metal layer disposed between the first face and the tape substrate.
18. The semiconductor device according to claim 17 ,
the metal layer including a metal alloy.
19. The semiconductor chip according to claim 1 ,
the first face being roughed.
Priority Applications (1)
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US11/798,506 US20070267744A1 (en) | 1999-11-18 | 2007-05-14 | Manufacturing a bump electrode with roughened face |
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
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JP32846799A JP2001148401A (en) | 1999-11-18 | 1999-11-18 | Semiconductor device and method of manufacturing therefor |
JP11-328467 | 1999-11-18 | ||
US71494400A | 2000-11-20 | 2000-11-20 | |
US10/445,188 US6872651B2 (en) | 1999-11-18 | 2003-05-27 | Manufacturing a bump electrode with roughened face |
US10/988,553 US7233067B2 (en) | 1999-11-18 | 2004-11-16 | Manufacturing a bump electrode with roughened face |
US11/798,506 US20070267744A1 (en) | 1999-11-18 | 2007-05-14 | Manufacturing a bump electrode with roughened face |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US10/988,553 Division US7233067B2 (en) | 1999-11-18 | 2004-11-16 | Manufacturing a bump electrode with roughened face |
Publications (1)
Publication Number | Publication Date |
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US20070267744A1 true US20070267744A1 (en) | 2007-11-22 |
Family
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Family Applications (3)
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US10/445,188 Expired - Fee Related US6872651B2 (en) | 1999-11-18 | 2003-05-27 | Manufacturing a bump electrode with roughened face |
US10/988,553 Expired - Fee Related US7233067B2 (en) | 1999-11-18 | 2004-11-16 | Manufacturing a bump electrode with roughened face |
US11/798,506 Abandoned US20070267744A1 (en) | 1999-11-18 | 2007-05-14 | Manufacturing a bump electrode with roughened face |
Family Applications Before (2)
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US10/445,188 Expired - Fee Related US6872651B2 (en) | 1999-11-18 | 2003-05-27 | Manufacturing a bump electrode with roughened face |
US10/988,553 Expired - Fee Related US7233067B2 (en) | 1999-11-18 | 2004-11-16 | Manufacturing a bump electrode with roughened face |
Country Status (2)
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US (3) | US6872651B2 (en) |
JP (1) | JP2001148401A (en) |
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DE102010005465B4 (en) * | 2009-01-26 | 2014-11-20 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Electrical or electronic component and method for making a connection |
US7863743B1 (en) * | 2009-06-30 | 2011-01-04 | Oracle America, Inc. | Capactive connectors with enhanced capacitive coupling |
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JP6347781B2 (en) * | 2012-08-10 | 2018-06-27 | スマートラック・テクノロジー・ゲゼルシャフト・ミット・ベシュレンクテル・ハフツングSmartrac Technology Gmbh | Contact bump connections, contact bumps, and methods for making contact bump connections |
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JPH0870019A (en) | 1994-08-30 | 1996-03-12 | Casio Comput Co Ltd | Connector structure of electronic parts and connection thereof |
JPH11111761A (en) | 1997-10-08 | 1999-04-23 | Fujitsu Ltd | Packaged semiconductor chip parts |
-
1999
- 1999-11-18 JP JP32846799A patent/JP2001148401A/en not_active Withdrawn
-
2003
- 2003-05-27 US US10/445,188 patent/US6872651B2/en not_active Expired - Fee Related
-
2004
- 2004-11-16 US US10/988,553 patent/US7233067B2/en not_active Expired - Fee Related
-
2007
- 2007-05-14 US US11/798,506 patent/US20070267744A1/en not_active Abandoned
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US4786545A (en) * | 1986-02-28 | 1988-11-22 | Seiko Epson Corporation | Circuit substrate and method for forming bumps on the circuit substrate |
US5108950A (en) * | 1987-11-18 | 1992-04-28 | Casio Computer Co., Ltd. | Method for forming a bump electrode for a semiconductor device |
US5487999A (en) * | 1991-06-04 | 1996-01-30 | Micron Technology, Inc. | Method for fabricating a penetration limited contact having a rough textured surface |
US5545589A (en) * | 1993-01-28 | 1996-08-13 | Matsushita Electric Industrial Co., Ltd. | Method of forming a bump having a rugged side, a semiconductor device having the bump, and a method of mounting a semiconductor unit and a semiconductor device |
US6088236A (en) * | 1993-01-28 | 2000-07-11 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device having a bump having a rugged side |
US6165820A (en) * | 1994-12-22 | 2000-12-26 | Pace; Benedict G. | Package for electronic devices |
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US6157079A (en) * | 1997-11-10 | 2000-12-05 | Citizen Watch Co., Ltd | Semiconductor device with a bump including a bump electrode film covering a projecting photoresist |
US6109507A (en) * | 1997-11-11 | 2000-08-29 | Fujitsu Limited | Method of forming solder bumps and method of forming preformed solder bumps |
US6288559B1 (en) * | 1998-03-30 | 2001-09-11 | International Business Machines Corporation | Semiconductor testing using electrically conductive adhesives |
US20030019917A1 (en) * | 1998-09-17 | 2003-01-30 | Kabushiki Kaisha Tamura Seisakusho | Bump forming method, presoldering treatment method, soldering method, bump forming apparatus, presoldering treatment device and soldering apparatus |
US6742701B2 (en) * | 1998-09-17 | 2004-06-01 | Kabushiki Kaisha Tamura Seisakusho | Bump forming method, presoldering treatment method, soldering method, bump forming apparatus, presoldering treatment device and soldering apparatus |
US6872651B2 (en) * | 1999-11-18 | 2005-03-29 | Seiko Epson Corporation | Manufacturing a bump electrode with roughened face |
US7233067B2 (en) * | 1999-11-18 | 2007-06-19 | Seiko Epson Corporation | Manufacturing a bump electrode with roughened face |
US6406991B2 (en) * | 1999-12-27 | 2002-06-18 | Hoya Corporation | Method of manufacturing a contact element and a multi-layered wiring substrate, and wafer batch contact board |
US6853074B2 (en) * | 1999-12-27 | 2005-02-08 | Matsushita Electric Industrial Co., Ltd. | Electronic part, an electronic part mounting element and a process for manufacturing such the articles |
Also Published As
Publication number | Publication date |
---|---|
JP2001148401A (en) | 2001-05-29 |
US7233067B2 (en) | 2007-06-19 |
US20050062158A1 (en) | 2005-03-24 |
US20040004273A1 (en) | 2004-01-08 |
US6872651B2 (en) | 2005-03-29 |
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