US20070187839A1 - Integrated circuit package system with heat sink - Google Patents
Integrated circuit package system with heat sink Download PDFInfo
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- US20070187839A1 US20070187839A1 US11/307,683 US30768306A US2007187839A1 US 20070187839 A1 US20070187839 A1 US 20070187839A1 US 30768306 A US30768306 A US 30768306A US 2007187839 A1 US2007187839 A1 US 2007187839A1
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- heat sink
- integrated circuit
- circuit die
- molding compound
- external interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4334—Auxiliary members in encapsulations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
- The present invention relates generally to integrated circuit packages and more particularly to integrated circuit packages with heat sinks.
- Consumer electronics requirements demand more integrated circuits in an integrated circuit package while paradoxically providing less physical space in the system for the increased integrated circuits content. Some technologies primarily focus on integrating more functions into each integrated circuit. Other technologies focus on stacking these integrated circuits into a single package. As more functions are packed into the integrated circuits and more integrated circuits into the package, more heat is generated degrading the performance and potentially the reliability of the integrated circuits. While these approaches provide more functions within an integrated circuit, they do not fully address the requirements for lower height, smaller space, heat dissipation, and cost reduction.
- Modern consumer electronics, such as smart phones, personal digital assistants, and location based services devices, are packing more integrated circuits into an ever shrinking physical space with expectations for decreasing cost. Contemporary consumer electronics expose integrated circuits and packages to more demanding and sometimes new environmental conditions, such as cold, heat, and humidity requiring integrated circuit packages to provide robust thermal management structures. Numerous technologies have been developed to meet these requirements. Some of the research and development strategies focus on new package technologies while others focus on improving the existing and mature package technologies. Research and development in the existing package technologies may take a myriad of different directions.
- One proven way to reduce cost is to use mature package technologies with existing manufacturing methods and equipments. Paradoxically, the reuse of existing manufacturing processes does not typically result in the reduction of package dimensions. Existing packaging technologies struggle to cost effectively meet the ever demanding thermal requirements of today's integrated circuits and packages.
- Thus, a need still remains for an integrated circuit package system providing low cost manufacturing, improved thermal performance, and reduce the integrated circuit package dimensions. In view of the ever-increasing need to save costs and improve efficiencies, it is more and more critical that answers be found to these problems.
- Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.
- The present invention provides an integrated circuit package system including forming an external interconnect from a padless lead frame, encapsulating a heat sink and the external interconnect, mounting an integrated circuit die on the heat sink, and encapsulating the integrated circuit die, the heat sink, and the external interconnect.
- Certain embodiments of the invention have other aspects in addition to or in place of those mentioned or obvious from the above. The aspects will become apparent to those skilled in the art from a reading of the following detailed description when taken with reference to the accompanying drawings.
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FIG. 1 is a cross-sectional view of a first integrated circuit package system in an embodiment of the present invention; -
FIG. 2 is a cross-sectional view of a second integrated circuit package system in an alternative embodiment of the present invention; -
FIG. 3 is a cross-sectional view of the first integrated circuit package system in a mounting phase of the heat sink; -
FIG. 4 is a cross-sectional view of the first integrated circuit package system in a first encapsulation phase with the first molding compound; -
FIG. 5 is a cross-sectional view of the first integrated circuit package system in an attachment phase of the integrated circuit die; -
FIG. 6 is a cross-sectional view of the first integrated circuit package system in a second encapsulation phase with the second molding compound; -
FIG. 7 is a cross-sectional view of the second integrated circuit package system in a mounting phase of the heat sink; -
FIG. 8 is a cross-sectional view of the second integrated circuit package system in a first encapsulation phase with the first molding compound; -
FIG. 9 is a cross-sectional view of the second integrated circuit package system in an attachment phase of the integrated circuit die; -
FIG. 10 is a cross-sectional view of the second integrated circuit package system in a second encapsulation phase with the second molding compound; and -
FIG. 11 is a flow chart of an integrated circuit package system for manufacture of the integrated circuit package system in an embodiment of the present invention. - In the following description, numerous specific details are given to provide a thorough understanding of the invention. However, it will be apparent that the invention may be practiced without these specific details. In order to avoid obscuring the present invention, some well-known system configurations, and process steps are not disclosed in detail. Likewise, the drawings showing embodiments of the apparatus are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and are shown greatly exaggerated in the figures. The same numbers are used in all the figures to relate to the same elements.
- The term “horizontal” as used herein is defined as a plane parallel to the conventional integrated circuit surface, regardless of its orientation. The term “vertical” refers to a direction perpendicular to the horizontal as just defined. Terms, such as “on”, “above”, “below”, “bottom”, “top”, “side”(as in “sidewall”), “higher”, “lower”, “upper”, “over”, and “under”, are defined with respect to the horizontal plane.
- The term “processing” as used herein includes deposition of material, patterning, exposure, development, etching, cleaning, molding, and/or removal of the material or as required in forming a described structure.
- Referring now to
FIG. 1 , therein is shown a cross-sectional view of a first integratedcircuit package system 100 in an embodiment of the present invention. The first integratedcircuit package system 100 includes an integrated circuit die 102, such as a wire bond integrated circuit, on aheat sink 104 with an adhesive 106, such as a thermally conductive adhesive, in between. The integrated circuit die 102 connects toexternal interconnects 108, such as leads of a padless lead frame (not shown), withelectrical interconnects 110, such as bond wires. - A
first molding compound 112, such as an epoxy molding compound, encapsulates theheat sink 104, with abottom surface 114 of theheat sink 104 may be exposed, and an inner portion of theexternal interconnects 108 from abottom 116 of theexternal interconnects 108. Theheat sink 104 is within the center of the padless lead frame not contacting theexternal interconnects 108. Asecond molding compound 118, such as an epoxy molding compound, encapsulates theintegrated circuit die 102, theelectrical interconnects 110, and the inner portion of theexternal interconnects 108 from atop 120 of theexternal interconnects 108. - For illustrative purpose, heights of the
first molding compound 112 and thesecond molding compound 118 from theexternal interconnects 108 are shown as substantially the same, although it is understood that the heights may differ. Also for illustrative purpose, thefirst molding compound 112 and thesecond molding compound 118 as shown as different, although it is understood that thefirst molding compound 112 and thesecond molding compound 118 may not be different. - The
heat sink 104 serves as a die paddle with beveled sides from a top and the bottom of theheat sink 104 forming aregistration 122, such as a protrusion or a mold interlock, at a mid section of theheat sink 104. Theregistration 122 anchors theheat sink 104 in thefirst molding compound 112. Theregistration 122 as well as the beveled top and bottom of theheat sink 104 do not contact theexternal interconnects 108 avoiding inadvertent electrical connections. For illustrative purpose, theheat sink 104 is shown with theregistration 122, although it is understood that theheat sink 104 may be a different shape, such as a trapezoid, and may optional have a mold interlock feature. - An
interconnect height 124 of theexternal interconnects 108 exceeds asink thickness 126 of theheat sink 104 and the height of thefirst molding compound 112 such that theheat sink 104 and thefirst molding compound 112 do not impede connections of theexternal interconnects 108 to the next system level (not shown), such as a printed circuit board. - The
heat sink 104 provides a thermal conduction path for the heat to flow from theintegrated circuit die 102. Theheat sink 104 in thefirst molding compound 112 does not increase the size or outline of the first integratedcircuit package system 100 allowing re-use of existing manufacturing equipments. - Referring now to
FIG. 2 , therein is shown a cross-sectional view of a second integratedcircuit package system 200 in an alternative embodiment of the present invention. The second integratedcircuit package system 200 includes anintegrated circuit die 202, such as a wire bond integrated circuit, on arecess 204 of aheat sink 206 with an adhesive 208, such as a thermally conductive adhesive, in between. Theintegrated circuit die 202 connects toexternal interconnects 210, such as leads of a lead frame (not shown), withelectrical interconnects 212, such as bond wires. - A
first molding compound 214, such as an epoxy molding compound, encapsulates theheat sink 206, with abottom surface 216 of theheat sink 206 may be exposed, and an inner portion of theexternal interconnects 210 from abottom 218 of theexternal interconnects 210. Theheat sink 206 is within the center of the padless lead frame not contacting theexternal interconnects 210. Asecond molding compound 220, such as an epoxy molding compound, encapsulates the integrated circuit die 202, theelectrical interconnects 212, and the inner portion of theexternal interconnects 210 from a top 222 of theexternal interconnects 210. Thesecond molding compound 220 fills therecess 204 to surround the integrated circuit die 202. - For illustrative purpose, heights of the
first molding compound 214 and thesecond molding compound 220 from theexternal interconnects 210 are shown as substantially the same, although it is understood that the heights may differ. Also for illustrative purpose, thefirst molding compound 214 and thesecond molding compound 220 as shown as different, although it is understood that thefirst molding compound 214 and thesecond molding compound 220 may not be different. - The
recess 204 serves as a die paddle and lowers the integrated circuit die 202 resulting in a lower height or profile of the second integratedcircuit package system 200. Therecess 204 also shortens lengths of theelectrical interconnects 212 resulting in improved electrical performance and smaller wire loops for improved electrical connection reliability. - The
heat sink 206 has beveled sides from a top and a bottom of theheat sink 206 forming aregistration 224, such as a protrusion or a mold interlock, at a mid section of theheat sink 206. Theregistration 224 anchors theheat sink 206 in thesecond molding compound 220. Theregistration 224 as well as the beveled top and bottom of theheat sink 206 do not contact the external interconnects 21 0 avoiding inadvertent electrical connections. For illustrative purpose, theheat sink 206 is shown with theregistration 224, although it is understood that theheat sink 206 may be a different shape, such as a trapezoid, and may optional have a mold interlock feature. - An
interconnect height 226 of theexternal interconnects 210 exceeds asink thickness 228 of theheat sink 206 and the height of thesecond molding compound 220 such that theheat sink 206 and thesecond molding compound 220 do not impede connections of theexternal interconnects 210 to the next system level (not shown), such as a printed circuit board. - The
heat sink 206 provides a thermal conduction path for the heat to flow from the integrated circuit die 202. Theheat sink 206 in thefirst molding compound 214 does not increase the size or outline of the second integratedcircuit package system 200 allowing re-use of existing manufacturing equipments. - Referring now to
FIG. 3 , therein is shown a cross-sectional view of the first integratedcircuit package system 100 in a mounting phase of theheat sink 104. Acoverlay tape 302 attaches to the top 120 of theexternal interconnects 108. Theheat sink 104 attaches to thecoverlay tape 302. Theheat sink 104 may be picked and placed on thecoverlay tape 302 for an adhesiveless attachment or may be provided pre-attached by a lead frame supplier. Theheat sink 104 does not contact theexternal interconnects 108 avoiding inadvertent connections. - Referring now to
FIG. 4 , therein is shown a cross-sectional view of the first integratedcircuit package system 100 in a first encapsulation phase with thefirst molding compound 112. Thefirst molding compound 112 encapsulates theheat sink 104 with theregistration 122 acting as an anchor. Thefirst molding compound 112 encapsulates the inner portion of theexternal interconnects 108 from the bottom 116. Thebottom surface 114 of theheat sink 104 may be exposed with a number of processes, such as chemical and mechanical planarization (CMP). An optional post-mold deflash process, such as a mechanical or chemical deflash, may be performed to eliminate resin bleeds and mold flash on theheat sink 104 and wire bonding surfaces on theexternal interconnects 108. Theheat sink 104 within thefirst molding compound 112 eliminates the need for epoxy paste dispensing and curing for the attachment of theheat sink 104. Thecoverlay tape 302 is removed from the structure for further processing. For illustrative purpose, thecoverlay tape 302 is shown as curled from the removing action, such as peeling, although it is understood that thecoverlay tape 302 is typically planar next to theheat sink 104, theexternal interconnects 108, and thefirst molding compound 112. - Referring now to
FIG. 5 , therein is shown a cross-sectional view of the first integratedcircuit package system 100 in an attachment phase of the integrated circuit die 102. The integrated circuit die 1 02 attaches to theheat sink 104 with the adhesive 106. Theelectrical interconnects 110 connect the integrated circuit die 102 and the inner portion of theexternal interconnects 108. Theheat sink 104 is exposed such that theheat sink 104 may be used to conduct heat for an attachment process, such as wire bonding, theelectrical interconnects 110 to the integrated circuit die 102. - Referring now to
FIG. 6 , therein is shown a cross-sectional view of the first integratedcircuit package system 100 in a second encapsulation phase with thesecond molding compound 118. Thesecond molding compound 118 encapsulates the integrated circuit die 102, theelectrical interconnects 110, and the inner portion of theexternal interconnects 108 from the top 120. Thefirst molding compound 112 and thesecond molding compound 118 attach forming a hermetic seal protecting the integrated circuit die 102 and theelectrical interconnects 110 as well as theheat sink 104 without requiring additional structure or space for theheat sink 104. - Referring now to
FIG. 7 , therein is shown a cross-sectional view of the second integratedcircuit package system 200 in a mounting phase of theheat sink 206. Thecoverlay tape 302 attaches to the top 222 of theexternal interconnects 210. Theheat sink 206 attaches to thecoverlay tape 302. Theheat sink 206 may be picked and placed on thecoverlay tape 302 for an adhesiveless attachment or may be provided pre-attached by a lead frame supplier. Theheat sink 206 does not contact theexternal interconnects 210 avoiding inadvertent connections. - Referring now to
FIG. 8 , therein is shown cross-sectional view of the second integrated circuit package system in 200 a first encapsulation phase with thefirst molding compound 214. Thefirst molding compound 214 encapsulates theheat sink 206 with theregistration 224 acting as the anchor with thecoverlay tape 302 preventing thefirst molding compound 214 from filling therecess 204. Thefirst molding compound 214 encapsulates the inner portion of theexternal interconnects 210 from the bottom 218. Thebottom surface 216 of theheat sink 206 may be exposed with a number of processes, such as chemical and mechanical planarization (CMP). An optional post-mold deflash process, such as a mechanical or chemical deflash, may be performed to eliminate resin bleeds and mold flash on theheat sink 206 and wire bonding surfaces on theexternal interconnects 210. Theheat sink 206 within thefirst molding compound 214 eliminates the need for epoxy paste dispensing and curing for the attachment of theheat sink 206. Thecoverlay tape 302 is removed from the structure for further processing. For illustrative purpose, thecoverlay tape 302 is shown as curled from the removing action, such as peeling, although it is understood that thecoverlay tape 302 is typically planar next to theheat sink 206, theexternal interconnects 210, and thefirst molding compound 214. - Referring now to
FIG. 9 , therein is shown a cross-sectional view of the second integratedcircuit package system 200 in an attachment phase of the integrated circuit die 202. The integrated circuit die 202 attaches to theheat sink 206 with the adhesive 208. Theelectrical interconnects 212 connect the integrated circuit die 202 and the inner portion of theexternal interconnects 210. Theheat sink 206 is exposed such that theheat sink 206 may be used to conduct heat for an attachment process, such as wire bonding, theelectrical interconnects 212 to the integrated circuit die 202. - Referring now to
FIG. 10 , therein is shown a cross-sectional view of the second integratedcircuit package system 200 in a second encapsulation phase with thesecond molding compound 220. Thesecond molding compound 220 encapsulates the integrated circuit die 202, theelectrical interconnects 212, and the inner portion of theexternal interconnects 210 from the top 222. Thesecond molding compound 220 also fills therecess 802 around the integrated circuit die 202. Thefirst molding compound 214 and thesecond molding compound 220 attach forming a hermetic seal protecting the integrated circuit die 202 and theelectrical interconnects 212 as well as theheat sink 206 without requiring additional structure or space for theheat sink 206. - Referring now to
FIG. 11 , therein is shown a flow chart of an integratedcircuit package system 1100 for manufacture of the first integratedcircuit package system 100 in an embodiment of the present invention. Thesystem 1100 includes forming an external interconnect from a padless lead frame in ablock 1102; encapsulating a heat sink and the external interconnect in ablock 1104; mounting an integrated circuit die on the heat sink in ablock 1106; and encapsulating the integrated circuit die, the heat sink, and the external interconnect in ablock 1108. - It has been discovered that the present invention thus has numerous aspects.
- It has been discovered that the integrated circuit package system provides a low cost manufacturing solution by simplifying handling methods, simplifying some manufacturing equipment design, alleviates and eliminates other causes that may result in potential yield issues. The two-step molding process encapsulates the heat sink providing improved thermal performance while providing low package height and maintaining package dimensions similar to high volume standard dimensions to keep the cost down.
- An aspect is that the present invention provides two-step molding of the integrated circuit package, such as leaded QFP or QLP packages, encasing the integrated circuit die, wire interconnects connecting the integrated circuit die to the integrated circuit package leads or pins, and the heat sink without additional structures or space required for the heat sink. The packaging manufacturing process allows the heat sink to be attached and held in place with the molding compound without an adhesive to hold the heat sink. Epoxy paste dispensing and curing to attach the heat sink have been eliminated to simplify the manufacturing process. The heat sink may be pre-attached to the lead frame by the lead frame supplier to simplify the manufacturing process.
- Another aspect of the present invention is that the integrated circuit package resulting from the two-step molding process provides the heat sink as the die paddle for the integrated circuit die. The heat sink attachment with the integrated circuit provides an improved thermal dissipation characteristic from the integrated circuit die for an improved thermal performance of the integrated circuit package. The heat sink may also be used to conduct heat for attaching the bond wires to the integrated circuit die.
- Yet another aspect of the present invention is that the recess of the heat sink offers a low profile packaging solution with the improved thermal performance. The recess also improves the electrical performance and wire bonding yield from the shortened bond wires with the integrated circuit die closer to the bonding sites of the leads.
- Yet another important aspect of the present invention is that it valuably supports and services the historical trend of reducing costs and increasing performance. These and other valuable aspects of the present invention consequently further the state of the technology to at least the next level.
- Thus, it has been discovered that the integrated circuit package system method of the present invention furnishes important and heretofore unknown and unavailable solutions, capabilities, and functional aspects for increasing chip density in systems. The resulting processes and configurations are straightforward, cost-effective, uncomplicated, highly versatile and effective, can be implemented by adapting known technologies, and are thus readily suited for efficiently and economically manufacturing stacked integrated circuit packaged devices.
- While the invention has been described in conjunction with a specific best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the aforegoing description. Accordingly, it is intended to embrace all such alternatives, modifications, and variations that fall within the scope of the included claims. All matters hithertofore set forth herein or shown in the accompanying drawings are to be interpreted in an illustrative and non-limiting sense.
Claims (20)
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US11/307,683 US7400049B2 (en) | 2006-02-16 | 2006-02-16 | Integrated circuit package system with heat sink |
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US11/307,683 US7400049B2 (en) | 2006-02-16 | 2006-02-16 | Integrated circuit package system with heat sink |
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US20080142938A1 (en) * | 2006-12-13 | 2008-06-19 | Stats Chippac Ltd. | Integrated circuit package system employing a support structure with a recess |
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US20090230519A1 (en) * | 2008-03-14 | 2009-09-17 | Infineon Technologies Ag | Semiconductor Device |
US8598602B2 (en) * | 2009-01-12 | 2013-12-03 | Cree, Inc. | Light emitting device packages with improved heat transfer |
US7923739B2 (en) | 2009-06-05 | 2011-04-12 | Cree, Inc. | Solid state lighting device |
US8415204B2 (en) * | 2009-03-26 | 2013-04-09 | Stats Chippac Ltd. | Integrated circuit packaging system with heat spreader and method of manufacture thereof |
US8133759B2 (en) * | 2009-04-28 | 2012-03-13 | Macronix International Co., Ltd. | Leadframe |
US8686445B1 (en) | 2009-06-05 | 2014-04-01 | Cree, Inc. | Solid state lighting devices and methods |
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