US20070187838A1 - Pad structure for bonding pad and probe pad and manufacturing method thereof - Google Patents

Pad structure for bonding pad and probe pad and manufacturing method thereof Download PDF

Info

Publication number
US20070187838A1
US20070187838A1 US11/691,606 US69160607A US2007187838A1 US 20070187838 A1 US20070187838 A1 US 20070187838A1 US 69160607 A US69160607 A US 69160607A US 2007187838 A1 US2007187838 A1 US 2007187838A1
Authority
US
United States
Prior art keywords
mark
pad
bonding
shaped
bonding pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/691,606
Inventor
Shu-Liang Nin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nanya Technology Corp
Original Assignee
Nanya Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanya Technology Corp filed Critical Nanya Technology Corp
Priority to US11/691,606 priority Critical patent/US20070187838A1/en
Publication of US20070187838A1 publication Critical patent/US20070187838A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H01L2223/5446—Located in scribe lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/5448—Located on chip prior to dicing and remaining on chip after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0605—Shape
    • H01L2224/06051—Bonding areas having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Automation & Control Theory (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

A mark-shaped pad. A bonding pad structure with at least one mark-shaped bonding pad comprises: a bottom metal layer disposed over the surface of a rectangular semiconductor substrate to connect the circuit electrically, an inter-metal dielectric layer disposed over the bottom metal layer, metal plugs formed in the inter-metal dielectric layer to connect with the bottom metal layer, a top metal layer disposed over the inter-metal dielectric layer connecting with the metal plugs, and a passivation layer disposed over the top metal layer with openings to expose the top metal layer portions as bonding pads, wherein at least one bonding pad is mark-shaped, e.g.
Figure US20070187838A1-20070816-P00001
,
Figure US20070187838A1-20070816-P00002
,
Figure US20070187838A1-20070816-P00003
or

Description

    FIELD OF THE INVENTION
  • The present invention relates to an integrated circuit device structure, and more particularly to a mark-shaped pad structure for a bonding pad and a probe pad.
    • BACKGROUND OF THE INVENTION
  • After integrated circuits are formed on a semiconductor wafer, the top metal layer is defined as a plurality of bonding pads to form a multi-layered wiring with the metal lines below. The wafer is then cut into dies for further IC chip electronic packaging.
  • In the electronic packaging of an IC chip, the dies cut from the wafer are bonded to a lead frame with a bonder, and the bonding pads on the IC chip are electrically connected with corresponding electrical leads on the lead frame by wire bonding. In other words, the bonding pads on IC chips are the interface between the integrated circuits on the semiconductor substrate and the packaging leads on the lead frame to connect electrical signals. The electrical signals can be power signals, ground signals, and/or input/output signals.
  • Conventionally, the active devices, e.g., MOS transistors or resistances, are laid on the central area (active area) of an IC chip and bonding pads are disposed around the active area to protect the active devices on the active area from damage during wire bonding. In some cases, bonding pads are laid on the central area of IC chip and active devices are disposed around the bonding pads for the same reason.
  • The conventional shape of a bonding pad is a square or a rectangle. FIG. 1 shows a conventional die array on a wafer. There are scribe lines 16 on a wafer 10 to define several die areas, e.g. 12A and 12B, and the wafer 10 is cut into dies along the scribe lines 16. There are alignment markers (e.g. 14A-14C) disposed at corners of the die areas 12A and 12B on the scribe lines 16 for cutting alignment. For the intact die area 12A, the dicing machine cuts the die area 12A from the wafer 10 by aligning with the markers 14A and 14B which are disposed along the diagonal line of area 12A. However, for the fragmental die area 12B, there is no corresponding diagonal markers on scribe lines for alignment, and therefore, there is difficulty cutting die area 12B.
  • FIGS. 2A and 2B show a conventional design of bonding pads. In FIG. 2A, the rectangular bonding pads 22A with equal size are disposed along the two longer sides of the rectangular chip 20A which is cut from a wafer. Another bonding pad design is shown in FIG. 2B. The rectangular bonding pads 22B with equal size are disposed on the central area of the rectangular chip 20B which is also cut from a wafer. The electrical layout in the chip 20A or 20B is predetermined and the bonding pads 22A or 22D on the IC chip 20A or 20B respectively are wire bonded with corresponding electrical leads on a lead frame according to the interior layout. However, it is hard to identify the bonding orientation of a chip and the leads on a lead frame because the IC chips 20A and 20B are rectangular and the bonding pads 22A and 22B are disposed on the IC chips 20A and 20B symmetrically.
  • The same orientation problem occurs on probe pads. The probe pads are disposed in certain positions on a circuit for in-line monitoring or checking the electrical performance of the circuit design. FIG. 3 shows the conventional design for probe pads. There are several tiny probe pads 36 disposed in a certain circuit 34 on IC chip 30. The inspector measures the probe pads 36 on the circuit 34 by using a micro-probe under a microscope to obtain the electrical data.
  • Since the square-shaped probe pads on the circuit are very tiny (e.g., 5×5 μm), it is hard and time consuming for an inspector to identify the layout orientation between the probe pads 36 on the circuit 34 under a microscope.
    • SUMMARY OF THE INVENTION
  • One object of the present invention is to provide a bonding structure which is used as an orientation marker for wire bonding and a manufacturing method thereof.
  • Another object of the present invention is to provide a bonding pad structure which can be an alignment marker for wafer dicing.
  • Still another object of the present invention is to provide a mark-shaped pad structure for probe pads as position markers to identify the orientation of the checking circuits.
  • To achieve the above-mentioned object, the present invention provides a bonding pad structure disposed on the surface of a semiconductor substrate with a circuit therein and a manufacturing method thereof. The structure comprises a bottom metal layer disposed over the surface of the semiconductor substrate to connect the circuit electrically, an inter-metal dielectric layer disposed over the bottom metal layer, a plurality of metal plugs formed therein to connect with the bottom metal layer below, a top metal layer disposed over the inter-metal dielectric layer connecting with the metal plugs, and a passivation layer disposed over the top metal layer with a plurality of openings to expose the top metal layer portions as bonding pads, wherein at least one bonding pad is mark-shaped to indicate the orientation of the bonding pads on the semiconductor substrate.
  • According to the present invention, the shape of the mark-shaped bonding pad on the above bonding pad structure can be, for example, a
    Figure US20070187838A1-20070816-P00001
    shape, a
    Figure US20070187838A1-20070816-P00002
    shape, a cross shape
    Figure US20070187838A1-20070816-P00003
    or a
    Figure US20070187838A1-20070816-P00004
    shape.
  • According to the present invention, the top metal and the bottom metal layers on the bonding pad structure can be, for example, an alloy of aluminum and copper or an alloy of aluminum, copper and silica. The inter-metal dielectric layer can be silicon oxide and the passivation layer can be silicon oxide or borophosphosilicate glass and silicon nitride.
  • The mark-shaped bonding pads on a wafer can be used as alignment markers for wafer dicing. The dicing machine can cut dies from a wafer by aligning with the mark-shaped bonding pads on the wafer surface. When the dies are cut from the wafer for further wire bonding, the orientation of circuits in the dies can be easily identified according to the mark-shaped bonding pads on the die surface.
  • A probe pad with a mark-shape is further provided according to the present invention. The probe pad is disposed on a semiconductor circuit for electric characteristic measurement which has a mark-shape to indicate the relative location of the probe pad on the semiconductor circuit.
  • According to the present invention, the shape of the mark-shaped probe pad on the semiconductor circuit can be, for example, a
    Figure US20070187838A1-20070816-P00001
    shape, a
    Figure US20070187838A1-20070816-P00002
    shape, a cross shape
    Figure US20070187838A1-20070816-P00003
    or a
    Figure US20070187838A1-20070816-P00004
    shape. The probe pad can be, for example, an alloy of aluminum and copper or an alloy of aluminum, copper and silica.
  • An inspector can easily identify the orientation of the target circuit under a microscopic with the mark-shaped probe pads according to the present invention.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present invention will become more fully understood from the detailed description given herein below and the accompanying drawings, given by way of illustration only and thus not intended to be limitative of the present invention. In the drawings,
  • FIG. 1 schematically shows a conventional die array on a wafer;
  • FIGS. 2A and 2B schematically show the conventional design of bonding pads (a plan view);
  • FIG. 3 schematically shows the conventional design for probe pads (a plan view);
  • FIG. 4 schematically shows a bonding pad structure according to one embodiment of the present invention;
  • FIGS. 5A-5D schematically show the shapes of bonding pads (a plan view) according to one preferred embodiment of the present invention; and
  • FIG. 6 schematically shows a probe pad (a plan view) according to one embodiment of the present invention.
    • DETAILED DESCRIPTION OF THE INVENTION
  • This invention will be described in further detail by way of example with reference to the accompanying drawings.
  • FIG. 4 is a cross-sectional view showing a bonding pad structure according to one embodiment of the present invention. A bonding pad structure is formed on the surface of a semiconductor substrate 40 with a circuit (not shown) therein. A bottom metal layer 42 is disposed over the surface of the semiconductor substrate 40 and connected with the circuit electrically on the semiconductor substrate 40. The preferred bottom metal layer 42 is an alloy of aluminum and copper or an alloy of aluminum, copper and silica. An inter-metal dielectric layer 44 is then disposed over the bottom metal layer 42. A plurality of metal plugs 46 is then formed in the inter-metal dielectric layer 44 to connect with the bottom metal layer 42 in below. The inter-metal dielectric layer 44 can be, but is not limited to, silicon oxide.
  • A top metal layer 48 is disposed over the inter-metal dielectric layer 44 and connected electrically with the metal plugs 46 in the inter-metal dielectric layer 44. A preferred top metal is an alloy of aluminum and copper or an alloy of aluminum, copper and silica. A passivation layer 49 is disposed over the top metal layer 48. A plurality of openings is defined thereon to expose the top metal portions below (e.g. 40×40 μm per opening) as bonding pads 50 for wire bonding. The passivation layer 49 can be a silicon oxide layer or a layer of borophosphosilicate glass (BPSG) and silicon nitride. At least one opening 50 is defined as a certain shape to form a mark-shaped bonding pad on the semiconductor substrate 40. For example, in having at least one mark-shaped bonding pad on the semiconductor substrate 40, it can be used to indicate the orientation of the circuit in the semiconductor substrate 40.
  • The preferred shapes of the mark-shaped bonding pads formed on the semiconductor substrate 40 are shown in FIGS. 5A to 5D (plan views). The mark-shaped bonding pad on a rectangular semiconductor substrate 40 can be a
    Figure US20070187838A1-20070816-P00001
    shape 50A as FIG. 5A shows, a
    Figure US20070187838A1-20070816-P00002
    shape 50B as FIG. 5B shows, a cross shape
    Figure US20070187838A1-20070816-P00003
    50C as FIG. 5C shows or a
    Figure US20070187838A1-20070816-P00004
    shape as FIG. 50D shows.
  • According to the present invention, there are two advantages of the mark-shaped bonding pads 50A to 50D that have special shapes other than conventional rectangular bonding pads on the semiconductor substrate 40. One advantages is the mark-shaped bonding pads 50A to 50D can be used as alignment markers for wafer dicing. In addition to conventional markers on scribe lines, a dicing machine can cut dies from a wafer by aligning the mark-shaped bonding pads on the wafer surface, especially when cutting the fragmental portions of a wafer.
  • Another advantage of the mark-shaped bonding pads in the present invention is that it is easy to identify the orientation of the rectangular semiconductor substrate 40 with the mark-shaped bonding pads 50A to 50D. As shown in FIGS. 5A-5D, there are bonding pads lined up in a row on the surface of the rectangular semiconductor substrate 40. There is difficulty identifying the orientation of the rectangular semiconductor substrate 40 only with the rectangular bonding pads 51. However, it is easy to identify the orientation of the rectangular semiconductor substrate 40 according to the invention by defining a least one bonding pad as a mark-shaped bonding pad, e.g. bonding pads 50A-50D.
  • Therefore, the relative position between the mark-shaped bonding pads 50A-50D and the other normal rectangular bonding pads denotes the orientation of circuits in the semiconductor substrate 40. Although the circuits layout cannot be seen from the surface of the rectangular semiconductor substrate 40, the orientation of the circuits can still be identified according to the mark-shaped bonding pads on the surface, which makes wire bonding easier to connect the interior circuit by bonding the bonding pads with corresponding leads on a lead frame.
  • According to the present invention, a probe pad is further provided. FIG. 6 shows a schematic plan view of a probe pad design according to one embodiment of the invention. There is a mark-shaped bonding pad 50 disposed on the surface of a rectangular semiconductor chip 40 to indicate the substrate 40's orientation and there is a checking area 62 on the semiconductor chip 40. A plurality of mark-shaped probe pads is disposed on certain circuits inside the checking area 62, e.g. a
    Figure US20070187838A1-20070816-P00001
    shape probe pad 60A or a
    Figure US20070187838A1-20070816-P00004
    shape probe pad 60B. The preferred probe pads can be, for example, an alloy of aluminum and copper or an alloy of aluminum, copper and silica.
  • The electric performance of certain circuits on the checking area 62 is obtained by removing the surface of the area 62 and then measuring the interior probe pads with a micro-probe under a microscope. Since the microscope magnifies the scale of the checking area 62, an inspector can clearly identify the orientation of the checking area 62 according to the mark-shaped probe pads 60A or 60B on the checking circuits. According to the present invention, it is easier to identify the circuit orientation with the mark-shaped probe pads than the conventional rectangular probe pads on the checking circuits, and therefore, the in-line monitoring or electrical checking of the circuits are more efficient.
  • The mark-shaped pads according to the present invention can be applied on a bonding pad structure on the surface of a semiconductor chip or a probe pad on a circuit. A bonding pad structure with at least one mark-shaped pad, can be used as an alignment marker of wafer dicing and/or an indicator of chip orientation in wire bonding. Mark-shaped probe pads on circuits of a checking area can be used as indicators showing the relative positions with each other.
  • The foregoing description of the preferred embodiments of this invention has been presented for purposes of illustration and description. Obvious modifications or variations are possible in light of the above teaching. The embodiments were chosen and described to provide the best illustration of the principles of this invention and its practical application to thereby enable those skilled in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. All such modifications and variations are within the scope of the present invention as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly, legally, and equitably entitled.

Claims (6)

1.-14. (canceled)
15. A method for forming a bonding pad structure on a surface of a semiconductor substrate with a circuit therein, comprising:
disposing a bottom metal layer over the surface of the semiconductor substrate to connect the circuit electrically;
disposing an inter-metal dielectric layer over the bottom metal layer;
forming a plurality of metal plugs in the inter-metal dielectric layer to connect with the bottom metal layer;
disposing a top metal layer over the inter-metal dielectric layer to connect with the metal plugs;
disposing a passivation layer over the top metal layer; and
defining a plurality of openings on the passivation layer to expose the top metal layer portions as bonding pads, wherein at least one bonding pad is defined as a mark-shape to indicate the orientation of the bonding pads on the semiconductor substrate.
16. The method as claimed as in claim 15, wherein the mark-shaped bonding pad is defined as a
Figure US20070187838A1-20070816-P00001
shape.
17. The method as claimed as in claim 15, wherein the mark-shaped bonding pad is defined as a
Figure US20070187838A1-20070816-P00002
shape.
18. The method as claimed as in claim 15, wherein the mark-shaped bonding pad is defined as a cross shape
Figure US20070187838A1-20070816-P00003
19. The method as claimed as in claim 15, wherein the mark-shaped bonding pad is defined as a
Figure US20070187838A1-20070816-P00004
shape.
US11/691,606 2002-03-21 2007-03-27 Pad structure for bonding pad and probe pad and manufacturing method thereof Abandoned US20070187838A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/691,606 US20070187838A1 (en) 2002-03-21 2007-03-27 Pad structure for bonding pad and probe pad and manufacturing method thereof

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
TW091105490A TW531776B (en) 2002-03-21 2002-03-21 Metal pad structure suitable for connection pad and inspection pad
TW91105490 2002-03-21
US10/150,389 US6734572B2 (en) 2002-03-21 2002-05-17 Pad structure for bonding pad and probe pad and manufacturing method thereof
US10/776,714 US7211904B2 (en) 2002-03-21 2004-02-09 Pad structure for bonding pad and probe pad and manufacturing method thereof
US11/691,606 US20070187838A1 (en) 2002-03-21 2007-03-27 Pad structure for bonding pad and probe pad and manufacturing method thereof

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/776,714 Division US7211904B2 (en) 2002-03-21 2004-02-09 Pad structure for bonding pad and probe pad and manufacturing method thereof

Publications (1)

Publication Number Publication Date
US20070187838A1 true US20070187838A1 (en) 2007-08-16

Family

ID=28037883

Family Applications (3)

Application Number Title Priority Date Filing Date
US10/150,389 Expired - Lifetime US6734572B2 (en) 2002-03-21 2002-05-17 Pad structure for bonding pad and probe pad and manufacturing method thereof
US10/776,714 Expired - Lifetime US7211904B2 (en) 2002-03-21 2004-02-09 Pad structure for bonding pad and probe pad and manufacturing method thereof
US11/691,606 Abandoned US20070187838A1 (en) 2002-03-21 2007-03-27 Pad structure for bonding pad and probe pad and manufacturing method thereof

Family Applications Before (2)

Application Number Title Priority Date Filing Date
US10/150,389 Expired - Lifetime US6734572B2 (en) 2002-03-21 2002-05-17 Pad structure for bonding pad and probe pad and manufacturing method thereof
US10/776,714 Expired - Lifetime US7211904B2 (en) 2002-03-21 2004-02-09 Pad structure for bonding pad and probe pad and manufacturing method thereof

Country Status (2)

Country Link
US (3) US6734572B2 (en)
TW (1) TW531776B (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003338519A (en) * 2002-05-21 2003-11-28 Renesas Technology Corp Semiconductor device and its manufacturing method
US7199039B2 (en) * 2003-05-19 2007-04-03 Intel Corporation Interconnect routing over semiconductor for editing through the back side of an integrated circuit
KR100675275B1 (en) * 2004-12-16 2007-01-26 삼성전자주식회사 Semiconductor device and pad arrangement method thereof
WO2008111977A1 (en) * 2007-03-13 2008-09-18 Kulicke And Soffa Industries, Inc. Method of teaching eyepoints for wire bonding and related semiconductor processing operations
US20080303177A1 (en) * 2007-06-06 2008-12-11 United Microelectronics Corp. Bonding pad structure
US8742599B2 (en) * 2012-08-30 2014-06-03 Freescale Semiconductor, Inc. Identification mechanism for semiconductor device die
US9536810B1 (en) * 2015-06-12 2017-01-03 Taiwan Semiconductor Manufacturing Co., Ltd. Flat pad structure for integrating complementary metal-oxide-semiconductor (CMOS) image sensor processes
US10109666B2 (en) 2016-04-13 2018-10-23 Taiwan Semiconductor Manufacturing Co., Ltd. Pad structure for backside illuminated (BSI) image sensors

Citations (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5022580A (en) * 1988-03-16 1991-06-11 Plessey Overseas Limited Vernier structure for flip chip bonded devices
US5317141A (en) * 1992-08-14 1994-05-31 National Semiconductor Corporation Apparatus and method for high-accuracy alignment
US5412329A (en) * 1991-11-18 1995-05-02 Tokyo Electron Yamanashi Limited Probe card
US5657394A (en) * 1993-06-04 1997-08-12 Integrated Technology Corporation Integrated circuit probe card inspection system
US5742173A (en) * 1995-03-18 1998-04-21 Tokyo Electron Limited Method and apparatus for probe testing substrate
US6008061A (en) * 1996-10-11 1999-12-28 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device having a test pad
US6251694B1 (en) * 1999-05-26 2001-06-26 United Microelectronics Corp. Method of testing and packaging a semiconductor chip
US20020016070A1 (en) * 2000-04-05 2002-02-07 Gerald Friese Power pads for application of high current per bond pad in silicon technology
US6392300B1 (en) * 1999-06-28 2002-05-21 Kabushiki Kaisha Toshiba Semiconductor device having an alignment mark formed on the uppermost layer of a multilayer wire
US20020178600A1 (en) * 2001-06-01 2002-12-05 Satoshi Machida Method of manufacturing alignment mark
US20030038367A1 (en) * 2001-08-21 2003-02-27 Tadashi Yamaguchi Semiconductor device and method for manufacturing the same
US20030052440A1 (en) * 2001-09-17 2003-03-20 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit device and method for fabricating the same
US6555922B1 (en) * 1999-03-18 2003-04-29 Fujitsu Limited IC bonding pad combined with mark or monitor
US6579734B2 (en) * 2001-04-09 2003-06-17 Oki Electric Industry Co., Ltd. Wire bonding method
US6664642B2 (en) * 1997-03-31 2003-12-16 Hitachi, Ltd. Semiconductor integrated circuit device
US6668449B2 (en) * 2001-06-25 2003-12-30 Micron Technology, Inc. Method of making a semiconductor device having an opening in a solder mask
US6784516B1 (en) * 2000-10-06 2004-08-31 International Business Machines Corporation Insulative cap for laser fusing
US6849957B2 (en) * 2000-05-30 2005-02-01 Renesas Technology Corp. Photomask including auxiliary mark area, semiconductor device and manufacturing method thereof
US6864589B2 (en) * 2001-03-30 2005-03-08 Sharp Laboratories Of America, Inc. X/Y alignment vernier formed on a substrate

Patent Citations (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5022580A (en) * 1988-03-16 1991-06-11 Plessey Overseas Limited Vernier structure for flip chip bonded devices
US5412329A (en) * 1991-11-18 1995-05-02 Tokyo Electron Yamanashi Limited Probe card
US5317141A (en) * 1992-08-14 1994-05-31 National Semiconductor Corporation Apparatus and method for high-accuracy alignment
US5657394A (en) * 1993-06-04 1997-08-12 Integrated Technology Corporation Integrated circuit probe card inspection system
US5742173A (en) * 1995-03-18 1998-04-21 Tokyo Electron Limited Method and apparatus for probe testing substrate
US6008061A (en) * 1996-10-11 1999-12-28 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device having a test pad
US6664642B2 (en) * 1997-03-31 2003-12-16 Hitachi, Ltd. Semiconductor integrated circuit device
US6555922B1 (en) * 1999-03-18 2003-04-29 Fujitsu Limited IC bonding pad combined with mark or monitor
US6251694B1 (en) * 1999-05-26 2001-06-26 United Microelectronics Corp. Method of testing and packaging a semiconductor chip
US6392300B1 (en) * 1999-06-28 2002-05-21 Kabushiki Kaisha Toshiba Semiconductor device having an alignment mark formed on the uppermost layer of a multilayer wire
US20020016070A1 (en) * 2000-04-05 2002-02-07 Gerald Friese Power pads for application of high current per bond pad in silicon technology
US6849957B2 (en) * 2000-05-30 2005-02-01 Renesas Technology Corp. Photomask including auxiliary mark area, semiconductor device and manufacturing method thereof
US6784516B1 (en) * 2000-10-06 2004-08-31 International Business Machines Corporation Insulative cap for laser fusing
US6864589B2 (en) * 2001-03-30 2005-03-08 Sharp Laboratories Of America, Inc. X/Y alignment vernier formed on a substrate
US6579734B2 (en) * 2001-04-09 2003-06-17 Oki Electric Industry Co., Ltd. Wire bonding method
US20020178600A1 (en) * 2001-06-01 2002-12-05 Satoshi Machida Method of manufacturing alignment mark
US6668449B2 (en) * 2001-06-25 2003-12-30 Micron Technology, Inc. Method of making a semiconductor device having an opening in a solder mask
US20030038367A1 (en) * 2001-08-21 2003-02-27 Tadashi Yamaguchi Semiconductor device and method for manufacturing the same
US20030052440A1 (en) * 2001-09-17 2003-03-20 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit device and method for fabricating the same

Also Published As

Publication number Publication date
TW531776B (en) 2003-05-11
US7211904B2 (en) 2007-05-01
US6734572B2 (en) 2004-05-11
US20040159952A1 (en) 2004-08-19
US20030181029A1 (en) 2003-09-25

Similar Documents

Publication Publication Date Title
US7057296B2 (en) Bonding pad structure
US7262513B2 (en) Apparatus and method extending flip-chip pad structures for wirebonding on low-k dielectric silicon
US20070187838A1 (en) Pad structure for bonding pad and probe pad and manufacturing method thereof
KR100979080B1 (en) Semiconductor device having a wire bond pad and method therefor
US6614120B2 (en) Semiconductor device
US20060231959A1 (en) Bonding pad for a packaged integrated circuit
US20070210442A1 (en) Method and apparatus for providing structural support for interconnect pad while allowing signal conductance
US7416964B2 (en) Semiconductor wafer, semiconductor chip and dicing method of a semiconductor wafer
US8072076B2 (en) Bond pad structures and integrated circuit chip having the same
US7939936B2 (en) Semiconductor package having semiconductor device featuring externally-accessible endless ring-shaped resistance circuit
US20080296570A1 (en) Semiconductor device
US6556454B1 (en) High density contact arrangement
US20200303268A1 (en) Semiconductor device including residual test pattern
US20070018340A1 (en) Integrated circuit pad with separate probing and bonding areas
TWI418004B (en) Chip package structure and chip packaging process
US8669555B2 (en) Semiconductor device
US20080303177A1 (en) Bonding pad structure
US20130187158A1 (en) Semiconductor device
US11043435B1 (en) Semiconductor die with hybrid wire bond pads
US20090014717A1 (en) Test ic structure
CN217588904U (en) Chip welding pad, chip and chip packaging structure
US20230187289A1 (en) Semiconductor device and method of forming the same
CN114783962A (en) Chip welding pad, chip packaging structure and method
TW200903681A (en) Test IC structure

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION