US20070114533A1 - Thin film transistor including a lightly doped amorphous silicon channel layer - Google Patents
Thin film transistor including a lightly doped amorphous silicon channel layer Download PDFInfo
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- US20070114533A1 US20070114533A1 US11/624,699 US62469907A US2007114533A1 US 20070114533 A1 US20070114533 A1 US 20070114533A1 US 62469907 A US62469907 A US 62469907A US 2007114533 A1 US2007114533 A1 US 2007114533A1
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- amorphous silicon
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- 229910021417 amorphous silicon Inorganic materials 0.000 title claims abstract description 53
- 239000010409 thin film Substances 0.000 title claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 125000004429 atom Chemical group 0.000 claims description 20
- 230000008021 deposition Effects 0.000 claims description 15
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 10
- 125000004437 phosphorous atom Chemical group 0.000 claims description 10
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 26
- 238000000034 method Methods 0.000 description 25
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 20
- 238000000151 deposition Methods 0.000 description 12
- 239000001257 hydrogen Substances 0.000 description 11
- 229910052739 hydrogen Inorganic materials 0.000 description 11
- 229910000077 silane Inorganic materials 0.000 description 11
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 239000012495 reaction gas Substances 0.000 description 8
- 150000002431 hydrogen Chemical class 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000000203 mixture Substances 0.000 description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 239000011651 chromium Substances 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910020776 SixNy Inorganic materials 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- WOAFDWZSMDJFRZ-UHFFFAOYSA-N oxotin;strontium Chemical compound [Sr].[Sn]=O WOAFDWZSMDJFRZ-UHFFFAOYSA-N 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000012780 transparent material Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78609—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
Abstract
A thin film transistor (TFT) is provided. The thin film transistor (TFT) comprises a substrate, a gate, an inter-gate dielectric layer, a channel layer and source/drain regions. A gate is formed over the substrate. An inter-gate dielectric layer is formed over the substrate covering the gate. A doped amorphous silicon layer is formed over a portion of the inter-gate dielectric layer at least covering the gate to serve as channel layer. Source/drain regions are formed over the channel layer.
Description
- This is a divisional application of patent application Ser. No. 10/711,509, filed on Sep. 23, 2004, which is a continuation-in-part of prior applications Ser. No. 10/777,564, filed on Feb. 11, 2004. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.
- 1. Field of the Invention
- The present invention generally relates to a thin film transistor (TFT). More particularly, the present invention generally relates to a thin film transistor (TFT) having a lightly doped amorphous silicon channel layer.
- 2. Description of the Related Art
- In recent years, a variety of macromedia electronic devices and products are drastically developed due to the rapid development of the semiconductor device and the user interface of the device. Conventionally, since the cathode ray tube (CRT) display device is low-cost and has high performance, it is widely used display device. However, as to the display device of the personal computer, the cathode ray tube (CRT) display has the disadvantages of large size and high power consumption. Accordingly, the liquid crystal display (LCD) being small, lightweight, use low operational voltage, low power consumption, radiation free and environmentally friendly, gradually replaced the conventional CRT display. In recent years, the liquid crystal display (LCD), for example, the thin film transistor (TFT) liquid crystal display (LCD) has become the main stream of the display devices.
- In general, the conventional thin film transistor (TFT) may be classified into amorphous silicon thin film transistor (TFT) and polysilicon thin film transistor (TFT). It is noted that, the technology of low temperature polysilicon (LTPS) is different from the technology of conventional amorphous silicon (α-Si). In the low temperature polysilicon (LTPS) technology, the electron mobility can be enhanced to more than 200 cm2/V-sec. Therefore, the size of the thin film transistor (TFT) can be minimized, the aperture ratio of the display can be enhanced, and the power consumption can be reduced. However, because of the manufacturing process of the amorphous silicon thin film transistor (TFT) technology is well developed, simple and low-cost, the amorphous silicon thin film transistor (TFT) technology is still the main stream of the array of the display device.
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FIG. 1 is a cross-sectional view schematically illustrating the structure of conventional amorphous silicon thin film transistor (TFT). Referring toFIG. 1 , the thin film transistor (TFT) 100 includes asubstrate 110, agate 120, an inter-gatedielectric layer 130, achannel layer 140 and source/drain regions 150. Thegate 120 is disposed on thesubstrate 110. The inter-gatedielectric layer 130 is disposed on the substrate and covers thegate 120. Thechannel layer 140 is disposed on a portion of the inter-gatedielectric layer 130 that at least covers thegate 120. The source/drain regions 150 are disposed on thechannel layer 140 and are separated by a distance. When thegate 120 operates to supply an operating voltage to thechannel layer 140, the source/drain regions 150 are electrically connected by thechannel layer 140. - The manufacturing method of the
channel layer 140 of the conventional thin film transistor (TFT) 100 includes the following steps. First, thesubstrate 110 is transported into a reaction chamber (not shown) and the substrate is subjected to a reaction gas mixture comprising of silane (SiH4) and hydrogen (H2) in the reaction chamber to form an intrinsic amorphous silicon layer. Next, the amorphous silicon layer is patterned to form thechannel layer 140. - Accordingly, because the channel layer of the thin film transistor (TFT) is an intrinsic amorphous silicon layer, the electron mobility and the turning-on-current are not high enough when the thin film transistor is operated.
- Accordingly, one object of the present invention is to provide a thin film transistor. (TFT) and the manufacturing method thereof to increase the turning-on-current and the electron mobility of the channel region of the thin film transistor (TFT).
- In accordance with the above objects and other advantages of the present invention, a manufacturing method of thin film transistor (TFT) is provided. The manufacturing method includes the following steps. First, a gate is formed over a substrate. Next, an inter-gate dielectric layer is formed over the substrate covering the gate. Next, a channel layer is formed covering over a portion of the inter-gate dielectric layer at least covering the gate. The channel layer comprises a lightly doped amorphous silicon layer. Next, source/drain regions are formed over the channel layer, wherein the source/drain regions are separated by a distance.
- In an embodiment of the present invention, the channel layer comprises an N-type lightly doped amorphous silicon layer. In another embodiment of the invention, the channel layer may comprise a P-type lightly doped amorphous silicon layer.
- In an embodiment of the present invention, the channel layer, for example but not limited to, doped with phosphorous atoms, and a concentration of phosphorous atoms in the channel layer is in a range of about 1E17 atom/cm3 to about 1E18 atom/cm3. In another embodiment of the invention, the channel layer is, for example but not limited to, doped with boron atoms, and a concentration of boron atoms in the channel layer is in a range of about 1E16 atom/cm3 to about 5E17 atom/cm3.
- In an embodiment of the present invention, the channel layer is formed by performing, for example but not limited to, a chemical vapor deposition (CVD) process using a reaction gas mixture comprising silane (SiH4), hydrogen and phosphine (PH3), wherein a effective content ratio of phosphine (PH3) is in a range of about 2.8E-7 to about 8E-6, wherein the effective content ratio of the phosphine (PH3) is equal to the ratio of the content of phosphine (PH3) to the total content of silane (SiH4), hydrogen (H2) and phosphine (PH3).
- In another embodiment of the present invention, the channel layer is formed by performing, for example but not limited to, a chemical vapor deposition (CVD) process using a reaction gas mixture comprising silane (SiH4), hydrogen (H2) and boroethane (B2H6), wherein a effective content ratio of the boroethane (B2H6) is in a range of about 5E-7 to about 1E-5, and wherein the effective content ratio of the boroethane (B2H6) is equal to the ratio of the content of boroethane (B2H6) to the total content of silane (SiH4), hydrogen (H2) and boroethane (B2H6).
- In an embodiment of the present invention, the channel layer is formed by, for example but not limited to, forming a first lightly doped sub-amorphous silicon layer over a portion of the inter-gate dielectric layer at a first deposition rate, and forming a second lightly doped sub-amorphous silicon layer over the first lightly doped sub-amorphous silicon layer at a second deposition rate, wherein the first deposition rate is lower than the second deposition rate.
- In an embodiment of the present invention, the method further includes, for example but not limited to, a step of forming an ohmic contact layer over the channel layer between the steps of forming the channel layer and the step of forming the source/drain regions.
- In an embodiment of the present invention, the method further includes, for example but not limited to, a step of forming a protection layer over the substrate covering the source/drain regions, the channel layer and the inter-gate dielectric layer.
- In accordance with above objects and other advantages of the present invention, a thin film transistor (TFT) is provided. The thin film transistor (TFT) includes a substrate, a gate, an inter-gate dielectric layer, a channel layer and source/drain regions. The gate is disposed over the substrate, and the inter-gate dielectric layer is disposed on the substrate and covers the gate. The channel layer is disposed over a portion of the inter-gate dielectric layer, wherein the channel covers the gate. The channel layer comprises a lightly doped amorphous silicon layer. The source/drain regions are disposed over the channel layer, wherein the source/drain regions are separated by a distance.
- In an embodiment of the present invention, the channel layer comprises an N-type lightly doped amorphous silicon layer. In another embodiment of the invention, the channel layer may comprise a P-type lightly doped amorphous silicon layer.
- In an embodiment of the present invention, the channel layer is, for example but not limited to, doped with phosphorous atoms, and a concentration of phosphorous atoms in the channel layer is in a range of about 1E17 atom/cm3 to about 1E18 atom/cm3. In another embodiment of the invention, the channel layer is, for example but not limited to, doped with boron atoms, and a concentration of boron atoms in the channel layer is in a range of about 1E16 atom/cm3 to about 5E17 atom/cm3.
- In an embodiment of the present invention, the method of forming the channel layer includes, for example but not limited to, a first lightly doped sub-amorphous silicon layer and a second lightly doped sub-amorphous silicon layer. Wherein the first lightly doped sub-amorphous silicon layer is formed over a portion of the inter-gate dielectric layer at a first deposition rate, and the second lightly doped sub-amorphous silicon layer is formed over the first lightly doped sub-amorphous silicon layer at a second deposition rate. Furthermore, the second deposition rate is higher than the first deposition rate.
- In an embodiment of the present invention, the TFT further includes, for example but not limited to, an ohmic contact layer disposed between the channel layer and the source/drain.
- In an embodiment of the present invention, the TFT further includes, for example but not limited to, a protection layer disposed over the substrate covering the source/drain regions, the channel layer and the inter-gate dielectric layer.
- According to an aspect of the present invention, a lightly doped amorphous silicon layer is provided as a channel layer achieve at least the advantages of increased electron mobility of the channel layer and thereby increase the turning-on-current of thin film transistor (TFT) without increasing the leakage current, and the improvement of the ohmic contact between the channel layer and the source/drain regions.
- It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
- The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The following drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
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FIG. 1 is a cross-sectional view schematically illustrating the structure of a conventional amorphous silicon thin film transistor (TFT). -
FIG. 2A toFIG. 2F are cross-sectional views schematically illustrating the process flow of a process of forming a thin film transistor (TFT) according to a preferred embodiment of the present invention. -
FIG. 3 is a plot illustrating the relationship between the turning-on-current and the effective content ratio of the phosphine (PH3) in the process of forming the thin film transistor (TFT) according to one of the preferred embodiment of the present invention. -
FIG. 4 is a plot illustrating the relationship between the electron mobility and the effective content ratio of the phosphine (PH3) in the process of forming the thin film transistor (TFT) according to one of the preferred embodiment of the present invention. - The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout.
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FIG. 2A toFIG. 2F are cross-sectional views schematically illustrating the process flow of a process of forming a thin film transistor (TFT) according to a preferred embodiment of the present invention. As shown inFIG. 2A , agate 220 is formed over asubstrate 210. Next, an inter-gatedielectric layer 230 is formed over thesubstrate 210 at least covering thegate 220. The method of forming thegate 220 includes, for example but not limited to, forming a first conductive layer (Metal 1) over thesubstrate 210 by performing a sputtering process, and then performing well known photolithography and etching process to form thegate 220. The inter-gatedielectric layer 230 can be formed by, for example but not limited to, performing a plasma enhance chemical vapor deposition (PECVD) process. - Furthermore, the
substrate 210 includes, for example but not limited to, a glass substrate, a transparent plastic substrate or a substrate composed of any transparent material. The material of thegate 220 includes, for example but not limited to, tantalum (Ta), chromium (Cr), molybdenum (Mo), titanium (Ti) or aluminum (Al) or other conductive material. The material of the inter-gatedielectric layer 230 includes, for example but not limited to silicon nitride (SixNy), silicon oxynitride (SiON), silicon oxide (SiOx) or other dielectric material. - Next, as shown in
FIG. 2B , achannel layer 240 is formed over a portion of the inter-gatedielectric layer 230 at least covering thegate 220. Thechannel layer 240 comprises, for example but not limited to, lightly doped amorphous silicon layer, wherein the doped amorphous silicon layer comprises an N-type lightly doped amorphous silicon layer or P-type lightly doped amorphous silicon layer. Thechannel layer 240 can be formed by performing, for example but not limited to, a chemical vapor deposition (CVD) process. The CVD process includes, for example, transporting thesubstrate 210 into a reaction chamber (not shown). Next, a reaction gas mixture is charged into the reaction chamber, wherein the reaction gas mixture comprises, for example but not limited, silane (SiH4), hydrogen (H2) and phosphine (PH3). Alternatively, the reaction gas mixture may comprise silane (SiH4), hydrogen (H2) and boroethane (B2H6). For the reaction gas comprising phosphine (PH3), the effective content ratio of the phosphine (PH3) is, for example but not limited to, in a range of about 2.8E-7 to about 8E-6. And, for the reaction gas comprising boroethane (B2H6), the effective content ratio of the boroethane (B2H6) is, for example but not limited to, in a range of about 5E-7 to about 1E-5. The effective content ratio of the phosphine (PH3) is equal to the ratio of the content of phosphine (PH3) to the total content of silane (SiH4), hydrogen and phosphine (PH3). The effective content ratio of the boroethane (B2H6) is equal to the ratio of the content of boroethane (B2H6) to the total content of silane (SiH4), hydrogen and boroethane (B2H6). - In an embodiment of the present invention, the
channel layer 240 is, for example but not limited to, doped with phosphorous atoms. The concentration of phosphorous atoms is, for example but not limited to, in a range of about 1E17 atom/cm3 to 1E18 atom/cm3. Alternatively, thechannel layer 240 is, for example but not limited to, doped with boron atoms. The concentration of boron atoms is, for example but not limited to, in a range of about 1E16 atom/cm3 to 5E17 atom/cm3. - The method of forming the
channel layer 240 is described as follows. First, a first lightly dopedsub-amorphous silicon layer 242 is formed over a portion of the inter-gatedielectric layer 230 at least covering thegate 220 at a first deposition rate. Next, a second lightly dopedsub-amorphous silicon layer 244 is formed over the first lightly dopedsub-amorphous silicon 242 at a second deposition rate. In an embodiment of the invention, the first deposition rate is, lower than the second deposition rate. - Next, as shown in
FIG. 2C , anohmic contact layer 250 is formed over thechannel layer 240, wherein theohmic contact layer 250 has an excellent contact with a metal surface. The method of forming theohmic contact layer 250 includes, for example but not limited to, performing an ion implant process to implant N-type ions into the amorphous silicon layer. - Next, as shown in
FIG. 2D , source/drain regions 260 are formed over thechannel layer 240. The forming method of source/drain regions 260 includes, for example but not limited to, first forming a second conductive layer (Metal 2) over thesubstrate 210, and then performing the well known photolithography and etching process to form the source/drain regions 260. The material of the source/drain 260 includes, for example but not limited to, tantalum (Ta), chromium (Cr), molybdenum (Mo), titanium (Ti), aluminum (Al), or other conductive material. - Next, as shown in
FIG. 2E , aprotection layer 270 is formed over thesubstrate 210 to cover the source/drain regions 260, thechannel layer 240 and the inter-gatedielectric layer 230. Theprotection layer 270 comprises anopening 272 exposing a portion of the source/drain region 260 there-within. - Next, as shown in
FIG. 2F , a transparentconductive layer 280 is formed over theprotection layer 270 and electrically connected to the source/drain region 260 through theopening 272. The transparentconductive layer 280 includes, for example but not limited to, a pixel electrode. The material of the transparentconductive layer 280 includes, for example but not limited to, indium tin oxide (ITO), strontium tin oxide (STO), or other transparent conductive material. - Referring to
FIG. 2E , a structure of the thin film transistor (TFT) 200 of the present invention is shown. The TFT comprises asubstrate 210, agate 220, an inter-gatedielectric layer 230, achannel layer 240 and source/drain regions 260. Thegate 220 is disposed over thesubstrate 210. The inter-gatedielectric layer 230 is disposed over thesubstrate 210 and covers thegate 220. Thechannel layer 240 is disposed over a portion of the inter-gatedielectric layer 230 at least covering thegate 210. The material of thechannel layer 240 includes, for example, a lightly doped amorphous silicon layer. The source/drain regions 260 are disposed over thechannel layer 240, wherein the source/drain are separated by a distance. - Furthermore, the
channel layer 240 comprises, for example but not limited to, an N-type lightly doped amorphous silicon layer or P-type lightly doped amorphous silicon layer. - Furthermore, the
channel layer 240 is, for example but not limited to, doped with phosphorous atoms, and the concentration of phosphorous atoms in thechannel layer 240 is, for example but not limited to, in a range of about 1E17 atom/cm3 to about 1E18 atom/cm3. Alternatively, thechannel layer 240 is, for example but not limited to, boron atoms, and the concentration of boron atoms in thechannel layer 240 is, for example but not limited to, in a range of about 1E16 atom/cm3 to about 5E17 atom/cm3. - Moreover, the
channel layer 240 can be formed by, for example but not limited to, sequentially forming a first lightly dopedsub-amorphous silicon layer 242 and a second lightly dopedsub-amorphous silicon layer 244 over the inter-gatedielectric layer 220. The first lightly dopedsub-amorphous silicon layer 242 is disposed, for example but not limited to, on a portion of the inter-gatedielectric layer 220 that at least covers thegate 210. The second lightly dopedsub-amorphous silicon layer 244 is disposed, for example but not limited to, on the first lightly dopedsub-amorphous silicon layer 242. - Moreover, the thin film transistor (TFT) 210 further includes, for example but not limited to, an
ohmic contact layer 250 and aprotection layer 270 formed over thesubstrate 210. Theohmic contact layer 250 is disposed, for example but not limited to, between thechannel layer 240 and the source/drain regions 260 to enhance the ohmic contact thechannel layer 240 and the source/drain regions 260. Theprotection layer 270 is disposed on, for example but not limited to, thesubstrate 210, and theprotection layer 270 covers the source/drain regions 260, thechannel layer 240 and the inter-gatedielectric layer 220. - However, it is noted that, the above-described thin film transistor (TFT) and the manufacturing method thereof of the embodiments of the present invention is provided as exemplary embodiments of the invention. Further, the use of channel layer composed of lightly doped amorphous silicon layer in a thin film transistor (TFT) and the process of forming the same in a TFT falls within the scope of the present invention.
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FIG. 3 is a plot illustrating the relationship between the turning-on-current and the effective content ratio of phosphine (PH3) in the process of forming the thin film transistor (TFT) according to one of the preferred embodiment of the present invention.FIG. 4 is a plot illustrating the relationship between the electron mobility and the effective content ratio of phosphine (PH3) in the process of forming the thin film transistor (TFT) according to one of the preferred embodiment of the present invention. As shown inFIG. 3 , the turning-on-current of the thin film transistor (TFT) increases drastically with the increasing effective content ratio of the phosphine (PH3) in presence of the channel layer. As shown inFIG. 4 , the electron mobility of the channel layer of the thin film transistor (TFT) drastically increases with the increasing effective content ratio of the phosphine (PH3) in presence of the channel layer. InFIG. 3 andFIG. 4 , the parameter (2.9/2.8) means that the effective content ratio of the phosphine (PH3) is 2.9*1E-7 when fabricating the first lightly doped sub-amorphous layer, and the effective content ratio of the phosphine (PH3) is 2.8*1E-7 when fabricating the second lightly doped sub-amorphous layer. Similarly, the parameter (5.7/5.6) means that the effective content ratio of the phosphine (PH3) is 5.7*1E-7 when fabricating the first lightly doped sub-amorphous layer, and the effective content ratio of the phosphine (PH3) is 5.6*1E-7 when fabricating the second lightly doped sub-amorphous layer. Moreover, the rest parameters such as (8.6/8.3), (11.4/11.1), (54.7/44.4), (80/77.8) and (108.6/105.6) are explained in the same way. For example, the effective content ratio of phosphine (PH3) X is calculated as follow. XPH3=(RPH3*WPH3)/((RPH3* WPH3)+(RH2*WH2)+(RSiH4*WSiH4)), wherein RPH3 is the flow rate of phosphine; WPH3 is the weight percent of phosphine; RH2 is the flow rate of hydrogen; WH2 is the weight percent of hydrogen; RsiH4 is the flow rate of silane; and WSiH4 is the weight percent of silane. - Furthermore, the TFT of the present invention was tested, the test results reveal that the TFT of the present invention do not have excess the leakage current, and the ohmic contact between the channel layer and the source/drain is substantially improved.
- It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Claims (8)
1. A thin film transistor (TFT), comprising:
a substrate;
a gate, disposed over the substrate;
an inter-gate dielectric layer, disposed over the substrate covering the gate;
a channel layer, disposed over a portion of the inter-gate dielectric layer, at least over the gate, wherein the channel layer comprises a lightly doped amorphous silicon layer; and
source/drain regions, disposed over the channel layer, wherein the source/drain regions are separated by a distance.
2. The thin film transistor (TFT) of claim 1 , wherein the channel layer comprises an N-type lightly doped amorphous silicon layer.
3. The thin film transistor (TFT) of claim 1 , wherein the channel layer comprises a P-type lightly doped amorphous silicon layer.
4. The thin film transistor (TFT) of claim 1 , wherein the channel layer is doped with phosphorous atoms, and a concentration of phosphorous atoms is in a range of about 1E17 atom/cm3 to about 1E18 atom/cm3.
5. The thin film transistor (TFT) of claim 1 , wherein the channel layer is doped with boron atoms, and a concentration of boron atoms is in a range of about 1E16 atom/cm3 to about 5E17 atom/cm3.
6. The thin film transistor (TFT) of claim 1 , wherein the lightly doped amorphous silicon layer comprises:
a first lightly doped sub-amorphous silicon layer, disposed over a portion of the inter-gate dielectric layer; and
a second lightly doped sub-amorphous silicon layer, disposed over the first lightly doped sub-amorphous silicon layer, wherein the first lightly doped sub-amorphous silicon layer is formed at a first deposition rate, and the second lightly doped sub-amorphous silicon layer is formed at a second deposition rate higher than the first deposition rate.
7. The thin film transistor (TFT) of claim 1 , further comprising an ohmic contact layer between the channel layer and the source/drain regions.
8. The thin film transistor (TFT) of claim 1 , further comprising a protection layer over the substrate, wherein the protection layer covers the source/drain regions, the channel layer and the inter-gate dielectric layer.
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US11/624,699 US20070114533A1 (en) | 2004-02-11 | 2007-01-19 | Thin film transistor including a lightly doped amorphous silicon channel layer |
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US10/777,564 US20050176188A1 (en) | 2004-02-11 | 2004-02-11 | Thin film transistor and manufacturing method thereof |
US10/711,509 US7205171B2 (en) | 2004-02-11 | 2004-09-23 | Thin film transistor and manufacturing method thereof including a lightly doped channel |
US11/624,699 US20070114533A1 (en) | 2004-02-11 | 2007-01-19 | Thin film transistor including a lightly doped amorphous silicon channel layer |
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US10/711,509 Expired - Lifetime US7205171B2 (en) | 2004-02-11 | 2004-09-23 | Thin film transistor and manufacturing method thereof including a lightly doped channel |
US11/307,160 Active 2024-07-04 US7375372B2 (en) | 2004-02-11 | 2006-01-26 | Thin film transistor |
US11/624,699 Abandoned US20070114533A1 (en) | 2004-02-11 | 2007-01-19 | Thin film transistor including a lightly doped amorphous silicon channel layer |
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US11/307,160 Active 2024-07-04 US7375372B2 (en) | 2004-02-11 | 2006-01-26 | Thin film transistor |
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Cited By (3)
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US20090090909A1 (en) * | 2007-10-05 | 2009-04-09 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
US20120097955A1 (en) * | 2010-10-21 | 2012-04-26 | Au Optronics Corporation | Thin film transistor and pixel structure having the thin film transistor |
US8383467B2 (en) * | 2008-09-24 | 2013-02-26 | Samsung Electronics Co., Ltd. | Thin film transistor and method of manufacturing the same |
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US20070042536A1 (en) * | 2005-08-17 | 2007-02-22 | Chi-Wen Chen | Thin film transistor and method for manufacturing the same |
CN100403498C (en) * | 2005-08-29 | 2008-07-16 | 友达光电股份有限公司 | Thin-film transistor and its manufacturing method |
TWI605509B (en) * | 2007-09-03 | 2017-11-11 | 半導體能源研究所股份有限公司 | Methods for manufacturing thin film transistor and display device |
TW200915573A (en) * | 2007-09-29 | 2009-04-01 | Chunghwa Picture Tubes Ltd | Thin film transistor, pixel structure and fabricating methods thereof |
US20090090915A1 (en) | 2007-10-05 | 2009-04-09 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistor, display device having thin film transistor, and method for manufacturing the same |
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JP2009099636A (en) * | 2007-10-15 | 2009-05-07 | Hitachi Displays Ltd | Display device and method of manufacturing the same |
JP5311957B2 (en) * | 2007-10-23 | 2013-10-09 | 株式会社半導体エネルギー研究所 | Display device and manufacturing method thereof |
JP5311955B2 (en) * | 2007-11-01 | 2013-10-09 | 株式会社半導体エネルギー研究所 | Method for manufacturing display device |
KR101523353B1 (en) | 2007-12-03 | 2015-05-27 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Thin film transistor and semiconductor device |
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Also Published As
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US20060197087A1 (en) | 2006-09-07 |
US7375372B2 (en) | 2008-05-20 |
US7205171B2 (en) | 2007-04-17 |
US20050176187A1 (en) | 2005-08-11 |
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