US20070047374A1 - Memory controller and memory system - Google Patents
Memory controller and memory system Download PDFInfo
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- US20070047374A1 US20070047374A1 US11/211,861 US21186105A US2007047374A1 US 20070047374 A1 US20070047374 A1 US 20070047374A1 US 21186105 A US21186105 A US 21186105A US 2007047374 A1 US2007047374 A1 US 2007047374A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1066—Output synchronization
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1093—Input synchronization
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
Abstract
A memory controller. A first counter is triggered by rising edges of a data strobe signal and generates a first count value. A second counter is triggered by falling edges of the data strobe signal and generates a second count value. A third counter is triggered by rising edges of an internal clock and generates a third count value. A first buffer uses the first count value as a write address for sequential storage of the data corresponding to the rising edges of the data strobe signal, and sequential outputs the data corresponding to the third count value after a first predetermined period. A second buffer uses the second count value as the write address for sequential storage of the data corresponding to the falling edges of the data strobe signal, and sequential outputs the data corresponding to the third count value after the first predetermined period.
Description
- This patent application is related to a copending U.S. patent application Ser. No. 11/120,517, filed May 2, 2005 and entitled “signal processing circuits and methods, and memory systems”, and the entire contents of which are hereby provided by reference.
- The disclosure relates in general to a memory controller. In particular, the disclosure relates to a memory controller for a double data rate (DDR) synchronous dynamic random access memory (SDRAM).
- Certain types of memory devices generate a clock strobe signal having edges aligned with changes in the read data. A DDR SDRAM transfers data on each rising and falling edge of the clock strobe signal, thereby transferring two data words per clock cycle.
- A read, data synchronization circuit is often used to coordinate the transfer of data to and from a memory device, such as a DDR SDRAM. The read data synchronization circuit provides a local clock signal to the memory device to synchronize read and write operations. The clock strobe signal generated by the memory device with the read data has predefined phase constraints with respect to the local clock signal provided by the read data synchronization circuit. The read data synchronization circuit uses the clock strobe signal to determine when the read data is valid and can therefore be latched. The times at which the read data is latched are preferably synchronized relative to the clock strobe signal so as to latch the read data in the middle of the valid data window.
- Due to varying propagation delays from the read data synchronization circuit's local clock signal and the clock strobe signal received from the memory device, the phase relationship between the captured read data and the local clock signal from one device to the next and can change over time. These changes in phase alignment can be caused by input/output (I/O) pad delay variations, power supply fluctuations, process variations, temperature variations and variations in the clock input to data clock strobe output characteristics of the memory device. In certain cases these changes can be large enough to cause the captured read data to cross a metastable region with respect to the read data synchronization circuit's clock.
- Due to these and other factors, accurate synchronization of captured read data to the read data synchronization circuit's clock requires the phase relationship between the data output clock strobe and the read data synchronization circuit clock to be maintained. Typically, a clock gating technique is employed which can introduce errors into data synchronization.
- U.S. Pat. No. 6,603,706 to Nystuen provides a method and apparatus for synchronization of read data in a read data synchronization circuit, wherein programmable timing signals are provided for use in synchronizing read data.
- However, the method and apparatus for synchronization of read data in a read data synchronization circuit provided by Nystuen requires a programmable logic to adjust latch points for reading data, and software or hardware programming the logic. In addition, since all bits on a bus may not be consentient, programmable logics are required for each bit of data accessing ports, increasing costs.
- An embodiment of a memory controller comprises a first counter triggered by rising edges of a data strobe signal and generating a first count value, a second counter triggered by falling edges of the data strobe signal and generating a second count value, a third counter triggered by rising edges of an internal clock and generating a third count value, a first buffer using the first count value as a write address for sequential storage of the data corresponding to the rising edges of the data strobe signal, and sequential output of the data corresponding to the third count value after a first predetermined period, a second buffer using the second count value as the write address for sequential storage of the data corresponding to the falling edges of the data strobe signal, and sequential output of the data corresponding to the third count value after the first predetermined period.
- An embodiment of a memory system comprises a memory device operative to output data and data strobe signals synchronized with the data according to a memory access request, a memory controller operative to provide the memory access request, comprising a first counter triggered by rising edges of the data strobe signal and generating a first count value, a second counter triggered by falling edges of the data strobe signal and generating a second count value, a third counter triggered by rising edges of an internal clock and generating a third count value, a first buffer using the first count value as a write address for sequential storage of the data corresponding to the rising edges of the data strobe signal, and sequential output of the data corresponding to the third count value after a first predetermined period, and a second buffer using the second count value as the write address for sequential storage of the data corresponding to the falling edges of the data strobe signal, and sequential output of the data corresponding to the third count value after the first predetermined period.
- The invention will become more fully understood from the detailed description, given hereinbelow, and the accompanying drawings. The drawings and description are provided for purposes of illustration only and, thus, are not intended to be limiting of the present invention.
-
FIG. 1 is a block diagram of amemory system 20. -
FIG. 2 is a block diagram of amemory controller 22 according to an embodiment of the invention. -
FIG. 3 is a timing diagram of thememory controller 22 according to an embodiment. -
FIG. 4 is a timing diagram of aDQS rising buffer 42 andDQS falling buffer 44 according to an embodiment. -
FIGS. 5A and 5B are respective timing diagrams ofDQS rising buffer 42 with different data latencies. -
FIG. 6 shows the timing ofDQS rising buffer 42 combined withFIGS. 5A and 5B . -
FIG. 1 is a block diagram of amemory system 20, comprisingmemory controller 22 andDDR memory 24.Memory controller 22 issues READ or WRITE commands to DDR memory through multiple control signals. After receiving the READ command,DDR memory 24 drives multiple data DQ and data strobe DQS respectively fromDQ port 26 and DOSport 28 tomemory controller 22.Memory controller 22 uses DQS to sample signal DQ to obtain read memory data. Normally, oneDOS signal samples -
FIG. 2 is a block diagram ofmemory controller 22 according to an embodiment of the invention.FIG. 3 is a timing diagram ofmemory controller 22 according, to an embodiment of the invention. - The data strobe DOS is provided by
memory controller 22 and driven fromDDR memory 24, passing through system PCB, IC subtract, I/O PAD, and any inter-media betweenDDR memory 24 andmemory controller 22 to reachmemory controller 22. Thus,DQ port 26 andDQS port 28 ofDDR memory 24 respectively provide data DQX and data strobe DQSX tomemory controller 22 delayed by a predetermined period FT, the total delay for data DQ and data strobe DQS passing through the all inter-media betweenmemory controller 22 andDDR memory 24. It is noted that predetermined period FT can be further varied by uncertain factors, such as skew between data strobe DQS and clock due toDDR memory 24 or PCB layout, and working condition and process variation ofmemory controller 22. In addition, adelay circuit 31 is provided to delay the data strobe DQSX to signal DQSY by about a quarter of cycle to meet timing requirements. -
DQS rising counter 32 is triggered by rising edges of the delayed data strobe signal DQSY and generates first count value DQSRCNT corresponding to the number of rising edges of the delayed data strobe signal DQSY.DQS falling counter 34 is triggered by falling edges of the delayed data strobe signal DQSY and generates second count value DQSFCNT corresponding to the number of falling edges of the delayed data strobe signal DQSY.Internal clock counter 36 is triggered by rising edges of internal clock CLK and generates third count value CLKCNT corresponding to the number of rising edges of the internal clock CLK. -
DQS rising buffer 42 andDQS falling buffer 44 each comprise a plurality of buffer entries (43A-43D and 45A-45D) indexed by sequential integral index. In an embodiment of the invention,DQS rising buffer 42 andDQS falling buffer 44 can be achieved by flip flops.FIG. 2 shows respectively four buffer entries inDQS rising buffer 42 andDQS falling buffer 44 as an example. In fact, the number of buffer entries inDQS rising buffer 42 andDQS falling buffer 44 can be set by any natural number in accordance with hardware requirements. -
DQS rising buffer 42 uses first count value DQSRCNT as write address for sequential storage of the data DQX corresponding to the rising edges of the data strobe DQSY to its buffer entries with corresponding index throughdemultiplexer 46A. DOS fallingbuffer 44 uses second count value DQSFCNT as the write address for sequential storage of the data DQX corresponding to the falling edges of the data strobe DQSY to its buffer entries with corresponding index throughmultiplexer 46B. Thus, D0 is written to entry 0 (43A) ofDQS rising buffer 42, D1 to entry 0 (45A) ofDOS falling buffer 44, D2 to entry 1 (43B) ofDOS rising buffer 42, D3 to entry 1 (45B) ofDOS falling buffer 44, and so on, as shown inFIG. 4 . - After the predetermined period SP,
DQS rising buffer 42 sequentially outputs data DQX from its buffer entries with the index corresponding to third count value CLKCNT throughmultiplexer 48A after predetermined period SP.DQS falling buffer 44 sequentially outputs the data DQX from buffer entries with the index corresponding to third count value CLKCNT throughmultiplexer 48B after predetermined period SP. InFIG. 2 , signals DQL and DQH are output respectively frommultiplexers DQS rising buffer 42 andDOS falling buffer 44 cannot be overwritten before being read out bymemory controller 22. -
FIGS. 5A and 5B are respective timing diagrams ofDQS rising buffer 42 with different data-latencies, where FIG. 5A shows timing with smallest practice data latency, and FIG. BB shows that with largest available practice data latency. Using there is one clock cycle between the smallest and the largest practice data latency as an example, the first rising edge of data strobe DQSX shown inFIG. 5A is atclock cycle 3, and that shown inFIG. 5B is atclock cycle 4. It is noted that the timing ofDQS falling buffer 42 may be similar to that ofFIGS. 5A and 5B , but with a phase shifted on the stored data. -
FIG. 6 shows the timing ofDQS rising buffer 42 combined withFIGS. 5A and 5B . InFIG. 6 , DR0(47A), DR1(47B), DR2(47C), and DR3(47D) show the available period for output of data stored inDQS rising buffer 42. In addition,intervals 70 allow further timing variations for thememory controller 22, such as PCB delay. - Accordingly, predetermined period SP can be reduced to improve data latency according to real system environment. In addition, predetermined period FT variation from 0 to multiple clock cycles is allowable, improving error allowance. In addition, the circuit disclosed in the embodiments of the invention can be utilized in other types of source synchronous bus, such as 1394 bus, Universal Serial Bus (USB), Advanced Technology Attachment (ATA), or Accelerated Graphics Port (AGP) interface.
- While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Claims (20)
1. A memory controller for a memory device outputting data and a data strobe signal synchronized with the data according to a memory access request, comprising:
a first counter triggered by rising edges of the data strobe signal and generating a first count value;
a second counter triggered by falling edges of the data strobe signal and generating a second count value;
a third counter triggered by rising edges of an internal clock and generating a third count value;
a first buffer using the first count value as a write address for sequential storage of the data corresponding to the rising edges of the data strobe signal, and sequential output of the data corresponding to the third count value after a first predetermined period; and
a second buffer using the second count value as the write address for sequential storage of the data corresponding to the falling edges of the data strobe signal, and sequential output of the data corresponding to the third count value after the first predetermined period.
2. The memory controller as claimed in claim 1 , wherein the data and the data strobe signal are delayed by a second predetermined period in any intra-media between memory and memory controller.
3. The memory controller as claimed in claim 2 , further comprising a delay circuit operative to delay the data strobe signal by a third predetermined period.
4. The memory controller as claimed in claim 2 , wherein the first predetermined period exceeds the second predetermined period.
5. The memory controller as claimed in claim 1 , wherein the first buffer comprises a plurality of first buffer entries indexed by sequential integral index.
6. The memory controller as claimed in claim 5 , wherein the first buffer stores the data corresponding to the rising edges of the data strobe signal to the first buffer entries with corresponding index.
7. The memory controller as claimed in claim 5 , wherein the first buffer outputs data from the first buffer entries with the index corresponding to the third count value.
8. The memory controller as claimed in claim 1 , wherein the second buffer comprises a plurality of second buffer entries indexed by sequential integral index.
9. The memory controller as claimed in claim 8 , wherein the second buffer stores the data corresponding to the falling edges of the data strobe signal to the second buffer entries with corresponding index.
10. The memory controller as claimed in claim 8 , wherein the second buffer outputs data from the second buffer entries with the index corresponding to the third count value.
11. A memory system, comprising:
a memory device operative to output data and data strobe signals synchronized with the data according to a memory access request;
a memory controller operative to provide the memory access request, comprising:
a first counter triggered by rising edges of the data strobe signal and generating a first count value;
a second counter triggered by falling edges of the data strobe signal and generating a second count value;
a third counter triggered by rising edges of an internal clock and generating a third count value;
a first buffer using the first count value as a write address for sequential storage of the data corresponding to the rising edges of the data strobe signal, and sequential output of the data corresponding to the third count value after a first predetermined period; and
a second buffer using the second count value as the write address for sequential storage of the data corresponding to the falling edges of the data strobe signal, and sequential output of the data corresponding to the third count value after the first predetermined period.
12. The memory system as claimed in claim 11 , wherein the data and the data strobe signal are delayed by a second predetermined period in any intra-media between memory and memory controller.
13. The memory system as claimed in claim 12 , further comprising a delay circuit operative to delay the data strobe signal by a third predetermined period.
14. The memory system as claimed in claim 12 , wherein the first predetermined period exceeds the second predetermined period.
15. The memory system as claimed in claim 11 , wherein the first buffer comprises a plurality of first buffer entries indexed by sequential integral index.
16. The memory system as claimed in claim 15 , wherein the first buffer stores the data corresponding to the rising edges of the data strobe signal to the first buffer entries with corresponding index.
17. The memory system as claimed in claim 15 , wherein the first buffer outputs data from the first buffer entries with the index corresponding to the third count value.
18. The memory system as claimed in claim 11 , wherein the second buffer comprises a plurality of second buffer entries indexed by sequential integral index.
19. The memory system as claimed in claim 18 , wherein the second buffer stores the data corresponding to the falling edges of the data strobe signal to the second buffer entries with corresponding index.
20. The memory system as claimed in claim 18 , wherein the second buffer outputs data from the second buffer entries with the index corresponding to the third count value.
Priority Applications (4)
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US11/211,861 US7177230B1 (en) | 2005-08-25 | 2005-08-25 | Memory controller and memory system |
TW094145803A TWI298503B (en) | 2005-08-25 | 2005-12-22 | Memory controller and memory system |
CNB2006100661813A CN100520956C (en) | 2005-08-25 | 2006-03-24 | Memory controller and memory system |
US11/644,222 US7542371B2 (en) | 2005-08-25 | 2006-12-21 | Memory controller and memory system |
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US11/211,861 US7177230B1 (en) | 2005-08-25 | 2005-08-25 | Memory controller and memory system |
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US11/644,222 Continuation US7542371B2 (en) | 2005-08-25 | 2006-12-21 | Memory controller and memory system |
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Cited By (2)
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US20080100359A1 (en) * | 2006-10-26 | 2008-05-01 | Sanyo Electric Co., Ltd. | Clock regeneration circuit |
WO2008130878A2 (en) * | 2007-04-19 | 2008-10-30 | Rambus Inc. | Techniques for improved timing control of memory devices |
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US7342838B1 (en) * | 2005-06-24 | 2008-03-11 | Lattice Semiconductor Corporation | Programmable logic device with a double data rate SDRAM interface |
US7908507B2 (en) * | 2006-02-28 | 2011-03-15 | Fujitsu Semiconductor Limited | Apparatus and method for masking input of invalid data strobe signal |
US7561481B2 (en) * | 2007-06-11 | 2009-07-14 | Mediatek Inc. | Memory controllers and pad sequence control methods thereof |
US7558151B1 (en) * | 2007-09-25 | 2009-07-07 | Integrated Device Technology, Inc. | Methods and circuits for DDR-2 memory device read data resynchronization |
US7804735B2 (en) * | 2008-02-29 | 2010-09-28 | Qualcomm Incorporated | Dual channel memory architecture having a reduced interface pin requirements using a double data rate scheme for the address/control signals |
US9431091B2 (en) | 2008-06-06 | 2016-08-30 | Uniquify, Inc. | Multiple gating modes and half-frequency dynamic calibration for DDR memory controllers |
US9368172B2 (en) * | 2014-02-03 | 2016-06-14 | Rambus Inc. | Read strobe gating mechanism |
JP2018055330A (en) * | 2016-09-28 | 2018-04-05 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
CN106875966B (en) * | 2017-01-09 | 2020-02-07 | 上海兆芯集成电路有限公司 | Data strobe signal processing system and processing method |
JP2019008859A (en) * | 2017-06-28 | 2019-01-17 | 東芝メモリ株式会社 | Semiconductor device |
US10176862B1 (en) * | 2018-01-26 | 2019-01-08 | Micron Technology, Inc. | Data strobe gating |
CN112804321A (en) * | 2021-01-08 | 2021-05-14 | 广州航天海特系统工程有限公司 | Method, device, equipment and storage medium for caching and forwarding Ethernet data packet |
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- 2005-12-22 TW TW094145803A patent/TWI298503B/en active
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Also Published As
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US7542371B2 (en) | 2009-06-02 |
TWI298503B (en) | 2008-07-01 |
CN100520956C (en) | 2009-07-29 |
US7177230B1 (en) | 2007-02-13 |
TW200709224A (en) | 2007-03-01 |
CN1921002A (en) | 2007-02-28 |
US20070104017A1 (en) | 2007-05-10 |
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