US20060240690A9 - Systems for testing and packaging integrated circuits - Google Patents
Systems for testing and packaging integrated circuits Download PDFInfo
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- US20060240690A9 US20060240690A9 US10/932,552 US93255204A US2006240690A9 US 20060240690 A9 US20060240690 A9 US 20060240690A9 US 93255204 A US93255204 A US 93255204A US 2006240690 A9 US2006240690 A9 US 2006240690A9
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
- G01R31/2889—Interfaces, e.g. between probe and tester
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/06711—Probe needles; Cantilever beams; "Bump" contacts; Replaceable probe pins
- G01R1/06716—Elastic
- G01R1/06727—Cantilever beams
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/06711—Probe needles; Cantilever beams; "Bump" contacts; Replaceable probe pins
- G01R1/06755—Material aspects
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
- G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
- G01R1/07342—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card the body of the probe being at an angle other than perpendicular to test object, e.g. probe card
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R3/00—Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments, e.g. of probe tips
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
- G01R31/2863—Contacting devices, e.g. sockets, burn-in boards or mounting fixtures
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
- G01R31/2874—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/50—Testing arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01027—Cobalt [Co]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01045—Rhodium [Rh]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4092—Integral conductive tabs, i.e. conductive parts partly detached from the substrate
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- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- General Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Environmental & Geological Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Materials Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Electrochemistry (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- General Chemical & Material Sciences (AREA)
- Mechanical Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Measuring Leads Or Probes (AREA)
Abstract
Description
- This application claims priority to U.S. Provisional Patent Application Ser. No. 60/385,252, filed May 31, 2002; and is a Continuation-in-part of U.S. patent application Ser. No. 10/311,109, filed Dec. 13, 2002, which is a national filing of International Patent Application No. PCT/US01/19063 filed Jun. 14, 2001, which claims priority to U.S. Provisional Patent Application Ser. No. 60/212,126 filed Jun. 16, 2000.
- The invention relates to the field of integrated circuit (IC) package and wafer design, as well as to the fields of interconnection, testing and burn-in structures and processes. More particularly, the invention relates to improvements in photolithography-patterned spring contacts and enhanced system interconnect assemblies having photolithography-patterned spring contacts for use in the testing or burn-in of integrated circuits, and for interconnecting a large number of signals between electronic systems or subsystems.
- Integrated circuits are typically tested in wafer form (wafer sort) before they are packaged. During wafer sort, integrated circuits are tested one or few at a time, even though there may be hundreds or even thousands of the same integrated circuit located on a wafer. The packaged integrated circuits are then tested again, and burned-in, if necessary.
- Prior to dicing the integrated circuits into individual dice on the wafer, the integrated circuits are placed (built) precisely on the wafer, but after dicing and separating the integrated circuits into individual dice for packaging and test, the packaged dices are handled individually, loosing the parallelism in handling.
- Parallel testing on the wafer level has been limited in number and has so far been limited to low pin count devices, due to the difficulty in managing the large number of interconnects, and the limited amount of electronics which can conventionally be placed close to a wafer under test.
- Attempts have also been made to burn-in ICs while in the wafer form. However, wafer-level burn-in is plagued with multiple problems, such as thermal expansion mismatch between the connector and the silicon wafer under test. Conventional structures, such as large area substrates having a large plurality of fanout traces which are electrically connected to pin or socket connectors, are typically implemented to manage connections between the IC under test, test electronics, and power management electronics.
- The density of integrated circuits on semiconductor wafers continues to increase, due to semiconductor device scaling, with more gates and memory bits per unit area of silicon. As well, the use of larger semiconductor wafers (e.g. often having a nominal diameter of 8 inches or 12 inches) has become common. However, semiconductor test costs have increased on a cost per unit area of silicon basis. Therefore, semiconductor test costs have increased disproportionately over time, to become a greater percentage of the total manufacturing cost for each integrated circuit device.
- Furthermore, advances in chip scale packaging (CSP) and other forms of small footprint packages have often made traditional packaged IC handlers obsolete for testing and burn-in.
- In some conventional large surface area substrate integrated circuit (IC) test boards, electrical contacts between the test board and an integrated circuit wafer are typically provided by tungsten needle probes. However, tungsten needle probe technology is not able to meet the interconnect requirements of advanced semiconductors having higher pin counts, smaller pad pitches, and higher clock frequencies.
- While emerging technologies have provided spring probes for different probing applications, most probes have inherent limitations, such as limited pitch, limited pin count, varying levels of flexibility, limited probe tip geometries, limitations of materials, and/or high costs of fabrication.
- K. Banerji, A. Suppelsa, and W. Mullen III, Selectively Releasing Conductive Runner and Substrate Assembly Having Non-Planar Areas, U.S. Pat. No. 5,166,774 (24 Nov. 1992) disclose a runner and substrate assembly which comprises “a plurality of conductive runners adhered to a substrate, a portion of at least some of the conductive runners have non-planar areas with the substrate for selectively releasing the conductive runner from the substrate when subjected to a predetermined stress”.
- A. Suppelsa, W. Mullen II and G. Urbish, Selectively Releasing Conductive Runner and Substrate Assembly, U.S. Pat. No. 5,280,139 (18 Jan. 1994) disclose a runner and substrate assembly which comprises “a plurality of conductive runners adhered to a substrate, a portion of at least some of the conductive runners have a lower adhesion to the substrate for selectively releasing the conductive runner from the substrate when subjected to a predetermined stress”.
- D. Pedder, Bare Die Testing, U.S. Pat. No. 5,786,701 (28 Jul. 1998) disclose a testing apparatus for testing integrated circuits (ICs) at the bare die stage, which includes “a testing station at which microbumps of conductive material are located on interconnection trace terminations of a multilayer interconnection structure, these terminations being distributed in a pattern corresponding to the pattern of contact pads on the die to be tested. To facilitate testing of the die before separation from a wafer using the microbumps, the other connections provided to and from the interconnection structure have a low profile”.
- D. Grabbe, I. Korsunsky and R. Ringler, Surface Mount Electrical Connector, U.S. Pat. No. 5,152,695 (6 Oct. 1992) disclose a connector for electrically connecting a circuit between electronic devices, in which “the connector includes a platform with cantilevered spring arms extending obliquely outwardly therefrom. The spring arms include raised contact surfaces and in one embodiment, the geometry of the arms provide compound wipe during deflection”.
- H. Iwasaki, H. Matsunaga, and T. Ohkubo, Partly Replaceable Device for Testing a Multi-Contact Integrated Circuit Chip Package, U.S. Pat. No. 5,847,572 (8 Dec. 1998) disclose “a test device for testing an integrated circuit (IC) chip having side edge portions each provided with a set of lead pins. The test device comprises a socket base, contact units each including a contact support member and socket contact numbers, and anisotropic conductive sheet assemblies each including an elastic insulation sheet and conductive members. The anisotropic conductive sheet assemblies are arranged to hold each conductive member in contact with one of the socket contact members of the contact units. The test device further comprises a contact retainer detachably mounted on the socket base to bring the socket contact members into contact with the anisotropic sheet assemblies to establish electrical communication between the socket contact members and the conductive members of the anisotropic conductive sheet assemblies. Each of the contact units can be replaced by a new contact unit if the socket contact members partly become fatigued, thereby making it possible to facilitate the maintenance of the test device. Furthermore, the lead pins of the IC chip can be electrically connected to a test circuit board with the shortest paths formed by part of the socket contact members and the conductive members of the anisotropic conductive sheet assemblies”.
- W. Berg, Method of Mounting a Substrate Structure to a Circuit Board, U.S. Pat. No. 4,758,9278 (19 Jul. 1988) discloses “a substrate structure having contact pads is mounted to a circuit board which has pads of conductive material exposed at one main face of the board and has registration features which are in predetermined positions relative to the contact pads of the circuit board. The substrate structure is provided with leads which are electrically connected to the contact pads of the substrate structure and project from the substrate structure in cantilever fashion. A registration element has a plate portion and also has registration features which are distributed about the plate portion and are engageable with the registration features of the circuit board, and when so engaged, maintain the registration element against movement parallel to the general plane of the circuit board. The substrate structure is attached to the plate portion of the registration element so that the leads are in predetermined position relative to the registration features of the circuit board, and in this position of the registration element the leads of the substrate structure overlie the contact pads of the circuit board. A clamp member maintains the leads in electrically conductive pressure contact with the contact pads of the circuit board”.
- D. Sarma, P. Palanisamy, J. Hearn and D. Schwarz, Controlled Adhesion Conductor, U.S. Pat. No. 5,121,298 (9 Jun. 1992) disclose “Compositions useful for printing controllable adhesion conductive patterns on a printed circuit board include finely divided copper powder, a screening agent and a binder. The binder is designed to provide controllable adhesion of the copper layer formed after sintering to the substrate, so that the layer can lift off the substrate in response to thermal stress. Additionally, the binder serves to promote good cohesion between the copper particles to provide good mechanical strength to the copper layer so that it can tolerate lift off without fracture”.
- R. Mueller, Thin-Film Electrothermal Device, U.S. Pat. No. 4,423,401 (27 Dec. 1983) discloses “A thin film multilayer technology is used to build micro miniature electromechanical switches having low resistance metal-to-metal contacts and distinct on-off characteristics. The switches, which are electrothermally activated, are fabricated on conventional hybrid circuit substrates using processes compatible with those employed to produce thin-film circuits. In a preferred form, such a switch includes a cantilever actuator member comprising a resiliently bendable strip of a hard insulating material (e.g. silicon nitride) to which a metal (e.g. nickel) heating element is bonded. The free end of the cantilever member carries a metal contact, which is moved onto (or out of) engagement with an underlying fixed contact by controlled bending of the member via electrical current applied to the heating element”.
- S. Ibrahim and J. Elsner, Multi-Layer Ceramic Package, U.S. Pat. No. 4,320,438 (16 Mar. 1982) disclose “In a multi-layer package, a plurality of ceramic lamina each has a conductive pattern, and there is an internal cavity of the package within which is bonded a chip or a plurality of chips interconnected to form a chip array. The chip or chip array is connected through short wire bonds at varying lamina levels to metallized conductive patterns thereon, each lamina level having a particular conductive pattern. The conductive patterns on the respective lamina layers are interconnected either by tunneled through openings filled with metallized material, or by edge formed metallizations so that the conductive patterns ultimately connect to a number of pads at the undersurface of the ceramic package mounted onto a metalized board. There is achieved a high component density; but because connecting leads are “staggered” or connected at alternating points with wholly different package levels, it is possible to maintain a 10 mil spacing and 10 mil size of the wire bond lands. As a result, there is even greater component density but without interference of wire bonds one with the other, this factor of interference being the previous limiting factor in achieving high component density networks in a multi layer ceramic package”.
- F. McQuade, and J. Lander, Probe Assembly for Testing Integrated Circuits, U.S. Pat. No. 5,416,429 (16 May 1995) disclose a probe assembly for testing an integrated circuit, which “includes a probe card of insulating material with a central opening, a rectangular frame with a smaller opening attached to the probe card, four separate probe wings each comprising a flexible laminated member having a conductive ground plane sheet, an adhesive dielectric film adhered to the ground plane, and probe wing traces of spring alloy copper on the dielectric film. Each probe wing has a cantilevered leaf spring portion extending into the central opening and terminates in a group of aligned individual probe fingers provided by respective terminating ends of said probe wing traces. The probe fingers have tips disposed substantially along a straight line and are spaced to correspond to the spacing of respective contact pads along the edge of an IC being tested. Four spring clamps each have a cantilevered portion which contact the leaf spring portion of a respective probe wing, so as to provide an adjustable restraint for one of the leaf spring portions. There are four separate spring clamp adjusting means for separately adjusting the pressure restraints exercised by each of the spring clamps on its respective probe wing. The separate spring clamp adjusting means comprise spring biased platforms each attached to the frame member by three screws and spring washers so that the spring clamps may be moved and oriented in any desired direction to achieve alignment of the position of the probe finger tips on each probe wing”.
- D. Pedder, Structure for Testing Bare Integrated Circuit Devices, European Patent Application No.
EP 0 731 369 A2 (Filed 14 Feb. 1996), U.S. Pat. No. 5,764,070 (9 Jun. 1998) discloses a test probe structure for making connections to a bare IC or a wafer to be tested, which comprises “a multilayer printed circuit probe arm which carries at its tip an MCM-D type substrate having a row of microbumps on its underside to make the required connections. The probe arm is supported at a shallow angle to the surface of the device or wafer, and the MCM-D type substrate is formed with the necessary passive components to interface with the device under test. Four such probe arms may be provided, one on each side of the device under test”. - B. Eldridge, G. Grube, I. Khandros, and G. Mathieu, Method of Mounting Resilient Contact Structure to Semiconductor Devices, U.S. Pat. No. 5,829,128 (3 Nov. 1998), Method of Making Temporary Connections Between Electronic Components, U.S. Pat. No. 5,832,601 (10 Nov. 1998), Method of Making Contact Tip Structures, U.S. Pat. No. 5,864,946 (2 Feb. 1999), Mounting Spring Elements on Semiconductor Devices, U.S. Pat. No. 5,884,398 (23 Mar. 1999), Method of Burning-In Semiconductor Devices, U.S. Pat. No. 5,878,486 (9 Mar. 1999), and Method of Exercising Semiconductor Devices, U.S. Pat. No. 5,897,326 (27 Apr. 1999), disclose “Resilient contact structures are mounted directly to bond pads on semiconductor dies, prior to the dies being singulated (separated) from a semiconductor wafer. This enables the semiconductor dies to be exercised (e.g. tested and/or burned-in) by connecting to the semiconductor dies with a circuit board or the like having a plurality of terminals disposed on a surface thereof. Subsequently, the semiconductor dies may be singulated from the semiconductor wafer, whereupon the same resilient contact structures can be used to effect interconnections between the semiconductor dies and other electronic components (such a wiring substrates, semiconductor packages, etc.). Using the all-metallic composite interconnection elements of the present invention as the resilient contact structures, burn-in can be performed at temperatures of at least 150° C., and can be completed in less than 60 minutes”. While the contact tip structures disclosed by B. Eldridge et al. provide resilient contact structures, the structures are each individually mounted onto bond pads on semiconductor dies, requiring complex and costly fabrication. As well, the contact tip structures are fabricated from wire, which often limits the resulting geometry for the tips of the contacts. Furthermore, such contact tip structures have not been able to meet the needs of small pitch applications (e.g. typically on the order of 50 μm spacing for a peripheral probe card, or on the order of 75 μm spacing for an area array).
- T. Dozier II, B. Eldridge, G. Grube, I. Khandros, and G. Mathieu, Sockets for Electronic Components and Methods of Connecting to Electronic Components, U.S. Pat. No. 5,772,451 (30 Jun. 1998) disclose “Surface-mount, solder-down sockets permit electronic components such as semiconductor packages to be releaseably mounted to a circuit board. Resilient contact structures extend from a top surface of a support substrate, and solder-ball (or other suitable) contact structures are disposed on a bottom surface of the support substrate. Composite interconnection elements are used as the resilient contact structures disposed atop the support substrate. In any suitable manner, selected ones of the resilient contact structures atop the support substrate are connected, via the support substrate, to corresponding ones of the contact structures on the bottom surface of the support substrate. In an embodiment intended to receive an LGA-type semiconductor package, pressure contact is made between the resilient contact structures and external connection points of the semiconductor package with a contact force which is generally normal to the top surface of the support substrate. In an embodiment intended to receive a BGA-type semiconductor package, pressure contact is made between the resilient contact structures and external connection points of the semiconductor package with a contact force which is generally parallel to the top surface of the support substrate”.
- Other emerging technologies have disclosed probe tips on springs which are fabricated in batch mode processes, such as by thin-film or micro-electronic mechanical system (MEMS) processes.
- D. Smith and S. Alimonda, Photolithographically Patterned Spring Contact, U.S. Pat. No. 5,613,861 (25 Mar. 1997), U.S. Pat. No. 5,848,685 (15 Dec. 1998), and International Patent Application No. PCT/
US 96/08018 (Filed 30 May 1996), disclose a photolithography patterned spring contact, which is “formed on a substrate and electrically connects contact pads on two devices. The spring contact also compensates for thermal and mechanical variations and other environmental factors. An inherent stress gradient in the spring contact causes a free portion of the spring to bend up and away from the substrate. An anchor portion remains fixed to the substrate and is electrically connected to a first contact pad on the substrate. The spring contact is made of an elastic material and the free portion compliantly contacts a second contact pad, thereby contacting the two contact pads”. While the photolithography patterned springs, as disclosed by Smith et al., are capable of satisfying many IC probing needs, the springs are small, and provide little vertical compliance to handle the planarity compliance needed in the reliable operation of many current IC prober systems. Vertical compliance for many probing systems is typically on the order of 0.004″-0.010″, which often requires the use of tungsten needle probes. - While interposers have been used as an interconnecting structure, conventional interposers have been limited by pitch density, as well as by long term reliability over elevated temperatures, such as commonly seen in test or burn-in environments.
- While probe substrates have been used as an interconnecting structure, such as for probing solder bumped wafers, the conventional probe substrates are often expensive, and/or require long lead times. Vertical probes, such as the Cobra Probe™, are currently available from International Business Machines, of San Jose, Calif. A Microspring™ probe assembly is currently available from Form Factor, Inc., of Livermore Calif.
- T. Distefano, J. Smith and A. Faraci, Fixtures and Methods for Lead Bonding and Deformation, U.S. Pat. No. 6,080,603 (27 Jun. 2000), disclose “In a method for mounting a sheet-like microelectronic element, the sheet-like element comprises a dielectric layer having a top surface and a bottom surface and is first bonded to an expansion ring. The expansion ring is then heated to stretch the sheet-like element. A frame ring, having an external diameter smaller than the internal diameter of the expansion ring, is then bonded to the sheet-like element. A plurality of leads are formed on the bottom surface of the sheet-like element, the leads including bonding pads. In other embodiments, a method is provided for bonding bond pads on a sheet-like microelectronic element to contacts on a microelectronic component.”
- T. Distefano and J. Smith, Methods of Making Connections to a Microelectronic Unit, U.S. Pat. No. 6,044,548 (4 Apr. 2000) disclose “A method of making connections to a microelectronic unit includes the steps of providing a connection component having a flexible dielectric top sheet, a plurality of terminals on the top sheet and a plurality of electrically conductive, elongated flexible leads connected to the terminals and extending side-by-side downwardly from the terminals away from the top sheet to bottom ends remote from the top sheet. The connection component is then engaged with a front surface of a microelectronic unit having an array of contacts thereon while subjecting the connection component and the microelectronic unit to heat and pressure so that bottom ends of the leads remote from the top sheet bond with the contacts on the microelectronic unit to form electrical connections therewith.”
- M. Beroz, B. Haba and C. Pickett, Lead Formation Using Grids, U.S. Pat. No. 6,063,648 (16 May 2000) disclose “A component for making microelectronic units includes a grid of interspersed leads with ends of the various leads being connected to one another by frangible elements. One end of each lead is bonded to a top element and the other end of each lead is bonded to a bottom element. The top and bottom elements are moved away from one another, thereby breaking the frangible elements and deforming the leads towards a vertically extensive disposition. A flowable composition such as dielectric material may be injected around the leads during or after the moving step. The resulting unit may be used to form permanent or temporary connections between microelectronic elements.”
- K. Gilleo, G. Grube and G. Mathieu, Compliant Semiconductor Chip Assemblies and Methods of Making Same, U.S. Pat. No. 6,020,220 (1 Feb. 2000) disclose “A semiconductor chip package assembly is mounted to contact pads on a die. A compliant interposer layer is disposed between the die and a dielectric substrate wiring layer. The contacts on the die are connected to terminals on the compliant interposer layer by means of a compliant, conductive polymer extending through apertures in the interposer layer. Compliancy in the interposer layer and in the conductive polymer permits relative movement of the terminals on the dielectric substrate wiring layer to the contacts on the die and hence relieves the shear forces caused by differential thermal expansion. The arrangement provides a compact packaged structure similar to that achieved through flip-chip bonding, but with markedly increased resistance to thermal cycling damage. Further, the packaged structure allows the standardization of the packages such that several companies can make competing chips that are packaged such that the resultant packaged structures are roughly the same as far as the end user is concerned.”
- T. DiStefano, Z. Kovac and J. Smith, Bondable Compliant Pads for Packaging of a Semiconductor Chip and Method Therefor, U.S. Pat. No. 6,030,856 (29 Feb. 2000) disclose “A method of making a microelectronic package includes providing first and second microelectronic elements having electrically conductive parts and disposing a resilient element having one or more intermediary layers capable of being wetted by an adhesive between the microelectronic elements. The resilient element includes fibrous material, a fibrous matrix and/or voids formed at the intermediary layers thereof. An adhesive is provided between the intermediary layers and the microelectronic elements. The adhesive is then cured while it remains in contact with the intermediary layers for bonding the resilient element and the microelectronic elements. The electrically conductive parts are then bonded together to form electrical interconnections. A microelectronic package comprising a resilient element including one or more intermediary layers capable of being wetted by an adhesive is also provided.”
- P. Bellaar, T. DiStefano, J. Fjelstad, C. Pickett and J. Smith, Microelectronic Component with Rigid Interposer, U.S. Pat. No. 6,002,168 (14 Dec. 1999) disclose “A microelectronic component for mounting a rigid substrate, such as a hybrid circuit to a rigid support substrate, such as a printed circuit board. The microelectronic component includes a rigid interposer which may have a chip mounted on its first surface; a pattern of contacts on the rigid interposer; a flexible interposer overlying the second surface of the rigid interposer; a pattern of terminals on the flexible interposer; flexible leads; and solder coated copper balls mounted on the flexible interposer. The microelectronic component may have a socket assembly mounted on the first surface of the rigid interposer. The microelectronic component may be mounted on a rigid support substrate.”
- B. Eldridge, G. Grube, I. Khandros and G. Mathieu, Method of Making Contact Tip Structures, U.S. Pat. No. 5,864,946 (2 Feb. 1999) disclose “Resilient contact structures are mounted directly to bond pads on semiconductor dies, prior to the dies being singulated (separated) from a semiconductor wafer. This enables the semiconductor dies to be exercised (e.g., tested and/or burned-in) by connecting to the semiconductor dies with a circuit board or the like having a plurality of terminals disposed on a surface thereof. Subsequently, the semiconductor dies may be singulated from the semiconductor wafer, whereupon the same resilient contact structures can be used to effect interconnections between the semiconductor dies and other electronic components (such as wiring substrates, semiconductor packages, etc.). Using the all-metallic composite interconnection elements of the present invention as the resilient contact structures, burn-in can be performed at temperatures of at least 150° C., and can be completed in less than 60 minutes.”
- B. Eldridge, G. Grube, I. Khandros and G. Mathieu, Wafer-Level Test and Burn-In, and Semiconductor Process, U.S. Pat. No. 6,032,356, disclose “Resilient contact structures are mounted directly to bond pads on semiconductor dies, prior to the dies being singulated (separated) from a semiconductor wafer. This enables the semiconductor dies to be exercised (e.g., tested and/or burned-in) in) by connecting to the semiconductor dies with a circuit board or the like having a plurality of terminals disposed on a surface thereof. Subsequently, the semiconductor dies may be singulated from the semiconductor wafer, whereupon the same resilient contact structures can be used to effect interconnections between the semiconductor dies and other electronic components (such as wiring substrates, semiconductor packages, etc.). Using the all-metallic composite interconnection elements of the present invention as the resilient contact structures, burn-in can be performed at temperatures of at least 150° C., and can be completed in less than 60 minutes.”
- D. Hembree, W. Farnworth and J. Wark, Force Applying Probe Card and Test System for Semiconductor Wafers, U.S. Pat. No. 6,078,186 (20 Jun. 2000) disclose “A probe card for testing a semiconductor wafer, a test method, and a test system employing the probe card are provided. The probe card includes: a substrate; an interconnect slidably mounted to the substrate; and a force applying mechanism for biasing contacts on the interconnect into electrical engagement with contacts on the wafer. The force applying mechanism includes spring loaded electrical connectors that provide electrical paths to the interconnect, and generate a biasing force. The biasing force is controlled by selecting a spring constant of the electrical connectors, and an amount of Z-direction overdrive between the probe card and wafer. The probe card also includes a leveling mechanism for leveling the interconnect with respect to the wafer.”
- It would be advantageous to provide a chip scale package structure which comprises compliant electrical interconnections which can be built directly on the integrated circuit wafer without additional packaging steps, and is compatible with current IC processing lines. It would also be advantageous to provide an interposer structure having compliant high density electrical interconnections which can be manufactured using batch processes. Furthermore, it would be advantageous to provide a probe contactor structure having compliant high density electrical interconnections at lower force than conventional interposer techniques, which can be manufactured using batch processes.
- The round trip transit time between a device under test and conventional test equipment is often longer then the stimulus to response times of high speed electronic circuits. It would be advantageous to provide a test interface system which reduces this transit time, by placing high speed test electronics in close proximity of the device under test, while meeting space and cost constraints. Furthermore, it would be advantageous to provide a test interface system which minimizes the cost, complexity, tooling, and turn around time required to change the test structure for the testing of different devices. The development of such a system would constitute a major technological advance.
- It would be advantageous to provide a test interface system which provides probe contact with many, hundreds, or even hundreds of thousands of pads for one or more separated devices which are mounted on a compliant wafer carrier, such as for massively parallel testing and/or burn-in applications, wherein the pads may be in close proximity of one another, with a minimum spacing approaching 1 mil or less, while providing a uniform force and minimizing pad damage over the entire wafer. It would also be advantageous to provide such a test interface system which organizes and manages the interconnections between the devices under test and the tester electronics, while maintaining signal integrity and power and ground stability, and assures that no two or more adjacent pads are contacted by a single test probe tip. Furthermore, it would be advantageous to provide such a test structure which preferably provides planarity compliance with the devices under test. The development of such a system would constitute a further technological advance.
- In addition, it would be advantageous to provide such a test system which preferably provides continuous contact with many, hundreds, or even hundreds of thousands of pads for one or more devices on a compliant wafer carrier over a wide temperature range, while providing thermal isolation between the test electronics and the devices under test. As well, it would be advantageous to provide a system for separate thermal control of the test system and of the devices under test.
- It would also be advantageous to provide a test interface system which may be used to detect power to ground shorts in any die quickly, and to isolate power from a die having a detected power to ground short, before damage is done to the test electronics. In addition, it would be advantageous to provide a test interface structure which can detect that the contacts to many, hundreds, or even hundreds of thousands of pads are reliably made and are each of the contacts are within the contact resistance specification, to assure that the self inductance and self capacitance of each signal line are below values that would adversely affect test signal integrity, and to assure that the mutual inductance and mutual capacitance between pairs of signal lines and between signal lines and power or ground lines are below values that would adversely affect test signal integrity. As well, it would also be advantageous to provide a test interface structure which provides stimulus and response detection and analysis to many, hundreds, or even thousands of die under test in parallel, and which preferably provides diagnostic tests to a failed die, in parallel with the continued testing of all other die.
- Furthermore, it would be advantageous to provide a large array interface system which can reliably and repeatedly establish contact to many, hundreds, or even hundreds of thousands of pads, without the need to periodically stop and inspect and/or clean the probe interface structure.
- It would also be advantageous to provide a system for massively parallel interconnections between electrical components, such as between computer systems, which utilize spring probes within the interconnection structure, to provide high pin counts, small pitches, cost-effective fabrication, and customizable spring tips. The development of such a method and apparatus would constitute a major technological advance.
- Several embodiments of stress metal springs are disclosed, which typically comprise a plurality of stress metal layers that are established on a substrate, which are then controllably patterned and partially released from the substrate. An effective rotation angle is typically created in the formed stress metal springs, defining a looped spring structure. The formed springs provide high pitch compliant electrical contacts for a wide variety of interconnection structures, including chip scale semiconductor packages, high density interposer connectors, and probe contactors. Several embodiments of massively parallel interface integrated circuit test assemblies are also disclosed, comprising one or more substrates having stress metal spring contacts, to establish connections between one or more separated integrated circuits on a compliant wafer carrier, and use one or more test modules which are electrically connected to the integrated circuits on the compliant wafer carrier through the substrates. The massively parallel interface assemblies provide tight pad pitch and compliance, and preferably enable the parallel testing or burn-in of multiple ICs. In some preferred embodiments, the massively parallel interface assembly structures include separable standard electrical connector components, which reduces assembly manufacturing cost and manufacturing time. These massively parallel interface structures and assemblies enable high speed testing of separated integrated circuit devices affixed to a compliant carrier, and allow test electronics to be located in close proximity to the integrated circuit devices under test. Preferred embodiments of the massively parallel interface assemblies provide thermal expansion matching to the wafer under test, and provide a thermal path for system electronic. Alternate massively parallel interface structures provide massively parallel connection interfaces, which may be used in a wide variety of circuitry, such as for interconnecting computers in a network, or for interconnecting other electronic circuitry.
-
FIG. 1 is a plan view of a linear array of photolithographically patterned springs, prior to release from a substrate; -
FIG. 2 is a perspective view of a linear array of photolithographically patterned springs, after release from a substrate; -
FIG. 3 is a side view of a first, short length photolithographically patterned spring, having a first effective radius and height after the short length spring is released from a substrate; -
FIG. 4 is a side view of a second, long length photolithographically patterned spring, having a second large effective radius and height after the long length spring is released from a substrate; -
FIG. 5 is a perspective view of opposing photolithographic springs, having an interleaved spring tip pattern, before the springs are released from a substrate; -
FIG. 6 is a perspective view of opposing photolithographic springs, having an interleaved spring tip pattern, after the springs are released from a substrate; -
FIG. 7 is a top view of a first opposing pair of interleaved multiple-point photolithographic spring probes, in contact with a single trace on an integrated circuit device, and a second opposing pair of interleaved multiple-point photolithographic spring probes, in contact with a single pad on the integrated circuit device; -
FIG. 8 is a plan view of opposing single-point photolithographic spring probes, before the springs are released from a substrate; -
FIG. 9 is a top view of parallel and opposing single-point photolithographic spring probes, after the springs are released from a substrate, in contact with a single pad on an integrated circuit device; -
FIG. 10 is a front view of a shoulder-point photolithographic spring probe; -
FIG. 11 is a partial cross-sectional side view of a shoulder-point photolithographic spring in contact with a trace on an integrated circuit device; -
FIG. 12 is a perspective view of a multiple shoulder-point photolithographic spring probe; -
FIG. 13 is a partial cross-sectional view of a multi-layered spring probe substrate providing controlled impedance and integrated components; -
FIG. 14 is a partial plan view of a substrate, in which a plurality of trace distribution regions are defined on the probe surface of the substrate, between a plurality of spring probes and a plurality of via contacts; -
FIG. 15 is a plan layout view of an integrated circuit having stress metal springs connected to IC pads, as laid out on the IC substrate surface, before release from the substrate surface; -
FIG. 16 is a plan layout view of an integrated circuit having stress metal springs connected to IC pads and extending from the substrate surface; -
FIG. 17 is a partial cutaway view of an integrated circuit having looped stress metal springs connected to IC pads and extending from the substrate surface, wherein a portion of the stress metal springs are embedded within a support substrate; -
FIG. 18 is a side view of integrated circuit devices on a semiconductor wafer; -
FIG. 19 is a side view of a semiconductor wafer having integrated circuit devices, which is mounted to a compliant wafer carrier substrate; -
FIG. 20 is a side view which shows the separation between integrated circuits for a semiconductor wafer which is mounted to a compliant wafer carrier substrate; -
FIG. 21 is a side view showing separated integrated circuits on a compliant wafer carrier substrate which is mounted to a test fixture; -
FIG. 22 is a side cross-sectional view of a stress metal spring interposer; -
FIG. 23 is a side cross-sectional view of a stress metal spring interposer having formed bumps on second surface contact region; -
FIG. 24 is a side cross-sectional view of a plated stress metal spring interposer; -
FIG. 25 is a side cross-sectional view of a stress metal spring interposer having filled bumps on a first surface contact region, and looped stress metal springs which partially extend beyond a polymer interposer layer; -
FIG. 26 is a side cross-sectional view of a stress metal spring interposer in which the interposer layer comprises a plurality of polymer layers; -
FIG. 27 is a side cross-sectional view of a stress metal spring interposer in which the stress metal springs have an effective spring angle less than 90 degrees; -
FIG. 28 is a partial view of a square leading end of a looped stress metal spring;FIG. 29 is a partial view of a pointed leading end of a looped stress metal spring; -
FIG. 30 is a partial view of a pointed leading end of a looped stress metal spring, which further comprises retaining grooves; -
FIG. 31 is a partial view of a pointed leading end of a looped stress metal spring, which further comprises retaining ledges; -
FIG. 32 is a plan view of a contact area of a looped stress metal spring, in which the contact area comprises an expanded rectangular contact region; -
FIG. 33 is a plan view of a contact area of a looped stress metal spring, in which the contact area comprises an expanded octagonal contact region; -
FIG. 34 is a plan view of a contact area of a looped stress metal spring, in which the contact area comprises an expanded diamond-shaped contact region; -
FIG. 35 is view of a first step of a stress metal spring interposer construction process, in which a sacrificial substrate is provided; -
FIG. 36 is a view of a second step of a stress metal spring interposer construction process, in which one or more stress metal spring layers are established on the sacrificial substrate; -
FIG. 37 is a view of a third step of a stress metal spring interposer construction process, in which non-planar portions of the stress metal springs extending from the sacrificial substrate are controllably formed; -
FIG. 38 is a view of a fourth step of a stress metal spring interposer construction process, in which an interposer substrate is applied on the sacrificial substrate and over the stress metal springs; -
FIG. 39 is a view of a fifth step of a stress metal spring interposer construction process, in which an outer portion of the applied interposer substrate is removed to access upper contact portions of the stress metal springs; -
FIG. 40 is a view of a sixth step of a stress metal spring interposer construction process, in which the sacrificial substrate is removed from the interposer substrate, exposing the lower contact portions of the stress metal springs; -
FIG. 41 is a side cross-sectional view of a stress metal spring contactor having contact areas extending from an elastomeric substrate; -
FIG. 42 is a side cross-sectional view of a stress metal spring contactor having bumped contact areas extending from an elastomeric substrate; -
FIG. 43 is a side cross-sectional view of a plated stress metal spring contactor having contact areas extending from an elastomeric substrate; -
FIG. 44 is a side cross-sectional view of a plated stress metal spring contactor having contact areas extending from the contactor substrate; -
FIG. 45 is a side cross-sectional view of a stress metal spring contactor having looped stress metal springs which partially extend beyond a polymer layer; -
FIG. 46 is a side cross-sectional view of a stress metal spring contactor in which the support layer comprises a plurality of polymer layers; -
FIG. 47 is a side cross-sectional view of a stress metal spring contactor in which the stress metal springs have an effective spring angle less than 90 degrees; -
FIG. 48 is a view of a first step of a stress metal spring contactor construction process, in which a contactor substrate having vias is provided; -
FIG. 49 is a view of a second step of a stress metal spring contactor construction process, in which in which one or more stress metal spring layers are established on the contactor substrate; -
FIG. 50 is a view of a third step of a stress metal spring contactor construction process, in which in which non-planar portions of the stress metal springs extending from the contactor substrate are controllably formed; -
FIG. 51 is a view of a preferred fourth step of a stress metal spring contactor construction process, in which the formed non-planar portions of the stress metal springs extending from the contactor substrate are controllably plated; -
FIG. 52 is a view of a fifth step of a stress metal spring contactor construction process, in which a secondary substrate is established over the formed non-planar portions of the stress metal springs extending from the contactor substrate; -
FIG. 53 is a view of a sixth step of a stress metal spring contactor construction process, in which an outer portion of the applied secondary substrate is removed to access upper contact portions of the stress metal springs; -
FIG. 54 is a side cross-sectional view of a stress metal spring contactor having a spring probe contact area extending from the contactor substrate, in which a connection is established between the stress metal spring contactor and a printed wiring board though a solder ball contact; -
FIG. 55 is a partial cutaway assembly view of a massively parallel test assembly having test electronics located in close proximity to the carrier-mounted integrated circuit devices under test; -
FIG. 56 is a partial perspective view of a massively parallel interconnection assembly; -
FIG. 57 is a partial expanded cross-sectional view of a massively parallel test assembly having an intermediate system board, which shows staged pitch and distribution across integrated circuit dies on a compliant carrier, a system board, and a flex circuit having a pad matrix; -
FIG. 58 is an expanded layer plan view of integrated circuit devices on a wafer, a circular substrate, and a system board; -
FIG. 59 is an expanded layer plan view of carrier-mounted integrated circuit devices which are directly connectable to a system board; -
FIG. 60 is a partial cross-sectional view of one embodiment of the flexible circuit structure; -
FIG. 61 is a partial cross-sectional view of an alternate embodiment of the flexible circuit, which comprises a flex circuit membrane structure; -
FIG. 62 is a partial perspective view of a flexible membrane circuit structure, wherein a flexible region is defined as an extension of the electronic test card structure; -
FIG. 63 is a partial perspective view of an alternate flexible circuit structure, wherein a flexible circuit is attached to an electronic test card structure; -
FIG. 64 is a partial cross-sectional view of one embodiment of a preferred flex circuit region of a test electronics module, in which the flex circuit is wrapped around the power and ground buss structure, and which preferably includes a thermal path across the flex circuit between a power module and a buss bar; -
FIG. 65 is a partial cross-sectional view of an alternate embodiment of the flex circuit region of a test electronics module, in which a plurality of power modules mounted on the inner surface of a flex circuit are positioned in thermal contact with a plurality of buss bars; -
FIG. 66 is a partial cross-sectional view of a second alternate embodiment of the flex circuit region of a test electronics module, in which a power module is electrically connected to the outer surface of a flex circuit, and is positioned in thermal contact with a buss bar; -
FIG. 67 is a perspective view of an alternate embodiment of a test electronics module, in which an integrated module base provides a pad matrix on a first planar region, and in which a power module is electrically connected to the pad matrix and to one or more buss bars, and is positioned in thermal contact with a buss bar; -
FIG. 68 is a partial cutaway assembly view of an alternate massively parallel test assembly having an intermediate system board, in which flexible spring probes are located on the lower surface of the system board; -
FIG. 69 is a partial cutaway assembly view of another alternate massively parallel test assembly having an intermediate system board, in which an interposer structure provides electrical connections between the substrate and the system board; -
FIG. 70 is a partial cutaway assembly view of a basic massively parallel test assembly, in which a substrate having spring probes is directly connected to the test electronics modules; -
FIG. 71 is a partial expanded cross-sectional view of a basic massively parallel test assembly, which shows staged pitch and distribution across a substrate and a flex circuit having a pad matrix; -
FIG. 72 is a partial cutaway assembly view of a massively parallel burn-in test assembly, in which burn-in test modules are connected directly to the system board, and in which separate temperature control systems are provided for the wafer-mounted integrated circuit devices under test and for the test electronics modules; -
FIG. 73 is a first partial expanded cross-sectional view showing massively parallel test assembly and alignment hardware and procedures; -
FIG. 74 is a second partial expanded cross-sectional view showing massively parallel test assembly and alignment hardware and procedures; -
FIG. 75 is a partial schematic block diagram of test circuitry for the massively parallel test system; -
FIG. 76 is a partial cutaway assembly view of a massively parallel interface assembly, in which a plurality of interface modules are connected, through a plurality of probe spring interposers and a system interconnect board structure; -
FIG. 77 is a partial cutaway assembly view of an alternate massively parallel interface assembly, in which a plurality of interface modules are connected through a system board and a system interconnect board structure; -
FIG. 78 is a schematic block diagram of connections between a plurality of computer systems, using a massively parallel interface assembly; and -
FIG. 79 is a schematic block diagram of connections between a plurality of electronic circuits, using a massively parallel interface assembly. -
FIG. 1 is aplan view 10 of alinear array 12 of photolithographicallypatterned springs 14 a-14 n, prior to release from asubstrate 16. The conductive springs 14 a 14 n are typically formed on thesubstrate layer 16, by successive layers of deposited metal 17, e.g. such aslayers FIG. 13 , typically through low and high energy plasma and sputter deposition processes, followed by photolithographic patterning, as is widely known in the semiconductor industry. The successive layers 17 have different inherent levels of stress. Therelease regions 18 of thesubstrate 16 are then processed by undercut etching, whereby portions of thespring contacts 14 a-14 n, which are located over therelease regions 18, are released from thesubstrate 16 and extend, i.e. bend, away from thesubstrate 16, as a result of the inherent stresses between the deposited metallic layers. Fixed regions 15 (FIG. 3 ,FIG. 4 ) of the deposited metal traces remain affixed to thesubstrate 16, and are typically used for routing (i.e. such as for redistribution or fan out) from thespring contacts 14 a-14 n.FIG. 2 is aperspective view 22 of alinear array 12 of photolithographicallypatterned springs 14 a-14 n, after release from asubstrate 16. Thespring contacts 14 a-14 n may be formed in high density arrays, with afine pitch 20, currently on the order of 0.001 inch. -
FIG. 3 is aside view 26 a of a first photolithographically patternedspring 14 having ashort length 28 a, which is formed to define a firsteffective spring angle 30 a (which can be from a few degrees to a full circle),spring radius 31 a, andspring height 32 a, after the patternedspring 14 is released from the release region 18 a of thesubstrate 16, away from theplanar anchor region 15.FIG. 4 is aside view 26 b of a second photolithographically patternedspring 14, having along spring length 28 b, which is formed to define a second largeeffective spring angle 30 b,spring radius 31 b andspring height 32 b, after the patternedspring 14 is released from the release region 18 b of thesubstrate 16. The effective geometry of the formedspring tips 14 is highly customizable, based upon the intended application. As well, the spring tips are typically flexible, which allows them to be used for many applications. - Patterned spring probes 14 are capable of very small spring to spring
pitch 20, which allows multiple spring probes 14 to be used to contact power or ground pads on an integrated circuit device 44 (FIG. 58 ,FIG. 59 ), thereby improving current carrying capability. As well, for a massively parallel interconnect assembly 278 (e.g. 278 a,FIG. 55 ) having an array 12 (FIG. 1 ) of spring probes 14, multiple spring probes 14 may be used to probe I/O pads 47 on an IC substrate 48 (FIG. 9 ), such as on an integrated circuit device under test (DUT) 44 (FIG. 58 ,FIG. 59 ). Everyspring probe contact 14 to be verified for continuity after engagement of thespring contacts 14 to theintegrated circuit devices 44 under test (FIG. 55 ), thereby ensuring complete electrical contact between a massivelyparallel interface assembly 78 and adevices 44 on a compliant carrier 115 (FIG. 55 ), before testing procedures begin. - Improved Structures for Miniature Springs.
FIG. 5 is a first perspective view of opposing photolithographic springs 34 a, 34 b, having an interleaved spring tip pattern, before spring to substrate detachment.FIG. 6 is a perspective view of opposing interleaved photolithographic springs 34 a, 34 b, after spring to substrate detachment. - The interleaved photolithographic springs 34 a, 34 b each have a plurality of spring contact points 24. When spring contacts are used for connection to power or ground traces 46 or
pads 47 of anintegrated circuit device 44, the greatest electrical resistance occurs at the point of contact. Therefore, an interleaved spring contact 34, having a plurality of contact points 24, inherently lowers the resistance between the spring contact 34 and atrace 46 orpad 47. As described above, multiple interleaved spring probes 34 may be used for many applications, such as for high quality electrical connections for anintegrated circuit device 44, or for a massively parallel interface assembly 78 (FIG. 15 ), such as for probing anintegrated circuit device 44 during testing. -
FIG. 7 is atop view 42 of opposing interleaved photolithographic spring pairs 34 a, 34 b in contact with thesame traces 46 orpads 47 on an integrated circuit device under test (DUT) 44. The interleavedspring contact pair springs same trace 46 orpad 47. As shown inFIG. 5 , when a zig-zag gap 38 is formed between the twosprings substrate 16,multiple tips 24 are established on eachspring substrate 16, the interleavedpoints 24 are located within an overlappinginterleave region 36. When the interleaved spring probes 34 a, 34 b are released from thesubstrate 16, the interleaved spring points 24 remain in close proximity to each other, within acontact region 40, which is defined between thesprings spring contact pair same trace 46, such as for a device undertest 44, providing increased reliability. As well, since each interleavedspring trace 46 is increased, while the potential for either overheating or current arcing across the multiple contact points 24 is minimized. -
FIG. 8 is a top view of parallel and opposing single-point photolithographic springs 14, before thesprings 14 are released from asubstrate 16. As described above for interleavedsprings parallel springs 14 may also be placed such that thespring tips 24 of multiple springs contact asingle trace 46 on adevice 44. As well, opposing spring probes 14 may overlap each other on asubstrate 16, such that upon release from thesubstrate 16 across arelease region 18, thespring tips 24 are located in close proximity to each other.FIG. 9 is a top view of parallel and opposing parallel single-point photolithographic springs 14, after thesprings 14 are released from thesubstrate 16, wherein the parallel and opposing parallel single-point photolithographic springs 14 contact asingle pad 47 on anintegrated circuit device 44. -
FIG. 10 is a front view of a shoulder-point photolithographic spring 50, having apoint 52 extending from ashoulder 54.FIG. 11 is a partial cross-sectional side view of a shoulder-point photolithographic spring 50, in contact with atrace 46 on an integrated circuit device.FIG. 12 is a perspective view of a multiple shoulder-point photolithographic spring 50. Single point spring probes 14 typically provide good physical contact withconductive traces 46 on anintegrated circuit device 22, often by penetrating existing oxide layers ontraces 46 orpads 47 by a single,sharp probe tip 24. However, forsemiconductor wafers 104 or integrated circuit devices having thin or relativelysoft traces 46 orpads 47, a singlelong probe tip 24 may penetrate beyond the depth of thetrace 46, such as into theIC substrate 48, or into other circuitry. - Shoulder-point photolithographic springs 50 therefore include one or more extending
points 52, as well as ashoulder 54, wherein thepoints 52 provide desired penetration to provide good electrical contact to traces 46, while theshoulder 54 prevents thespring 50 from penetrating too deep into adevice 44 orwafer 104. Since the geometry of the spring probes 50 are highly controllable by photolithographic screening and etching processes, the detailed geometry of the shoulder-point photolithographic spring 50 is readily achieved. -
FIG. 13 shows a partialcross-sectional view 56 of an ultra high frequencyspring probe substrate 16. For embodiments wherein aspring probe 61 and relatedelectrical conductors substrate 16 are required to be impedance matched, one or more conductive reference surfaces 58 a, 58 b, 58 c, 58 d and vias 65 a, 65 b, 65 c may preferably be added, either within or on thesubstrate 16. Thesubstrate 16 may also contain alternating ground reference traces 62 a, 62 b, which are connected to referenceplanes transmission line environment 63. As well, theimpedance control surfaces FIG. 13 . - An insulating
layer 66 may be deposited on a portion theprobe spring 61, such as on the fixed region of theprobe spring 61, up to but not enclosing the tip 24 (FIG. 2 ), as well as on thetrace 60, which connects thespring probe 61 to the via 68. Aconductive layer 58 d may be deposited on top of the insulatinglayer 66, to provide a coaxial, controlled low impedance connection. Alternate layers ofconductive materials 58 anddielectric materials 66 can preferably be integrated within thesubstrate 16, such as for embodiments which require decoupling capacitors in close proximity to aprobe spring 61. For asubstrate 16 which is a conductive material, such as silicon, athin oxide layer 57 may preferably be deposited between thesubstrate 16 and aconductive reference plane 58 c, thereby forming ahigh capacitance structure 59 between thespring probe 61 and the ground planes 58 a and 58 b. As well, one or more assembledcomponents 69, such as passive components 69 (e.g. typically capacitors, resistors, and/or inductors), oractive component devices 69, may be incorporated on eithersurface 62 a, 62 of the substrate. - The fixed
portions 15 of the spring probes 61 typically extend a relatively short distance across thesubstrate 16.Traces 60 located on the surface of thesubstrate 16 are electrically connected to the fixedportions 15 of the spring probes 61, and electrically connect the probe springs 61 to thevias 68. The traces may be comprised of a different material than the spring probes 61, and are preferably comprised of metals having high electrical conductivity (e.g. such as copper or gold). -
FIG. 14 is apartial plan view 72 of asubstrate 16, in which a plurality of distribution fanout traces 60 are defined on theprobe surface 62 a of thesubstrate 16, between a plurality of spring probes 61 and a plurality of viacontacts 70. As described above, the spring probes 61, which are preferably photolithographically formed springs 61, may currently be formed with a pitch of approximately 0.001 inch. Thetraces 60 are preferably routed on theprobe surface 62 a, to connect to viacontact areas 70, which are preferably laid out in a matrix across the surface of thesubstrate 16. In thesubstrate 16 shown inFIG. 14 , the viacontact areas 70 are positioned with a probe surface first distribution pitch 74 a, and a probe surfacesecond distribution pitch 74 b. - As the size and design of
integrated circuit devices 44 becomes increasingly small and complex, the fine pitch 20 (FIG. 2 ) provided by miniaturespring probe tips 61 becomes increasingly important. Furthermore, with the miniaturization of bothintegrated circuits 44 and the required test assemblies, differences in planarity between one or moreintegrated circuits 44 located on awafer 104 and asubstrate 16 containing a large number of spring probes 61 becomes critical. - As seen in
FIG. 14 ,lower standoffs 75 are preferably provided on theprobe surface 62 a of thesubstrate 16, such as to prevent thesubstrate 16 from damaging a wafer undertest 104, or to set thespring probe tips 24 to operate at an optimal contact angle. Thelower standoffs 75 are preferably made of a relatively soft material, such as polyamide, to avoid damage to the semiconductor wafer undertest 104. In addition, to further avoid damage toactive circuits 44 in thesemiconductor wafer 104, thestandoffs 75 are preferably placed, such that when the massivelyparallel interface assembly 78 is aligned with adevice 44 on asemiconductor wafer 104, thestandoffs 75 are aligned with the saw streets 136 (FIG. 18 ,FIG. 19 ) on thesemiconductor wafer 104, where there are noactive devices 44 or test structures. Furthermore, the height of thelower standoffs 75 are preferably chosen to limit the maximum compression of the spring probes 61 a-61 n, thus preventing damage to the spring probes 61 a-61 n. - The
substrate 16 also typically includes one or more alignment marks 77 (FIG. 14 ), preferably on theprobe surface 62 a, such that theprobe surface 62 a of thesubstrate 16 may be precisely aligned with a wafer to be tested 104. - Chip Scale Semiconductor Package.
FIG. 15 is aplan layout view 78 of a chip scale integrated circuit package dieregion 80 having stress metal springs 84 connected toIC pads 82 and laid out on theupper substrate surface 85 a, before release from theupper substrate surface 85 a. In theplan layout view 78, the stress metal springs 84 each have aspring contact region 86, which before release are preferably laid out in an IC surface first fanout pitch 87 and an IC surfacesecond fanout pitch 88.FIG. 16 is aplan layout view 90 of an integrated circuit dieregion 80 having stress metal springs 84 connected toIC pads 82 and extending from thesubstrate surface 85 a, after release from theupper substrate surface 85 a. During release from theupper substrate surface 85 a, each of the stress metal springs 84 extend fromrespective release regions 18, whereby the contact regions 86 (FIG. 15 ) are rotated though an effective spring angle 30 (FIG. 3 ,FIG. 4 ), such that eachstress metal spring 84 further preferably defines aspring contact surface 92. After release from thesubstrate surface 85 a, each of the spring contact surfaces 92 are preferably laid out on a spring contactfirst fanout pitch 94 and on a spring contactsecond fanout pitch 96. -
FIG. 17 is a partial cutaway view of an chip scale integratedcircuit package 100 having looped stress metal springs 84 connected toIC pads 82 and extending from thesubstrate spring surface 85 a, wherein a portion of the stress metal springs 84 are embedded within asupport substrate 106 comprised of an electrically insulative material. Thesupport substrate 106 is typically comprised of a polymer substrate which provides support for each of thesprings 84. In some preferred embodiments of the chip scale integratedcircuit package 100, thesupport substrate 106 is a compliant polymer, i.e. an elastomer. - The
support substrate 106 provides mechanical protection and adds mechanical support, i.e. strength, to thesprings 84, provides passivation to the integrated circuit dieregions 80, and adds mechanical strength to the assembly. - The combination of
springs 84 andsupport substrate 106 constructed on the integrated circuit device, together form theintegrated circuit package 100, which is attachable to a printedcircuit board 216, typically using epoxy or solder. Thesupport substrate 106 provides mechanical strength for chip attachment to the printed wiring board, and controls the amount of wetting for solder or epoxy on thesprings 84. The compliant springs 84 provide the compliant connection to manage the thermal expansion mismatch between thedie region 80 and a printedwiring board 216. - While the
springs 84 shown inFIG. 17 are preferably stress metal springs 84, thesupport substrate 106 can alternately be used to provide support for a wide variety ofchip scale contacts 84. Thesupport substrate 106 adds strength to thesprings 84, and typically improves the robustness of thesprings 84 to handling and use, that could otherwise result in breakage. - As seen in
FIG. 17 , thesprings 84 provide a conductive path between theintegrated circuit 102 and the loopspring contact regions 92, which extend beyond the outer surface of thesupport substrate 106. As seen inFIG. 15 ,FIG. 16 , -
FIG. 32 ,FIG. 33 , andFIG. 34 , the loopspring contact regions 92 may preferably have an enhanced contact area geometry, such as to provide dimensional tolerance for electrical connections for testing, burn-in, or for subsequent device operation. - As seen in
FIG. 17 ,FIG. 24 ,FIG. 43 , andFIG. 51 , stress metal springs 84, 152 may preferably also comprise one or more metal ormetal alloy coatings 166. These coatings may be applied using eletro or electroless plating, sputtering, evaporation, or equivalent processes. - Specific metals or alloys for spring coatings are selected to provide a high integrity physical mounting between the
IC package 100 and its mounting substrate (e.g., printed wiring board 216), a low resistance electrical path betweenIC contact pads 82 andspring contact region 92, as well as a surface compatible with either a solder or pressure connection to solder ball 220 (FIG. 54 ) or spring contact region 92 (FIG. 17 ), respectively. - Desirable metals for stress metal spring body and tip coatings include nickel or nickel alloys such as, nickel iron, nickel cobalt, nickel cobalt iron, nickel molly, nickel tungsten, nickel iron tungsten, nickel cobalt tungsten, nickel rhodium, nickel cobalt manganese, nickel iron rhodium, nickel iron manganese, and silver, rhodium, palladium or palladium alloys such as palladium cobalt, cobalt, silver, gold or gold alloys, tin and tin alloys, copper and copper alloys, and lead containing and lead free solder materials.
- Metal coatings can be applied to exemplary
stress metal springs 14 a-14 n inFIG. 2 either before or after release fromsubstrate 16 or to those ofsprings die region 80. Metallic coatings, such asexemplary coating 166 inFIG. 24 , can also be used to increase the strength ofexemplary springs 84 ofFIG. 17 or 152 ofFIGS. 22-27 to improve the robustness of the springs to handling and use.Metallic coating 166 can also be used to reduce the overall electrical resistance ofexemplary springs - In some embodiments, harder metals such as rhodium, palladium or a palladium alloy such as palladium cobalt, or other alloys may be used to provide improved contact performance by increasing resistance to mechanical wear and debris pickup from printed circuit board pads. These metals may be plated as primary, secondary, or subsequent plating metal layers to serve as stress metal spring contact regions, such as in
region 92 inFIG. 17 , or other exemplary contact regions including 92 and 158 ofFIG. 22,158 and 162 ofFIG. 23, 92 and 158 ofFIG. 24-27 . - Exemplary contact bumps 159 in
FIGS. 25-27 can be filled or plated on thestress metal tips 158 inFIG. 26 either before or after lifting the springs from the substrate. The bumps can be fabricated using selected metals and alloys such as nickel or nickel alloys, rhodium, palladium, or palladium alloys, copper or copper alloys, gold or gold alloys, and solders such as mentioned above. - Additional plating layers or buttons can be applied before or after lifting the springs from the substrate and can be selectively applied to the
spring tips 92 inFIG. 27 using photolithographic methods. As well, the use of a platedmetallic coating 166 creates a higher contact force betweenspring 84 and the pad on a circuit board, to reduce the electrical contact resistance. - In some preferred embodiments of the stress metal springs 84,152, a
metal plating layer 166, such as a nickel alloy, is then followed by subsequent plating layers 166, such as gold or rhodium, to provide increased spring strength and, lowered spring resistance, as well as improved contact performance. - For stress springs 84,152 which preferably comprise a plated
metal coating 166, a large portion of the required strength for thesprings plating 166, such that the stress metal layers 17 a-17 n (FIG. 13 ) are not required to provide as much strength, such as compared to anunplated spring FIG. 13 ) may only be used to define the structural shape before plating, thereby relaxing the process, i.e. metallurgical, parameters needed for the stress metal layers 17 a-17 n. - For embodiments of stress springs 84, 152 in which the plated
metal coating 166 significantly strengthens the spring,support substrate 106 can alternately be comprised of a relativelyhard polymer material 106, such as polyimide or a conventional molding material, such as to create a rigid IC package for direct surface mount applications to printedcircuit boards 216. Chip-scale package integratedcircuit devices 100 for use in harsh environments may also preferably further comprise platedmetal spring coatings 166 combined with a polymer underfill 217 (FIG. 54 ). - As well, a boundary layer 161 (
FIG. 26 ,FIG. 46 ) can preferably be used on the stress metal springs 84, 152, in which theboundary layer 161 is initially established as the first layer, i.e. the layer in contact with therelease region 18. After release from thesubstrate surface 85 a, the stress metal springs 84 loop through aneffective angle 30, such that theboundary layer 161 becomes the outer layer of thecontact region 92, forsprings boundary layer 161 is preferably comprised of a highly conductive and non-corrosive metal, such as gold, rhodium, or palladium. In some embodiments, theboundary layer 161 is preferably be patterned on thesubstrate surface 85 a, such as to be selectively applied to portions of thesprings 84, e.g. such as to control the wetting of solder on acontact area 92 of aspring 84. - As seen in
FIG. 17 , the stress metal springs 84 preferably have aeffective angle 30 which is typically larger than 180 degrees, such that the leading edges 155 of thesprings 84 preferably extend back into thesupport substrate 106, defining a loopspring contact region 92 along the convex arch of thespring 84. While the chipscale package semiconductor 100 shown inFIG. 16 shows a largeeffective spring angle 30, a wide variety of chip scale package contact springs 84 can be enhanced by the use ofsupport substrates 106 and one or more plating layers 166. Some springs 84,152 which require higher force or which need to contact smaller pads on a printedcircuit board 216 preferably have aneffective angle 30 which is typically less than 90 degrees. - Chip Scale Semiconductor Package Fabrication. The chip
scale semiconductor package 100 can be efficiently fabricated using batch processing methods. Arelease layer 18, such as titanium or silicon oxinitride, is typically initially fabricated on the wafer dieregion 80. Next, one or more metal layers 17 with controlled stress, such aslayers FIG. 13 , are deposited on top of therelease layer 18. In some embodiments of the chipscale semiconductor package 100, the stress metal layers 17 are comprised of the same or similar deposited metal, which have an initial stress gradient. - In some embodiments of the chip
scale semiconductor package 100, the stress metal springs are built in compliance to photolithographic springs, such as described above, or as disclosed in U.S. Pat. No. 5,848,685, U.S. Pat. No. 5,613,861, or U.S. Pat. No. 3,842,189, which are incorporated herein by reference. - The stress metal layers 17 are then typically patterned, to form spring and interconnect traces, using conventional photolithography and etch processes. A dielectric release window, such as polyimide, oxide, or nitride is defined, after the stress metal layers 17 are controllably etched. The release window defines the
areas 18 where the spring metal is released from thesubstrate surface 58 a, forming springs 84. After the stress metal springs 84 are controllably released from the substrate dieregion 80, thesprings 84 are preferably plated 166, to adjust the spring constant, or to increase the strength of the stress metal springs 84. As described above, the exposedcontact portions 92 of the stress metal springs 84 are preferably coated with gold or other material, such as for ease of soldering during a subsequent IC circuit assembly process. As well, abarrier metal 161 can also be formed on thestress metal spring 84, before stress metal deposition. - The
support substrate layer 106 is then typically applied on thewafer 104, after thesprings 84 are released and are preferably plated. Thesupport substrate 106, typically comprising a polymer, functions as a protective layer for the integrated circuit device. In some embodiments of the chipscale semiconductor package 100, thesupport substrate 106 is controllably applied to a desired depth, such that thecontact portions 92 of the stress metal springs 84 are exposed. In other embodiments of the chipscale semiconductor package 100, wherein thesupport substrate 106 is initially applied to cover theentire spring structures 84, thesupport substrate 106 is subsequently etched back, to expose thetop contact region 92 of thesprings 84. A photomask is preferably used for anetched support substrate 106, to controllably define the precise location and shape of the exposed region of thecontact portions 92 of the stress metal springs 84. - Advantages of Chip Scale Semiconductor Package. The chip scale integrated
circuit package 100 simplifies the process and reduces the number of processing steps in the fabrication of chip scale packages. A chip scale integratedcircuit package 100 can be easily fabricated through batch processing techniques, similar to batch process manufacturing methods for semiconductor assemblies, such as integrated circuit devices. - The chip scale integrated
circuit package 100 thus eliminates the serial process of bonding device leads to an integrated circuit one at a time. As well, the chip scale integratedcircuit package 100 enables tight pitch packages with high electrical performance. - Furthermore, chip scale integrated
circuit packages 100 can also provide a direct temporary contact to a board, such as to a printedcircuit board 216, by pressure, which can eliminate the need for a socket or interposer connection. This temporary contact can also function as a probe contact, thus allowing the probe contact to be reduced to a simple pad array on a printedcircuit board 216. - Compliant Wafer Chip Carrier.
FIG. 18 is aside view 110 of integrated circuit dieregions 80 on asemiconductor wafer 104. Each of the integrated circuit dieregions 80 havecontacts 47, such as contact pads or stress metal springs 84. Sawstreets 114 are defined between the integrated circuit dieregions 80. In a preferred embodiment, the integrated circuit dieregions 80 are chipscale semiconductor packages 100, having stressmetal spring contacts 84 and asupport substrate 106, as described above. -
FIG. 19 is aside view 112 of asemiconductor wafer 104, having integrated circuit dieregions 80, in which thewafer 104 is adhesively mounted to a compliantwafer carrier substrate 115. Thecompliant substrate 115 has afirst surface 116 a and a second surface opposite the first surface 116 b. Thefirst surface 116 a includes an adhesive layer, such that awafer 104 may readily be mounted for subsequent IC separation and processing. Asupport 118 is also typically attached to thecompliant substrate 115. -
FIG. 20 is aside view 120 which shows of theseparation 122 of integrated circuits on asemiconductor wafer 104, which is mounted to acompliant carrier substrate 115. As known in the semiconductor processing industry, a saw is typically used to formseparations 122 betweenintegrated circuits 44 and dieregions 80, along thesaw streets 114. - The
compliant wafer carrier 115 is typically comprised of a compliant polymer material, such as RISTON™, Part Number 1004R-9.0, from Nitto-Danko, Japan, or Ultron Systems, of Moore Park, Calif. As described below, some preferred embodiments of thecompliant wafer carrier 115 are thermally conductive and/or electrically conductive. -
FIG. 21 is aside view 130 which shows separatedintegrated circuits compliant wafer carrier 115. Thecompliant wafer carrier 115 holds the integratedcircuit dice wafer separation 122, e.g. such as after saw and break, making it possible to handle all the separateddice wafer 104 as a group, through back end assembly, test and burn in. - The use of a
compliant wafer carrier 115 integrates assembly and wafer level testing and burn-in processes, and offers the speed advantage of parallel testing and simplicity in handling. - In conventional wafer level testing and burn in, the
integrated circuit dice 44 are sometimes burned-in and tested before packaging and singulation from the wafer. However, a common difficulty encountered in a conventional wafer-level pre-singulation approach is the complexity in managing the thermal expansion mismatch between the silicon wafer and the connector systems, which are required to make connections between the integrated circuit dies on the wafer and the system electronics. As well, defects induced by the packaging, singulation, and handling are not screened out by such a process. - The preferred use of a stress metal spring
chip scale package 100, in conjunction with acompliant carrier 115, as described above, allows the use of low cost printedwiring board material 282, whose material coefficient of expansion can be different from the carrier mounted devices undertest 100, to contact the dice during test and burn-in. As well, as described below, various embodiments of a massively parallel interface assembly 278, e.g. such as massivelyparallel interface assembly 278 a shown inFIG. 55 , allow connection to a wide variety of carrier-mountedintegrated circuits - Therefore, the preferred use of
chip scale package 100 and/or a massively parallel interface assembly 278 allow the test and burn ofintegrated circuit dice singulation 122, making it possible to detect assembly, saw and handling caused defects, while keeping the die in position for precision handling with massive parallelism. - In embodiments using a preferred
chip scale package 100, thesemiconductor wafer 104, having stress metal springs 84 which are processed onto theactive surface 85 a and are preferably partially encapsulated 106, is attached to a compliantdecal wafer carrier 115. In some embodiments of thecompliant carrier 115, thecarrier 115 is similar to a conventional “blue” tape carrier which is commonly used for wafer sawing in the semiconductor processing industry. - The mounted
wafer 104 is then sawed 122 intoseparate die carrier 115. Thecarrier tape 115 holds the packageddice 100 in their relative position, as they were on thewafer 104. Acontact fixture 132, such as the massively parallel test assembly 278 (FIG. 55 ,FIG. 57 ,FIG. 68 ,FIG. 70 ,FIG. 71 ), typically including a printedwiring board 282, comprises connections and associated electronics for connecting to and for testing theintegrated circuits contact fixture 132 connections are designed to match theconnections 47, such as spring leads 84, on the devices undertest contact fixture 132 is pressed onto theDUT devices compliant carrier 115. - As seen in
FIG. 21 , apressure plate support 134, preferably constructed of a material having a similar thermal coefficient of expansion (TCE) to the TCE of the printedwiring board 282, supports the back surface 116 b of thecompliant carrier 115. During testing and/or burn-in operations, theIC contact fixture 132 is fixedly attached 136 in relation to thepressure plate support 134, forming asandwich structure 130, in which the mounted integrated circuit die 44,100 and thecompliant carrier 115 are held in place. Thepressure plate support 134 may also be preferably comprised of a compliant material, whereby thepressure plate support 134 and the carrier-mounteddie system board 282. - When the temperature of this
sandwich structure 130 is raised to the test and burn-in temperature, the printedwiring board 282, having a higher coefficient of expansion than the silicon dieregions 80, expands faster than the silicon dieregions 80. However, friction between the integrated circuit die 44,100 and the printedwiring board 282 and thepressure plate support 134 acts to drag the integrated circuit die 44,100, along with the printedwiring board 282, since the integrated circuit die 44,100 are separated 122 from each other, and are only connected through the compliantflexible carrier 115. Therefore, the relatively independent movement of each of the separated integrated circuit die 44,100 maintains pad to lead alignment between theintegrated circuits wiring board 282. - The separated integrated circuit die 44,100 which are mounted to the
compliant carrier 115, are able to move relative to each other, while holding their positions on thecompliant carrier 115. Therefore, the separated integrated circuit die 44,100 can be handled and processed as a “wafer” assembly, while maintaining sufficient connections to theIC contact fixture 132. - Therefore, the printed
wiring board 282 and thepressure plate support 134 are not required to be comprised of a material having a similar coefficient of expansion TCE to theIC substrate 104. The compliant carrier-mounteddice system board 282 and thesupport structure 134, such that thedice system board 282 within theIC contact fixture 132. Furthermore, since thedice dice - As seen in
FIG. 21 , atemperature controller 144 is preferably attached to thesandwich structure 130, such as to provide heating or cooling during testing and/or burn-in processes. In some embodiments of thecompliant wafer carrier 115, thecarrier 115 is comprised of a thermally conductive material, which functions as a thermal control plane during testing or burn-in, wherein the back side of the integrated circuits are in thermal contact totemperature control 144, such as for cooling and/or heating, through thecompliant tape layer 115. - As well, the
carrier 115 may preferably be comprised of electrically conductive material, whereby thecarrier 115 may provide anelectrical connection 140 to the back surface of the separated and mountedintegrated circuit dice 80. - Stress Metal Spring Interposer.
FIG. 22 is a partialcross-sectional view 150 of a stressmetal spring interposer 151 a, comprising one ormore springs 152 which extend from afirst surface 156 a to a second surface of aninterposer substrate 154. Thesprings 152 also typically comprisecontact pads 158 which extend from the first surface of theinterposer substrate 154. Stress metal spring interposers 151 provide ultra-high density, compliant through connections, and provide high density connections over extreme temperature ranges. - Conventional interposers, such as pogo pins, springs, or wires which are fabricated by mechanical construction methods are limited in pitch, which limits the connection density and requires high connection force.
- Stress metal spring interposers 151 use thin film stress metal to form a tight array of thin film springs, held together by a
substrate 154 comprises of a polymer material. Electrical connections are made from oneside 156 a of the polymer sheet to theother side 156 b by the conductive springs 152. - A high density connection between the two
surfaces spring 152, such as for different contact materials. - In some embodiments of the stress metal spring interposers 151, the stress metal springs are built in accordance to U.S. Pat. No. 3,842,189 and/or U.S. Pat. No. 3,842,189, which are incorporated herein by reference.
- A wide variety of geometries and materials may be used for the construction of the
spring interposer 152. For example,FIG. 23 is a side cross-sectional view 160 of a stressmetal spring interposer 151 b having formedbumps 162 on the secondsurface contact region 158.FIG. 24 is a sidecross-sectional view 64 of a plated stressmetal spring interposer 151 c. Thesprings 152, as well as stress springs 84, are preferably comprised of layers of metal having 17 (FIG. 13 ) having different initial levels of stress, such that the springs form an effective spring angle 30 (FIG. 3 ) during fabrication. -
FIG. 25 is a side cross-sectional view of a stressmetal spring interposer 151 d having filledbumps 159 on a first surface contact region, and looped stress metal springs 152 which partially extend beyond apolymer interposer layer 154, defining ahollow contact region 157 between thecontact area 92 of the looped stress metal springs and thetop surface 156 b of thepolymer layer 154. -
FIG. 26 is a side cross-sectional view of a stressmetal spring interposer 151 e, in which the interposer layer comprises a plurality ofpolymer layers boundary layer 161. In some embodiments of the stress metal springs 84,152, theboundary layer 161 comprises a metal having high electrical conductivity and/or corrosion resistance. Theboundary layer 161 may also be used for increased stress spring strength. -
FIG. 27 is a side cross-sectional view of a stressmetal spring interposer 151 f, in which the stress metal springs 152 have an effective spring angle less than 90 degrees, and in which theinterposer substrate 154 adds strength and/or protection for the stress metal springs 152. - Leading Edge and Contact Geometries for Loop Stress Metal Springs. Loop
stress metal prings 152, such as used for the stress metalchip scale package 100, the stress metal interposer 151, or for thestress metal contactor 196, such ascontactor 196 a inFIG. 41 , can have a wide variety of leading edge and contact area geometries. - Looped Stress Metal Spring Leading End Detail.
FIG. 28 is a partial view of a squareleading end 155 a of a loopedstress metal spring FIG. 29 is a partial view of a pointedleading end 155 b of a loopedstress metal spring FIG. 30 is a partial view of a pointedleading end 155 c of a loopedstress metal spring grooves 157.FIG. 31 is a partial view of a pointedleading end 155 d of a loopedstress metal spring ledges 163. - The leading end 155 of high effective angle looped stress metal springs 84,152 can have a variety of leading end geometries 155, since the leading ends 155 are typically not used for contacting. The desired geometry of the leading end 155 is typically chosen to control the formation of the non-planar springs 152, during lift-off from a substrate, i.e. the spring tip geometry helps the
stress metal spring 152 to lift in the correct direction. In some embodiments, the geometry of the leading end 155 is chosen to anchor the loop spring probe within a supportingsubstrate 154, such as withgrooves 157 orledges 163. - Contact Area Structures.
FIG. 32 is a plan view of a contact area of a loopedstress metal spring 152, in which thecontact area 92 which extends beyond theouter surface 156 b of thepolymer layer rectangular contact region 92 a.FIG. 33 is a plan view of acontact area 92 b of a loopedstress metal spring 152, in which thecontact area 92 b which extends beyond theouter surface 156 b of thepolymer layer octagonal contact region 92 b.FIG. 34 is a plan view of a contact area 96 c of a looped stress metal spring, in which thecontact area 92 c comprises an expanded diamond-shapedcontact region 92 c. As the stress metal springs 84,152 are typically comprised of photolithographically formed layers 17, e.g. such as 17 a, 17 b inFIG. 13 , the definedcontact area 92 can have a variety of geometries, such as to provide dimensional tolerance for the interconnection structure. - Stress Metal Spring Interposer Construction Process.
FIG. 35 is view of afirst step 170 of a stress metal spring interposer construction process, in which asacrificial substrate 172 is provided. For embodiments of the stress metal spring interposer 151 in which thesprings 152 includecontact pads sacrificial substrate 172 includes apad formation structure 174. Thesacrificial substrate 172 can be fabricated from a wide variety of etchable materials, such aluminum or silicon. As described below, thesacrificial substrate 172 is used as a temporary substrate in the fabrication of a spring interposer 151, and is eventually removed, typically by an etching process. -
FIG. 36 is a view of asecond step 176 of a stress metal spring interposer construction process, in which one or more stress metal spring layers 178, such as stress metal layers 17, are established on thesacrificial substrate 172, and in whichspring release regions 18 are controllably defined. For some embodiments of the stress metal spring interposer 151 in which thesprings 152 includecontact pads 158, the successive layers 17 of thespring 152 are formed directly intopad formation structures 174. In alternate embodiments of the stress metal spring interposer 151 in which thesprings 152 includecontact pads 158, discrete contact pads 159 (FIG. 26 ,FIG. 27 ) are formed withinpad formation structures 174, such as by a fill and polish process, in which the successive layers 17 of thespring 152 are formed over thediscrete contact pads 158. -
FIG. 37 is a view of athird step 180 of a stress metal spring interposer construction process, in which non-planar portions of the stress metal springs 152 extending from thesacrificial substrate 172 are controllably formed, upon release from therelease regions 18. The inherent stress of the metal layers 17 forms a spring having aneffective spring angle 30. In the embodiment shown inFIG. 37 , the effective spring angle is greater than 180 degrees, e.g. such as 270 degrees, such that thespring 152 has a convex contact surface 92 (FIG. 39 ). - Various spring shapes and lift can be used, including
springs 152 withsharp contact tips 24, which point towards the contact pad surface atvarious angles 30. Thesprings 152 provide ultra high-density connectivity between the two different surfaces, while maintaining compliance. Different contact shapes can be fabricated on the contact surfaces, by first defining the desired contact shapes on thesubstrate material 172. - The stress metal springs 152 shown in
FIG. 37 also preferably comprise a plating layer 166 (FIG. 24 ), which is typically applied to the formednon-planar springs 152, before the formation of thesupport substrate 154, such as anelastomer 154, such that theplating 166 is applied to the non-planar portions of the stress metal springs 152. Plating 166 can be used for spring strengthening, enhanced conductivity, and/or for corrosion protection. -
FIG. 38 is a view of afourth step 182 of a stress metal spring interposer construction process, in which aninterposer substrate 184 is applied on thesacrificial substrate 172 and typically over the stress metal springs 152. -
FIG. 39 is a view of a fifth step 186 of a stress metal spring interposer construction process, in which an outer portion of the appliedinterposer substrate 184 is removed 188 to form a contouredinterposer substrate 154, such as by etching, to accessupper contact portions 92 of the stress metal springs 152. -
FIG. 40 is a view of asixth step 190 of a stress metal spring interposer construction process, in which thesacrificial substrate 172 is removed 192, such as by etching from theinterposer substrate 154, exposing thelower contact portions 158 of the stress metal springs 152. - The spring interposer 151 can be configured for a wide variety of applications, and can be used to provide a high density interface, e.g. such as 50-100 microns. The spring interposer 151 can be fabricated to have a variety of
contact area geometries 92 as well, such as a square, rectangle, or circular configurations, based on the desired application. - As well, some embodiments of the spring interposer 151 have an
effective spring angle 30 less than 180 degrees, whereby the springs include acontact tip 24 to establish electrical connections. As well, some embodiments of the spring interposer 151 preferably have a planarlower contact region 158. As described above, aboundary layer 161, such as a metal having enhanced conductivity, corrosion resistance, or solderability characteristics (e.g. such as gold, rhodium, or palladium), may also preferably be established as the lowest layer of stress metal layers, such that theboundary layer 161 provides thecontact surface 92. - In alternate embodiments of the spring interposer 151, the
interposer substrate interposer layers FIG. 26 ). A firstthin layer 154 a, comprising a relatively rigid electrically insulative material, such as polyimide, provides increased dimensional control, handleability, and mountability for the interposer 151, while thesecond interposer layer 154 b, typically comprising a relatively non-rigid electrically insulative elastomer, provides enhanced support and compliance for thesprings 152. In embodiments of the spring interposer 151 having acomposite interposer structure 154, the thinsemi-rigid layer 154 a may also preferably comprise one or more openings. - Stress Metal Spring Contactor.
FIG. 41 is a sidecross-sectional view 194 of a stressmetal spring contactor 196 a havingcontact areas 92 extending from anelastomeric support substrate 154, which are electrically connected tovias 200 that extend through awafer substrate 198.FIG. 42 is a side cross-sectional view of a stressmetal spring contactor 196 b having bumpedcontact areas 162 extending from asupport substrate 154.FIG. 43 is a side cross-sectional view of a plated stressmetal spring contactor 196 c having platedcontact areas 92 extending from asupport substrate 154.FIG. 44 is a side cross-sectional view of a plated stressmetal spring contactor 196 d havingcontact areas 92 extending from thecontactor substrate 198. -
FIG. 45 is a side cross-sectional view of a stressmetal spring contactor 196 e having looped stress metal springs 152 which partially extend beyond a polymer layer, defininghollow regions 157 between thecontact area 92 of the stress metal springs 152 and theupper surface 156 b of thesupport substrate 154.FIG. 46 is a side cross-sectional view of a stressmetal spring contactor 196 f in which the support layer comprises a plurality ofpolymer layers FIG. 47 is a side cross-sectional view of a stressmetal spring contactor 196 g in which the stress metal springs 152 further comprise aboundary layer 161, such as gold, rhodium, or palladium, and have aneffective spring angle 30 less than 90 degrees. - As seen in
FIG. 54 , the stressmetal spring contactor 196 spring structure can be used for probing solder balls 220 on a bumped wafer, such as to provide a temporary contact to solder bumps on flip chip devices. - Traditional vertical probes, such as the Cobra Probe™ from IBM and the Microspring™ from Form Factor are expensive, and have a long lead time. The stress
metal spring contactor 196 can be fabricated using batch processing methods, which decreases the cost of the contactor, and provides a short turnaround time. - Stress Metal Spring Contactor Construction Process.
FIG. 48 is a view of afirst step 202 of a stress metal spring contactor construction process, in which a springprobe contactor substrate 198 havingvias 200 is provided. -
FIG. 49 is a view of asecond step 204 of a stress metal spring contactor construction process, in which in which one or more stress metal springs 178 are established on the springprobe contactor substrate 198, wherein each of thesprings 178 comprise a plurality of layers 17 having different levels of inherent stress.FIG. 50 is a view of athird step 206 of a stress metal spring contactor construction process, in which in whichnon-planar portions 152 of the stress metal layers extending from the contactor substrate are controllably formed. -
FIG. 51 is a view of afourth step 208 of a stress metal spring contactor construction process, in which the formed non-planar portions of the probe springs 152 extending from the contactor substrate are preferably plated 166. Theplating layer 166 is typically applied to the formed springs 152, before the formation of anelastomer support layer plating 166 is applied to the non-planar portions of thestress metal 152. Plating 166 is preferably used for contactor embodiments which require spring strengthening, enhanced conductivity, and/or corrosion protection. -
FIG. 52 is a view of afifth step 210 of a stress metal spring contactor construction process, in which asecondary substrate 184 is established over the formed non-planar portions of the probe springs 152 extending from thecontactor 198.FIG. 53 is a view of asixth step 212 of a stress metal spring contactor construction process, in which an outer portion of the appliedsecondary substrate 184 is removed 214 to established acontoured substrate 154, to accessupper contact portions 92 of the stress metal springs 152. -
FIG. 54 is a sidecross-sectional view 214 of aprobe spring contactor 196 having a springprobe contact area 92 extending from thesupport substrate 154, in which a connection is established between the compliant stress metalspring contactor lead 152 and a printed wiring board (PWB) 216, though a solder ball contact 220 and aboard contact 218. - Massively Parallel Interface Assemblies for Testing and Burn-In of Compliant Wafer Carrier.
FIG. 55 is a partial expanded cross-sectional view of a massivelyparallel test assembly 278 a having anintermediate system board 282 for connection to separatedintegrated circuit devices compliant carrier 115.FIG. 56 is apartial perspective view 310 of a massivelyparallel interface assembly 278 a.FIG. 57 is a partial expandedcross-sectional view 320 of a massivelyparallel test assembly 278 a having anintermediate system board 282, which shows staged pitch and distribution across asystem board 282, and aflex circuit 290 having a pad matrix 288 (FIG. 55 ) ofelectrical connectors 319 a-319 n. As shown inFIG. 55 andFIG. 57 , theinterface assembly 278 a is positioned in relation to acompliant wafer carrier 115, having one or moreintegrated circuits 44, which are separated by IC separation 122 (FIG. 20 ,FIG. 21 ). The test structures shown inFIG. 21 andFIG. 55 allow parallel testing and burn-in for separatedintegrated circuit devices compliant carrier 115. The chip scale packageddevices compliant carrier 115, and make contact to thesystem transformer board 282. These devices can be connected as shown to a standard tester, or through a set of electronics, to minimize the number of connections between the separatedintegrated circuit devices - The massively
parallel interface assembly 278 a provides electrical interconnections to each of theintegrated circuit devices compliant carrier 115, to work effectively in a typical integrated circuit testing environment. Theinterface assembly 278 a is readily used for applications requiring very high pin counts, for tight pitches, or for high frequencies. As well, theinterface assembly 278 a is easily adapted to provide electrical contact for all traces 46 (FIG. 7 ) and input and output pads 47 (FIG. 7 ,FIG. 9 ) for one or more integrated circuit devices undertest 44 on thecompliant carrier 115. - The
conductive pads 284 a-284 n on the lower surface of thesystem board 282 are typically arranged with a pad pitch 324 (FIG. 57 ), such that theconductive pads 284 a 284 n are aligned with theelectrical contacts 47, such as thecontact regions 92 of stress metal springs 84, on the carrier-mountedintegrated circuit devices conductive pads 284 a-284 n on the lower surface of thesystem board 282 are then routed toconductive paths 286 a-286 n, which are typically arranged with asystem board pitch 326. The electrically conductive connections 328 a-328 n, which may be arranged within one ormore connection regions 332, are located on the upper surface of thesystem board 282, and are routed to theconductive paths 286 a-286 n. The electrically conductive connections 328 a-328 n are typically arranged within theconnection region 332, with a system boardpad matrix pitch 320, which is typically aligned with the flex circuitpad matrix pitch 334 for each of thetest electronics modules 292 a-292 k (FIG. 55 ). - The system
board matrix pitch 320 is typically chosen such that the electrically conductive connections 328 a-328 n are aligned with the flex circuitelectrical connectors 319 a-319 n located on theflex circuits 290, which are typically arranged in a plurality of pad matrices 288 (FIG. 56 ), having a flex circuitpad matrix pitch 334. - The
test electronics modules 292 a-292 k are a basic building block for most of the embodiments of the massively parallel interface test assemblies 278 a-278 d. Thetest electronics modules 292 a-292 k are mounted in parallel (e.g. as seen inFIG. 55 ), to form an array ofmodules 292 a-292 k, which each provide electronics support to one or more columns 339 (FIG. 58 ,FIG. 59 ) of integratedcircuit devices compliant carrier 115 or in awafer form 104, or to a portion of acolumn 339 or die 44, along which thetest electronics modules 292 a-292 k are mounted. -
FIG. 56 is apartial perspective view 310 of a massivelyparallel interface assembly 278 a, whereintest electronics modules 292 are mounted on aframe 302. Each of thetest electronics modules 292 shown includes apreferred flex circuit 290, having apad matrix 288 ofelectrical contactors 319, and one or morepower control modules 300. Theflex circuit 290 for each of thetest electronics modules 292 is mounted on one or more buss bars 298 a-298 h, and extends downwardly through theframe 302. The buss bars 298 a-298 h are attached to theframe 302, such as by electrically isolated fasteners 312, thereby providing a substantially rigid structure. Theframe 302 preferably includes test module alignment guides 318, as well as frame to system alignment pins 314 and means 316 for fastening theframe 302 to a wafer chuck 306 (FIG. 55 ) or to a pressure plate support 134 (FIG. 21 ). Theassembly 310 may also preferably include other means for holding thetest electronics modules 292 a-292 k, such as a card cage (not shown) located below theframe 302. - The separated carrier-mounted
integrated circuit devices system board 282, which provides a standard interface to the tester electronics, at a coarser pitch than the contact pitch of theintegrated circuit devices system board 282 can be comprised a wide variety of materials, such as ceramic, high density printed wiring board, silicon, glass, or glass epoxy. Each of thetester electronics modules 292 a-292 n are attached to thesystem board 282, via a membrane orflex circuit 290. -
Contacts 319,328 betweentest electronics modules 292 a-292 k and thesystem board 282 are achieved using solder, pressure contact, or spring probes. For embodiments which usespring probes 319,328, the spring probes may have a variety of tip geometries, such as single point springs 14, interleaved springs 34, or shoulder point springs 50, and are typically fabricated using thin-film or MEMS processing methods, to achieve low manufacturing cost, well controlled uniformity, very fine pad pitches 20, and large pin counts. In some embodiments, theconnections 319,328 are built in compliance to photolithographic springs, such as described above, or as disclosed in either U.S. Pat. No. 5,848,685 or U.S. Pat. No. 5,613,861, which are incorporated herein by reference. - The configuration shown in
FIG. 55 brings power through theswitchable power modules 300, and input/output signal traces 348 (FIG. 62 ,FIG. 63 ) from thepin electronics card 294 to thesystem board 282. This configuration has the advantage of reducing routing congestion in the flex circuit ormembrane 290. - The structure of the
interface assembly 278 a provides very short electrical distances between the carrier-mountedintegrated circuit devices system board 282, which allows theinterface assembly 278 a to be used for high frequency applications. -
FIG. 58 is an expanded layer plan view of a integrated circuit dies 44 on awafer 104, acircular substrate 16, and arectangular system board 282, wherein theintermediate substrate 16 is typically used in test system embodiments wherein an interface assembly 278 is required to be connected to anentire wafer 104, i.e. for integrated circuits which are not separated and mounted to acompliant carrier 115. Forsubstrates 16 which are preferably comprised of silicon (which may be preferably chosen to match the thermal coefficient of expansion (TCE) of a integrated circuit dies 44 under test), thesilicon substrate 16 may preferably be fabricated by a similar process to that of awafer 104, such that thesubstrate 16 may be fabricated from acircular wafer substrate 16. - As seen in
FIG. 58 ,devices 44, each having a plurality ofpads 47, are formed on awafer 104, and are typically populated across thewafer 104 by a series ofrows 337 andcolumns 339, wherein sawstreets 114 are located between therows 337 andcolumns 339. Forsubstrates 16 which are preferably comprised of ceramic materials, thesilicon substrate 16 may preferably be fabricated from one or more rectangularceramic substrates 16. Thesubstrate 16 may include a travel limit mechanism, such as one or more upper standoffs located on the connector surface of thesubstrate 16, such as to limit perpendicular travel of the substrate in relation to thesystem board 282. -
FIG. 59 is an expanded layer plan view of separated integrated circuit dies 44,100 on acompliant carrier 115, which can be directly connected to asystem board 282. As described above, the carrier-mounted separated integrated circuit dies 44,100 are typically mounted between thesystem board 282 and a pressure plate support 134 (FIG. 21 ). - As can be seen in the
system board 282 inFIG. 58 andFIG. 59 , the electrically conductive connections 328 a-328 n, which are located on the upper surface of thesystem board 282, are typically arranged within one ormore connection regions 332, to connect to flex circuit contactors 319 (FIG. 57 ), which are preferably arranged within a similar number of one or more pad matrices 288 (FIG. 56 ). - In some preferred embodiments of the massively parallel interface assembly 278, each of the test electronics modules 292 (e.g. 292 a) is identical to the other test electronics modules (e.g. 292 b-292 k), thereby having an identical number of test componentry (thereby having an identical test capacity). In some embodiments of the massively parallel interface assembly 278, a similar number of
devices 44 is routed to eachtest electronics modules 292 a-292 k. - In alternate embodiments of the massively parallel interface assembly 278, a different number of
devices 44 may routed to a test electronics module 292 (e.g. 292 a), such as forouter columns 339 of devices undertest 44 on awafer carrier 115. For a plurality of standardizedtest electronics modules 292 a-292 k having an identical number of test componentry, atest electronics module 292 which has a greater capacity than the number ofdevices 44 which are connected may still be used, typically through programming thetest electronics module 292 to bypass testing forunused test circuitry 294, or through system control 430 (FIG. 75 ). -
FIG. 60 is a partial cross-sectional view of one embodiment of theflexible circuit structure 342 a, having apolyamide layer 344 a, and opposingconductive layers 346 a and 346 b.FIG. 61 is a partial cross-sectional view of an alternate embodiment of theflexible circuit 290, which comprises a dielectric flexcircuit membrane structure 342 b, and opposingconductive layers 346 a and 346 b. In some embodiments of theflex circuit 290, the flexcircuit membrane structure 342 is inherently flexible. In alternate embodiments of theflex circuit 290, theflex circuit structure 342 is rigid in regions where one or both conductive layers are substantially located. The controlled removal of theconductive layers 346 a, 346 b produces controlled flexibility for theflex circuit 290, while providing regions of formed conductive paths. -
FIG. 62 is a partial perspective view of a flexible membrane circuit structure, wherein a flexible region 290 a is defined on thetest card structure 294 a.FIG. 63 is a partial perspective view of an alternate flexible circuit structure, wherein aflexible circuit 390 b is attached to a test card structure 294 b by attachments 350 (e.g. such as but not limited to fasteners, heat staking, microwelding, or adhesives). - The
test electronics 294 a, 294 b populated on each of thetest electronics modules 292 a-292 k provide stimulus and response detection for one or more devices undertest 44. Thetest electronics 294 a, 294 b are built on a high density interconnect (HDI)substrate wiring board 294 a, which is connected to theflexible circuit 290. The testelectronic card 294 a, 94 b is populated with control and response electronics (e.g. such astest electronics 440 inFIG. 75 ). Each test electronics module 292 (e.g. 292 a) is connected to the backend electronics and computer interface links 296 (e.g. typically by parallel or serial links). Alternatively, the signal pins in thetester electronics modules 292 a-292 k can be connected serially, on a daisy chain, to simplify the electrical connections, such as to external test hardware. Test vector and setup information is sent to the pin electronics, from a system computer and control electronics (e.g. such asexternal pattern generator 446 inFIG. 75 ), through thelinks 296. - Within each of the
test electronics modules 292 a-292 k, atest electronics card 294 is connected to the flex circuit/membrane 290.Test electronics cards 294 may preferably be fabricated as an integral structure with theflexible circuit 290, such as on an etched thin film substrate, whereby portions of the substrate are etched, to create theflexible membrane circuit 290. In an alternate embodiment of the test electronics module, a separate testelectronics card substrate 294 is connected to a flex circuit, typically by solder, wire bond or connectors. -
FIG. 64 is a partial cross-sectional view of one embodiment of theflex circuit region 290 of a testelectronic module 292, which preferably includes a thermallyconductive pathway 354 across aflex circuit 290 between apower control module 300 and one or more buss bars 298. Each of the buss bars 298 a-298 h, which are typically separately electrically connected to a plurality of external power supplies 434 a-434 h (FIG. 75 ), are typically electrically isolated from each other byinsulators 352. Theinsulators 352 may be a separate layer from the buss bars 298 a-298 h, or may alternately be an electricallyinsulative layer 352 on the buss bars 298 a-298 h. -
FIG. 65 is a partial cross-sectional view of an alternate embodiment of theflex circuit region 290 of a testelectronic module 292, in which one or morepower control modules 300 a-300 h are mounted on the inner surface of theflex circuit 290, and are positioned in thermal contact with a plurality of buss bars 298 a-298 h. -
FIG. 66 is a partial cross-sectional view of a second alternate embodiment of theflex circuit region 290 of a testelectronic module 292, in which apower control module 300 is electrically connected to the outer surface of aflex circuit 300. A powercontrol access region 356 is preferably defined through theflex circuit region 290, whereby thepower control module 300 positioned in intimate thermal contact with a buss bar 298 (e.g. such as buss bar 298 b). - One or more power and ground bus bars 298 a-298 h are used to distribute power to all the devices under
test 44.Power control modules 300, typically comprising decoupling capacitors, switching control circuits and regulators for each device undertest 44, are preferably mounted on theflex circuit 290, as shown inFIG. 64 ,FIG. 65 , orFIG. 66 . - While some preferred embodiments of the
test electronics modules 292 a-292 k includeflex circuit structures 290, the unique interface structure provided by theflex circuit structure 290 may alternately be achieved by other suitable interface designs.FIG. 67 is a perspective view of one alternate embodiment of atest electronics module 292, in which anintegrated module base 357 provides apad matrix 288 ofelectrical contacts 319 on a pad matrixplanar region 358. One or morepower control modules 300 are electrically connected toelectrical contacts 319 located on thepad matrix 288, through power control module (PCM) traces 349, and to one or more buss bars 298 a-298 h. Thepower control modules 300 are also preferably positioned in thermal contact with one or more buss bars 298 a-298 h. Signal traces 348 (FIG. 62 ,FIG. 63 ) are also connected toelectrical contacts 319 located thepad matrix 288. The signal traces 348 extend across a link and componentplanar region 359, and are either connected to testelectronics 294, or extend to link 296. - In the various embodiments of the
test electronics modules 292, one or more bus bars 298 provide the power and heat sink paths for thepower control modules 300. Power for devices undertest 44 is typically provided through separate rail buss bars 298, or may alternately share the same rail buss bars 298 with thepower control modules 300. The power rail buss bars 298 also preferably provide mechanical support for theflex circuit 290 and thesystem board 282 and/or thetest electronics cards 294 a-294 k. In some embodiments of thetest electronics modules 292 a-292 k, the powercontrol module circuits 300 are connected in the serial scan path, to provide individual power and ground control to the devices undertest 44. - Alternate Massively Parallel Test Assemblies.
FIG. 68 is a partial cutaway assembly view of an alternate massivelyparallel test assembly 278 b having anintermediate system board 282, in which flexible spring probes 360 are located on thelower surface 339 a (FIG. 57 ) of thesystem board 282. The structure and features of the massivelyparallel test assembly 278 b are otherwise identical to the massivelyparallel test assembly 278 a shown inFIG. 55 . The system board spring probes 360 can be used to provide planarity compliance between thesystem board 282 and the carrier-mountedintegrated circuit devices -
FIG. 69 is a partial cross-sectional view of analternate interface assembly 278 c, wherein a large grid array (LGA)interposer connector 362 is located between asubstrate 16 and thesystem board 282. TheLGA interposer connector 362 provides a plurality of conductors 164 a-164 n between theelectrical connections 64 a-64 n on thesubstrate 16 and plurality ofconductive pads 284 a-284 n on the lower surface of thesystem board 282. In one embodiment, theLGA interposer connector 362 is an AMPIFLEX™ connector, manufactured by AMP, Inc., of Harrisburg Pa. In another embodiment, theinterposer connector 362 is a GOREMATE™ connector, manufactured by W. L. Gore and Associates, Inc., of Eau Clare, Wis. In another alternate embodiment, apogo pin interposer 362 is used to connect opposingconductive pads 284 a-284 n on thesystem board 282 toelectrical connections 64 a-64 n on thesubstrate 16. -
FIG. 70 is a partial cutaway assembly view of a basic massivelyparallel test assembly 278 d, in which asubstrate 16 hasspring probes 61 a-61 n on alower probe surface 62 a, and vias 68 a-68 n which are connected between the spring probes 61 a-61 n andconductors 64 a-64 n located on anupper surface 62 b of thesubstrate 16, wherein thesubstrate 16 is directly connected to thetest electronics modules 292 a-292 k.FIG. 71 is a partial expanded cross-sectional view 366 of the basic massivelyparallel test assembly 278 d, which shows staged pitch and distribution across asubstrate 16 and atest electronics module 292 having apad matrix 288 ofelectrical contactors 319. -
FIG. 72 is a partial crosssectional view 370 of an alternate massivelyparallel interface assembly 378 e, which shows one embodiment of abasic clamping structure 372. Theinterface assembly 378 e is typically intended for burn-in testing only, wherebytest electronics 294 are packaged in small modules 374. The modules 374 are mounted directly onto thesystem board 282, and are preferably used for burn-in testing, which typically requires significantly less test electronics than thetest electronics modules 292 a-292 k (e.g. such as shown inFIG. 55 ). The clampingstructure 372 shown inFIG. 72 may also be used for the wafer level massively parallel interface assemblies 278. - For the massively
parallel interface assembly 378 e shown inFIG. 71 , theinterposer substrate 16 is preferably fabricated from athin substrate 16, such as a 10 mil thick glass plate, whereby thesubstrate 16 may flex slightly, to conform to the surface of integrated circuit dies 44 on awafer 104, to accommodate for non-planarity or bowing between the wafer and theinterposer substrate 16. - A
seal 380 around the periphery of theinterposer substrate 16 preferably provides an air-tight chamber 382. Air pressure is preferably applied between thesystem board 282 and theinterposer substrate 16. An applied pressure 384 also thermally isolates the integrated circuit dies 44 on awafer 104 from thetest electronics 374,294. While integrated circuit dies 44 are typically required to operate at elevated temperatures during burn-in testing (e.g. such as at 125-160 degrees Celsius), thetest electronics 294 should preferably operate at a lower temperature (e.g. such as below 75 degrees Celsius). - The
wafer chuck 306, such as wafer chuck 306 b inFIG. 72 , preferably includes a waferthermal control system 392, which preferably comprises awafer heating system 394 and/or awafer cooling system 396, such as to provide temperature control to the wafer undertest 104. The waferthermal control system 392 is preferably controlled by a testsystem temperature controller 388, which is typically linked 389 to the system controller 432 (FIG. 75 ). - The
test electronics 374,294 are preferably located in one ormore cooling chambers 376. Acooling system 390 is preferably used to control the operating temperature of thetest electronics 374,294 within the coolingchambers 376, and is also preferably controlled by the testsystem temperature controller 388. - A wafer
loading vacuum circuit 386, having vacuum tracks 408 (FIG. 73 ), is preferably built into thewafer chuck 306, to provide vacuum suction to hold thewafer 104 in position, and to improve planarity between thesubstrate connector 16 and thewafer 104. - Test System Architecture. The test system consists of an alignment set up, which performs wafer alignment, cooling unit, and tester electronics. The alignment subsystem and cooling units can be built with technology known in the art.
- System Alignment.
FIG. 73 is a first partial expanded cross-sectional view showing massivelyparallel test assembly 400 and alignment hardware and procedures forwafers 104. Thetest assembly 400 includes acarrier ring 402, which preferably includes one or more alignment features, such as alignment pins 406, whereby thecarrier ring 402 may be aligned to asystem board 282. Thesystem board 282 preferably has mating alignment features, such as alignment holes 426 (FIG. 74 ). - A
substrate 16 is releaseably mounted to acarrier ring 402, such as by a flexible tape 404 (e.g. such as a ring-shaped KAPTON™ tape), whereby theelectrical connections 64 a-64 n (e.g. such as seen inFIG. 71 ) on theconnector surface 62 b of thesubstrate 16 are aligned to the alignment pins 406, such that theelectrical connections 64 a-64 n on theconnector surface 62 b of thesubstrate 16 may be aligned to theconductive pads 284 a-284 n (FIG. 57 ) on the lower surface of thesystem board 282. - The
wafer chuck 306 preferably includes a waferloading vacuum circuit 386, having one or more wafer loading holes 408 on awafer loading surface 409. The waferloading vacuum circuit 386 is connectable to avacuum source 410, and may be sealed by wafer loadingvacuum circuit valve 412. A wafer to be tested 304 is placed onto thewafer chuck 306, and is held in place by a applied vacuum applied through the wafer loading holes 408. - A
substrate 16, mounted on acarrier ring 402, which is to be mounted to thewafer chuck 306, is controllably positioned over thewafer 104, which is held in place by vacuum applied to thewafer chuck 306. Thesubstrate 16 and the integrated circuit dies 44 are then accurately aligned, such as by a lookup/lookdown camera 414 within a modifiedwafer probe system 416, whereby the probe springs 61 a-61 n on theprobe surface 62 a (FIG. 57 ) of thesubstrate 16 are brought into alignment with thedie pads 47 on the integrated circuit dies 44. Alignment is typically achieved, either by looking at spring tips 24 (FIG. 2 ), or at alignment marks 77 (FIG. 14 ) printed on thesubstrate 16. - The
wafer chuck 306 also preferably includes a carrierring vacuum circuit 418, having one or more carrier ring vacuum holes 420. The carrierring vacuum circuit 418 is also connectable to avacuum source 410, and may be sealed by carrier ringvacuum circuit valve 422. Once thesubstrate 16 and the integrated circuit dies 44 to be tested are accurately aligned, the lookup/lookdown camera 414 is removed, and thecarrier ring 402 is controllably moved onto the wafer chuck 304, whereby thesubstrate 16 is accurately positioned over thewafer 104, such that the probe springs 61 a-61 n on theprobe surface 62 a of thesubstrate 16 contact thedie pads 47 on the integrated circuit dies 44. Thecarrier ring 402 is held in place by a vacuum applied through the carrier ring vacuum holes 420. - The wafer loading
vacuum circuit valve 412 and the carrier ringvacuum circuit valve 422 are then closed, such that the applied vacuum to the waferloading vacuum circuit 406 and the carrierring vacuum circuit 418 is maintained, while the entire test assembly can be handled as a unit, for mounting to thesystem board 282 andtest electronics modules 292 a-292 k. In alternate embodiments of the waferloading vacuum circuit 406 and the carrierring vacuum circuit 418, a single valve is used to apply a sealable vacuum to bothvacuum circuits vacuum circuit valves circuit -
FIG. 74 is a second partial expanded cross-sectional view showing massively parallel test assembly and alignment hardware andprocedures 424, whereby a massively parallel interface test assembly 278 may be assembled into a system which may then be used for wafer testing. As described above, thesystem board 282 preferably includes a means foralignment 426 to the carrier ring and/or to thewafer chuck 306, such as alignment holes 426. Thesystem board 282, which is mounted to thetest electronics modules 292 a-292 k and theframe 302, is then positioned over thecarrier ring 402, such that the alignment pins 406 engage the alignment holes 426. A means forattachment 428 is then typically provided, such as between theframe 302 and thewafer chuck 306 or thecarrier ring 402, thus completing the assembly structure. - While accurate means (e.g. such as optical alignment) is typically used to align the fine pitch probe springs 61 a-61 n to the
fine pitch pads 47 on the integrated circuit dies 44 to be tested, the mechanical alignment provided between thecarrier ring 402 and the system board 282 (e.g. such as between alignment pins 406 and holes 426) is typically sufficient for the distributedelectrical connections 64 a-64 n andpads 284 a-284 n, which preferably have larger features, and preferably havecoarser pitches flex circuit pitch 334 on the pad matrix is relatively large (e.g. on the order of 1 mm), making alignment between thetest electronics modules 292 a-292 k and thesystem card 282 relatively easy using similar conventional mechanical alignment techniques. - Tester Electronics.
FIG. 75 is a partial schematic block diagram oftest circuitry 430 for the massively parallel interface test systems 278. Thetester electronics 430 consists of but not limited to acontrol computer 432, a power subsystem,test electronics modules 292 a-292 k, DC parametric andmeasurement systems - As seen in
FIG. 75 , atest electronics module 292 is typically connected to agroup 464 of one or more integrated circuit dies 44,100 to be tested which are mounted on acompliant carrier 115, e.g. such as but not limited to acolumn 339 of devices undertest - The
test electronics modules 292 a-292 k each providestimulus signals 450 to the devices under test (DUT) 44,100, monitor theresponses 454, and store the device under test pass or failinformation 458 within the tester memory, or transfer the device under test pass or failinformation 458 to thesystem controller 432. - For example, in memory testing, a
test electronics module 292 has all the critical functions of a memory tester. This includes thehardware pattern generator 446 to drive the memory devices undertest test electronics module 292, in parallel. Response detection and fail detection circuits in thetest electronics module 292 records the fail locations for each device undertest - The
test electronics modules 292 are preferably software re-configurable and programmable, making it possible to configure thetest electronics modules 292 for a specific DUT design or test function. A built-in self-test (BIST) engine can also be integrated into thetest electronics modules 292, such as to provide additional test features. - Each
test electronics module 292 also provides analog multiplexing functions, to route the intendedDUT pin 47 to the digital test electronics in thetest electronics module 292, or to one or moreDC measurement subsystems 438, which perform analog measurements of the output signals 454. - Sample Test Sequence. After the carrier-mounted integrated circuit dies 44,100 to be tested are loaded, aligned, and engaged, the
system controller 432 sends a control signal to all thepower control modules 300, to connect all power and ground pins 47 for a device under test (DUT) 44,100 to ground, except for a selectedpin 47 to be tested, which is controllably connected to the DCparametric unit 436. The power supplies 434 a-434 h are disconnected from the power buses 298 a-298 h. The power pin integrity of the selecteddevice parametric unit 436. - The DC
parametric unit 436, which is connected to the power rails 298 a-298 h, via relay or solid state switches 435, is then programmed, to check for power to ground shorts. The same sequence is repeated for every power pin on every device undertest - Similar testing is performed on the DUT input and output pins 47, through the
test electronics card 294, to determine short circuits and open circuits for a selected device undertest test output pins 47 of the device undertest - Upon the completion of setup testing, the integrity of the connections and the status of each
device pin 47 is determined, in regard to open or short circuits. An excessive number of measured open circuits for one or more devices undertest wafer carrier 115 may be due to an originallydefective wafer 104, to system setup, or to one or more defective devices undertest - The
test circuitry 430 preferably provides diagnostic capabilities, to further diagnose faults. Shorts can be isolated from the power busses 298 andpin test electronics 294, by scanning the appropriate bit control pattern into thepower control module 300 and pintest electronics module 292. - The remaining devices to be tested 44,100 can then be powered up, and tested in parallel. Short circuit detection and report circuitry is preferably built into each
power control module 300, such that a particular device undertest device power control module 300, such as to provide additional test coverage. - Power Pin Testing. The
system controller 432 selectively switches on the power connections to one or more devices undertest test parametric unit 436. - I/O Pin Testing. Similarly, the input and output pins 47 on a device under
test system controller 432. - Device Functional Testing. With test results from power pin testing and I/O pin testing, for any devices under
test output pins 47 for the faileddevices test - Functional Testing. The
stimulus unit 448 andpattern generator 446 generate theinput pattern 450 to the device undertest DUT response 454 is captured in theresponse block 456, which compares the device undertest pattern generator 446 orstimulus unit 448. Apattern generator 446 is commonly used in memory testing, whereas a truth table representing thedevice stimulus 450 and expectedresponse 454 can be stored in the pattern memory of thestimulus unit 448 for logic device testing. A fail map or log 458 is maintained for each die 44,100. WhileFIG. 75 portrays one embodiment of the functional schematic of, the pattern generation and stimulus/response system architecture, other pattern generation and stimulus/response system architectures may suitably be used to meet the testing requirements of a device undertest 44, as is commonly practiced in the art. - Alternate Interface Embodiments.
FIG. 76 is a partial cutaway assembly view of a massivelyparallel interface assembly 470 a, in which a plurality of interface modules 472 a-472 j are electrically connected to asystem interconnect board 486 a. Each of the interface modules 472 (e.g. such as 472 a) includes apad matrix 288 ofelectrical conductors 319, which are each electrically connected to aprobe spring interposer 476. - Each of the
probe spring interposers 476 includes lower surface spring probes 480, electrically connected to upper surface spring probes 484 byvias 482. As described above, the lower surface spring probes 480, as well as the upper surface spring probes 484, may have a variety of tip geometries, such as single point springs 14, interleaved springs 34, or shoulder point springs 50, and are fabricated on thesubstrate 16, typically using thin-film or MEMS processing methods, to achieve low manufacturing cost, well controlled uniformity, very fine pad pitches 20, and large pin counts. In some embodiments, the flexible connections lower surface spring probes 480 and/or the upper surface spring probes 484 are built in compliance to photolithographic springs, such as described above, or as disclosed in either U.S. Pat. No. 5,848,685 or U.S. Pat. No. 5,613,861, which are incorporated herein by reference. - The
probe spring interposers 476 are provide electrical connections between each of the interface modules 472 a-472 j and thesystem interconnect board 486 a. Thesystem interconnect board 486 a has upper surfaceelectrical contactors 490, vias 491, uppersurface interconnection structures 492 and lowersurface interconnection structures 492 494, such that one or more pads one each interface modules 472 may typically be connected together. Thesystem interconnect board 486 a may also preferably include board electrical componentry, which may be electrically connected to one or more of the interface modules 472. Each of the interface modules 472 includeslinks 296 which provide electrical connections to thesystem interconnect board 486 a, and may also preferably includeinterface module circuitry 498. -
FIG. 77 is a partial cutaway assembly view of an alternate massivelyparallel interface assembly 470 b, in which a plurality of interface modules 472 a-472 j are electrically connected, through asystem board interposer 500 to asystem interconnect board 486 b, which includesflexible probe spring 64 a-64 n, as described above. Thesystem board interposer 500 may preferably include interconnection structures 502 and/or boardelectrical componentry 504, which may be electrically connected to one or more of the interface modules 472. - The massively
parallel interface assemblies parallel interface assembly 470 a may simply be used to provide a robust massively parallel interface, such as to provide complex parallel connections between similar components. In preferred interface embodiments, the massivelyparallel interface assemblies electronic circuitry 498, or sharedcircuitry 496. -
FIG. 78 is a schematic block diagram 506 of connections between a plurality of computer systems 508 a-508 n, using a massivelyparallel interface assembly 470.FIG. 79 is a schematic block diagram 510 of connections between a plurality of electronic circuits 512 a-512 n, using a massivelyparallel interface assembly 470. - System Advantages. The massively parallel interface assemblies 278 a-278 d provide signal and power interconnections between a test system and a large number of
devices wafer carrier 115, while providing planarity compliance between theintegrated circuits system board 282 and thepad matrices 288 on thetest electronics modules 292 a-292 k. - As well, the massively parallel interface assemblies 278 a-278 d provide short electrical paths for the power and input and output signals, between the
test electronics modules 292 a-292 k and the devices undertest system board 282 and the vertically packagedtest electronics modules 292 a-292 k, which typically includeflex circuits 290. - Furthermore, while the massively parallel interface assemblies 278 a-278 d provide short electrical paths for the power and input and output signals, between the
test electronics modules 292 a-292 k and the devices undertest 44,100 (thereby reducing round trip transit time), the massively parallel interface assemblies 278 a-278 d provide thermal isolation between thetest electronics 294 and the devices undertest test test electronics modules 292 a 292 k provide enhanced heat transfer away from heat sensitive components (e.g. such as through buss bars 298 a-298 h), and while preferably providing enhanced test module temperature control. - As described above, the massively parallel test interface assemblies 278 may be used to detect power to ground shorts in any die quickly, and to isolate power from a die having a detected power to ground short before damage is done to the test electronics. In addition, the massively parallel test interface assemblies 278 and related test system may be used to detect that the contacts to many, hundreds, or even hundreds of thousands of pads are reliably made and whether each of the contacts are within the contact resistance specification, and to assure that the self inductance and self capacitance of each signal line are below values that would adversely affect test signal integrity.
- Furthermore, the massively parallel test interface assemblies 278 and related test system can be used to detect whether the mutual inductance and mutual capacitance between pairs of signal lines and between signal lines and power or ground lines are below values that would adversely affect test signal integrity.
- As well, the massively parallel test interface assemblies 278 provide stimulus and response detection and analysis to many, hundreds, or even thousands, of die under test in parallel, and which preferably provides diagnostic tests to a failed die, in parallel with the continued testing of all other die.
- In addition, the massively parallel test interface assemblies 278 can reliably and repeatedly establish contact to many, hundreds, or even thousands of
pads 47, without the need to periodically stop and inspect and/or clean theprobe interface structure 16. - Furthermore, the massively parallel test interface assemblies 278 inherently organize and manage the interconnections between the devices under
test 44 and thetester electronics 430, while maintaining signal integrity and power and ground stability, and assures that no two or moreadjacent pads 47 are contacted by a single test probe tip. - Although the disclosed massively parallel interface assemblies are described herein in connection with integrated circuit testing, computer networking, and circuit connections, the assemblies and techniques can be implemented with a wide variety devices and circuits, such as interconnections between integrated circuits and substrates within electronic components or devices, burn-in devices and MEMS devices, or any combination thereof, as desired.
- Accordingly, although the invention has been described in detail with reference to a particular preferred embodiment, persons possessing ordinary skill in the art to which this invention pertains will appreciate that various modifications and enhancements may be made without departing from the spirit and scope of the claims that follow.
Claims (12)
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US7247035B2 (en) | 2007-07-24 |
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