US20060119605A1 - Method and apparatus for pattern ram sharing color look up table - Google Patents

Method and apparatus for pattern ram sharing color look up table Download PDF

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US20060119605A1
US20060119605A1 US11/335,597 US33559706A US2006119605A1 US 20060119605 A1 US20060119605 A1 US 20060119605A1 US 33559706 A US33559706 A US 33559706A US 2006119605 A1 US2006119605 A1 US 2006119605A1
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pattern
memory
color
sharing
graphic
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US11/335,597
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Roger Lin
Hill Cho
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Via Technologies Inc
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Via Technologies Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
    • H04N7/0117—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving conversion of the spatial resolution of the incoming video signal
    • H04N7/012—Conversion between an interlaced and a progressive signal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/02—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed
    • G09G5/06—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed using colour palettes, e.g. look-up tables
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • G—PHYSICS
    • G10—MUSICAL INSTRUMENTS; ACOUSTICS
    • G10H—ELECTROPHONIC MUSICAL INSTRUMENTS; INSTRUMENTS IN WHICH THE TONES ARE GENERATED BY ELECTROMECHANICAL MEANS OR ELECTRONIC GENERATORS, OR IN WHICH THE TONES ARE SYNTHESISED FROM A DATA STORE
    • G10H1/00—Details of electrophonic musical instruments
    • G10H1/0033—Recording/reproducing or transmission of music for electrophonic musical instruments
    • G10H1/0041—Recording/reproducing or transmission of music for electrophonic musical instruments in coded form
    • G10H1/0058—Transmission between separate instruments or between individual components of a musical system
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/222—Studio circuitry; Studio devices; Studio equipment
    • H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
    • H04N5/265—Mixing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
    • H04N7/0135—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving interpolation processes
    • H04N7/014—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving interpolation processes involving the use of motion vectors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/10—Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region
    • H04N5/144—Movement detection
    • H04N5/145—Movement estimation

Definitions

  • the present invention relates to the usage of video memory, especially to a method and apparatus for sharing the video memory of a graphic chip.
  • a graphic engine obtains the graphic block from a source/destination/pattern block and the pattern block from the other source/destination/pattern block to have various logic executions, and then writes back to a frame buffer to be displayed in a screen.
  • the source block can be obtained from a CPU, main memory and the frame buffer itself.
  • the pattern block can also be obtained from the CPU, pattern memory and pattern register to write back to the destination block after executing a masking operation. But among the obtained blocks, the pattern memory is the largest block in a graphic chip.
  • FIG. 1A is the flowchart for the graphic engine of a prior art processing a pattern block.
  • Step 110 is to configure a pattern block in a pattern memory.
  • Step 130 is to access the pattern block in the pattern memory if the graphic engine needs to process the pattern block.
  • Step 150 is to store the processed pattern block in a frame buffer.
  • FIG. 1B is the color expansion flowchart of a prior art.
  • Step 120 is to configure a look up table (LUT) in a video memory.
  • Step 140 is to expand colors in accordance with the LUT if the destination block of the frame buffer needs to expand colors.
  • Step 160 is to superpose and output the color-expanded destination block and the other graph and video source.
  • the LUT stored in the video memory of a graphic chip recovers the color index stored in a frame buffer, so called pixel value, into the true color RGB 24-bit pixel value by looking up the table when the displayed colors are 256 or under 256 color-scaled colors (indirect colors).
  • the LUT fails to work when the displayed colors are above 256 color-scaled colors, but the LUT still occupies certain area of the video memory.
  • FIG. 2 is the graphic chip block diagram of a prior art, including a graphic engine 220 , a video memory 230 , and a graph and video superposition unit 240 .
  • the video memory 230 includes a pattern memory 231 and a color LUT 232 .
  • a frame buffer can store digitalized images temporarily; therefore, the graphic chip can also include a frame buffer 250 .
  • a microprocessor 210 instructs the graphic engine 220 to obtain the graphic block from the pattern memory 231 of the video memory 230 and the frame buffer 250 to write back to the frame buffer 250 after executing the pattern block process, like masking operation, and then the graphic block is sent directly to the graph and video superposition unit 240 .
  • a color expansion through the color LUT 232 is needed and then sent graph and video superposition unit 240 .
  • a color space conversion CSC
  • the input format is Y, Cb and Cr, but the output format is R, G and B, and the output format is Y, Cb and Cr, a process of the color space conversion is necessary to make the color formats in accordance (because it is not the emphasis of this invention, it will not be described in detail).
  • the present invention provides a method for sharing the video memory of a graphic chip comprising the steps of storing a color look up table (LUT) in a sharing memory of pattern and color LUT in the video memory of the graphic chip while a destination block of a frame buffer executes color expansion; and storing a plurality of pattern blocks in the sharing memory of pattern and color LUT for the access of the graphic engine while the graphic engine accesses a pattern memory.
  • LUT color look up table
  • the present invention also provides a design method of a graphic chip comprising a sharing memory of pattern and color LUT is configured in a video memory of the graphic chip, wherein the sharing memory of pattern and color LUT works as a color LUT when a destination block of a frame buffer proceeds to color expansion, and works as a pattern memory when a graphic engine accesses a pattern block.
  • the present invention provides a graphic chip sharing video memory comprising a video memory for storing one sharing memory of a pattern and color LUT at least, and the contents of the sharing memory of pattern and color LUT adjusted in accordance with an access apparatus; and a graphic engine for accessing and processing a plurality of pattern blocks of the sharing memory of pattern and color LUT.
  • the physical layout area of a graphic chip can be reduced so that the cost drops by a method for sharing the video memory of a graphic chip and the design method of the graphic chip based on the present invention.
  • FIG. 1A is the flowchart for the graphic engine of a prior art to process a pattern block
  • FIG. 1B is the flowchart of the color expansion of a prior art
  • FIG. 2 is the block diagram of the graphic of a prior art
  • FIG. 3 is the method for sharing the video memory for a graphic chip in accordance with a preferred embodiment of the present invention.
  • FIG. 4 is the block diagram of a graphic chip in accordance with the present invention.
  • FIG. 3 is the method for sharing the video memory of a graphic chip in accordance with a preferred embodiment of the present invention.
  • Step 310 judges the access apparatus and content of the video memory. If the access apparatus is a graphic engine and the content of the sharing memory of pattern and color LUT is the pattern block, the sharing memory of pattern and color LUT is accessed in Step 350 . If the content of the sharing memory of pattern and color LUT is the color LUT, the copy of the pattern block is written to the sharing memory of pattern and color LUT in Step 330 , and the sharing memory of pattern and color LUT is accessed in Step 350 .
  • Step 350 If the content of the sharing memory of pattern and color LUT is the pattern block, the copy of the color LUT is written to the sharing memory of pattern and color LUT in Step 340 , and then the sharing memory of pattern and color LUT is accessed in Step 350 .
  • FIG. 4 is the block diagram of the graphic chip in accordance with the present invention.
  • the graphic chip comprising a graphic engine 420 , a video memory 430 , and a graph and video overlapping unit 440 , wherein the video memory 430 further comprising a sharing memory of pattern and color LUT 431 , and the graphic chip can also comprising a frame buffer 450 .
  • a microprocessor 410 instructs the graph engine 420 to obtain the graphic block from the sharing memory of pattern and color LUT of the video memory 430 and the frame buffer 450 to write back to the frame buffer 450 after executing the pattern block process, like masking operation, and then the graphic block is sent directly to the graph and video overlapping unit 440 .
  • the color LUT stored in the sharing memory of pattern and color LUT 431 is accessed to execute color expansion, and then sent to the graph and video superposition unit 440 , including reading the copy of the color LUT 462 in the external memory 460 and then writing to the video memory 430 for color expansion.
  • an external memory 460 like an SDRAM can be provided to store the copy of the pattern block 461 and the copy of the color LUT 462 for different access needs.
  • the copy of the color LUT 462 can be written to the sharing the sharing memory of pattern and color LUT 431 for color expansion.
  • the copy of the pattern block 461 can be written to the sharing memory of pattern and color LUT 431 for the access of the graphic engine 420 .

Abstract

A method and apparatus for sharing the video memory of a graphic chip includes the steps as follows: when the destination block of a frame buffer executes color expansion, storing a color LUT to a memory shared by both pattern and color LUT in a video memory, so as to provide color expansion; and when the graphic engine accesses a pattern memory, storing a pattern block to the memory shared by both pattern and color LUT for the access of a graphic engine. By the above-mentioned sharing mechanism, the physical layout area of the graphic chip is reduced and the cost also drops.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to the usage of video memory, especially to a method and apparatus for sharing the video memory of a graphic chip.
  • 2. Description of the Prior Art
  • Generally, a graphic engine obtains the graphic block from a source/destination/pattern block and the pattern block from the other source/destination/pattern block to have various logic executions, and then writes back to a frame buffer to be displayed in a screen. Therein, the source block can be obtained from a CPU, main memory and the frame buffer itself. The pattern block can also be obtained from the CPU, pattern memory and pattern register to write back to the destination block after executing a masking operation. But among the obtained blocks, the pattern memory is the largest block in a graphic chip. Taking a 16×16-pixel true color video area as an example, a 768-byte (16×16×3) memory is configured in a graphic chip (in true color, every pixel includes 3 bytes to represent 3 primary colors) to work as a pattern memory. FIG. 1A is the flowchart for the graphic engine of a prior art processing a pattern block. Step 110 is to configure a pattern block in a pattern memory. Step 130 is to access the pattern block in the pattern memory if the graphic engine needs to process the pattern block. And then Step 150 is to store the processed pattern block in a frame buffer.
  • In another side, FIG. 1B is the color expansion flowchart of a prior art. Step 120 is to configure a look up table (LUT) in a video memory. Step 140 is to expand colors in accordance with the LUT if the destination block of the frame buffer needs to expand colors. And then Step 160 is to superpose and output the color-expanded destination block and the other graph and video source. In another word, the LUT stored in the video memory of a graphic chip recovers the color index stored in a frame buffer, so called pixel value, into the true color RGB 24-bit pixel value by looking up the table when the displayed colors are 256 or under 256 color-scaled colors (indirect colors). When the displayed colors are the above 256 color-scaled colors, the information of R, G and B is not necessary to be recovered by looking up the LUT, because the information included in R, G and B is already the original information of the colors at this moment. It is called direct color. Therefore, the LUT fails to work when the displayed colors are above 256 color-scaled colors, but the LUT still occupies certain area of the video memory.
  • FIG.2 is the graphic chip block diagram of a prior art, including a graphic engine 220, a video memory 230, and a graph and video superposition unit 240. The video memory 230 includes a pattern memory 231 and a color LUT 232. Besides, a frame buffer can store digitalized images temporarily; therefore, the graphic chip can also include a frame buffer 250. A microprocessor 210 instructs the graphic engine 220 to obtain the graphic block from the pattern memory 231 of the video memory 230 and the frame buffer 250 to write back to the frame buffer 250 after executing the pattern block process, like masking operation, and then the graphic block is sent directly to the graph and video superposition unit 240. If the displayed colors are 256 or under 256 color-scaled colors, a color expansion through the color LUT 232 is needed and then sent graph and video superposition unit 240. Besides, if the input color format is different from the covering color format, a color space conversion (CSC) is also needed. For example, if the input format is Y, Cb and Cr, but the output format is R, G and B, and the output format is Y, Cb and Cr, a process of the color space conversion is necessary to make the color formats in accordance (because it is not the emphasis of this invention, it will not be described in detail).
  • Because the usage moment of the pattern memory and color LUT are exclusive and in timing order, and the access paths of the pattern area and the color expansion are overlapped because they both are in the pattern memory, how to reduce the layout of the pattern memory in the graphic chip and how to use the video memory in the graphic chip are the challenges that the technology field has to face.
    • SUMMARY OF THE INVENTION
  • The present invention provides a method for sharing the video memory of a graphic chip comprising the steps of storing a color look up table (LUT) in a sharing memory of pattern and color LUT in the video memory of the graphic chip while a destination block of a frame buffer executes color expansion; and storing a plurality of pattern blocks in the sharing memory of pattern and color LUT for the access of the graphic engine while the graphic engine accesses a pattern memory.
  • The present invention also provides a design method of a graphic chip comprising a sharing memory of pattern and color LUT is configured in a video memory of the graphic chip, wherein the sharing memory of pattern and color LUT works as a color LUT when a destination block of a frame buffer proceeds to color expansion, and works as a pattern memory when a graphic engine accesses a pattern block.
  • Again, the present invention provides a graphic chip sharing video memory comprising a video memory for storing one sharing memory of a pattern and color LUT at least, and the contents of the sharing memory of pattern and color LUT adjusted in accordance with an access apparatus; and a graphic engine for accessing and processing a plurality of pattern blocks of the sharing memory of pattern and color LUT.
  • The physical layout area of a graphic chip can be reduced so that the cost drops by a method for sharing the video memory of a graphic chip and the design method of the graphic chip based on the present invention.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1A is the flowchart for the graphic engine of a prior art to process a pattern block;
  • FIG. 1B is the flowchart of the color expansion of a prior art;
  • FIG. 2 is the block diagram of the graphic of a prior art;
  • FIG. 3 is the method for sharing the video memory for a graphic chip in accordance with a preferred embodiment of the present invention; and
  • FIG. 4 is the block diagram of a graphic chip in accordance with the present invention.
    • DESCRIPTION OF THE PREFERRED EMBODIMENT
  • Some embodiments of the present invention will be described in detail as the following. But, besides the description in detail, the present invention can be implemented in the other embodiments broadly, and the scope of the present invention is not limited, in accordance with the following claims.
  • For providing clearer description and understanding the present invention more easily, every part of the drawings is not drew in its relative dimensions. Certain dimensions and the other ratios of the relative scales are exaggerated. The irrelevant details are not drawn completely for the simplicity of the drawings.
  • FIG. 3 is the method for sharing the video memory of a graphic chip in accordance with a preferred embodiment of the present invention. Step 310 judges the access apparatus and content of the video memory. If the access apparatus is a graphic engine and the content of the sharing memory of pattern and color LUT is the pattern block, the sharing memory of pattern and color LUT is accessed in Step 350. If the content of the sharing memory of pattern and color LUT is the color LUT, the copy of the pattern block is written to the sharing memory of pattern and color LUT in Step 330, and the sharing memory of pattern and color LUT is accessed in Step 350. In another side, if the destination block of a frame buffer proceeds to color expansion in Step 320, and the content of the sharing memory of pattern and color LUT is the color LUT, the sharing memory of pattern and color LUT is accessed in Step 350. If the content of the sharing memory of pattern and color LUT is the pattern block, the copy of the color LUT is written to the sharing memory of pattern and color LUT in Step 340, and then the sharing memory of pattern and color LUT is accessed in Step 350.
  • FIG. 4 is the block diagram of the graphic chip in accordance with the present invention. The graphic chip comprising a graphic engine 420, a video memory 430, and a graph and video overlapping unit 440, wherein the video memory 430 further comprising a sharing memory of pattern and color LUT 431, and the graphic chip can also comprising a frame buffer 450. A microprocessor 410 instructs the graph engine 420 to obtain the graphic block from the sharing memory of pattern and color LUT of the video memory 430 and the frame buffer 450 to write back to the frame buffer 450 after executing the pattern block process, like masking operation, and then the graphic block is sent directly to the graph and video overlapping unit 440. In another side, if the displayed colors in the destination block are 256 or under 256 color-scaled colors, the color LUT stored in the sharing memory of pattern and color LUT 431 is accessed to execute color expansion, and then sent to the graph and video superposition unit 440, including reading the copy of the color LUT 462 in the external memory 460 and then writing to the video memory 430 for color expansion. In another word, because of sharing the sharing memory of pattern and color LUT 431 (like an SRAM), an external memory 460 (like an SDRAM) can be provided to store the copy of the pattern block 461 and the copy of the color LUT 462 for different access needs. If the content of the sharing memory of pattern and color LUT 431 is the pattern block, and the destination block of the frame buffer 450 will execute color expansion, the copy of the color LUT 462 can be written to the sharing the sharing memory of pattern and color LUT 431 for color expansion. In another side, if the content of the sharing memory of pattern and color LUT 431 is the color LUT, and the graphic engine 420 will access the pattern memory, the copy of the pattern block 461 can be written to the sharing memory of pattern and color LUT 431 for the access of the graphic engine 420.
  • While the described embodiment represents the preferred form of the present invention, it is to be understood that modifications will occur to those skilled in that art without departing from the spirit of the invention. The scope of the invention is therefore to be determined solely by the appended claims.

Claims (5)

1-6. (canceled)
7. A graphic chip with a sharing video memory comprising:
a video memory for storing one sharing memory of a pattern and color LUT at least, and a content of said sharing memory of pattern and color LUT is adjusted in accordance with an access apparatus; and
a graphic engine for accessing and processing a plurality of pattern blocks of said sharing memory of pattern and color LUT.
8. The graphic chip with a sharing video memory as recited in claim 7 comprising:
a graph and video overlapping unit for receiving and overlapping a destination block of a frame buffer and a graph and video source.
9. The graphic chip with a sharing video memory as recited in claim 7 comprising:
a frame buffer for storing a destination block at least for a graph and video overlapping unit to perform an overlapping procedure.
10. The graphic chip with a sharing video memory as recited in claim 7, wherein if the access apparatus is a frame buffer, said sharing memory of pattern and color LUT provided for storing said color LUT, whereas if the access apparatus is said graphic engine, said sharing memory of pattern and color LUT provided for storing said plurality of said pattern blocks.
US11/335,597 2003-05-23 2006-01-20 Method and apparatus for pattern ram sharing color look up table Abandoned US20060119605A1 (en)

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US47273203P 2003-05-23 2003-05-23
US10/851,220 US20040233204A1 (en) 2003-05-23 2004-05-24 Method and apparatus for pattern ram sharing color look up table
US11/335,597 US20060119605A1 (en) 2003-05-23 2006-01-20 Method and apparatus for pattern ram sharing color look up table

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US10/851,222 Active 2029-08-12 US7812890B2 (en) 2003-05-23 2004-05-24 Auto-configuration for instrument setting
US10/851,239 Active 2025-10-29 US7206026B2 (en) 2003-05-23 2004-05-24 Method and apparatus for adaptive frame rate conversion
US10/851,240 Active 2025-09-29 US7196731B2 (en) 2003-05-23 2004-05-24 Method and apparatus of adaptive de-interlacing of dynamic image
US10/851,220 Abandoned US20040233204A1 (en) 2003-05-23 2004-05-24 Method and apparatus for pattern ram sharing color look up table
US10/851,101 Active 2026-04-08 US7420569B2 (en) 2003-05-23 2004-05-24 Adaptive pixel-based blending method and system
US10/851,223 Abandoned US20040233217A1 (en) 2003-05-23 2004-05-24 Adaptive pixel-based blending method and system
US10/851,242 Active 2025-10-08 US7242436B2 (en) 2003-05-23 2004-05-24 Selection methodology of de-interlacing algorithm of dynamic image
US10/851,241 Active 2025-09-29 US7190405B2 (en) 2003-05-23 2004-05-24 Method and apparatus of adaptive de-interlacing of dynamic image
US10/851,224 Active 2025-10-14 US7206028B2 (en) 2003-05-23 2004-05-24 Method and apparatus of adaptive de-interlacing of dynamic image
US11/335,597 Abandoned US20060119605A1 (en) 2003-05-23 2006-01-20 Method and apparatus for pattern ram sharing color look up table

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US10/851,239 Active 2025-10-29 US7206026B2 (en) 2003-05-23 2004-05-24 Method and apparatus for adaptive frame rate conversion
US10/851,240 Active 2025-09-29 US7196731B2 (en) 2003-05-23 2004-05-24 Method and apparatus of adaptive de-interlacing of dynamic image
US10/851,220 Abandoned US20040233204A1 (en) 2003-05-23 2004-05-24 Method and apparatus for pattern ram sharing color look up table
US10/851,101 Active 2026-04-08 US7420569B2 (en) 2003-05-23 2004-05-24 Adaptive pixel-based blending method and system
US10/851,223 Abandoned US20040233217A1 (en) 2003-05-23 2004-05-24 Adaptive pixel-based blending method and system
US10/851,242 Active 2025-10-08 US7242436B2 (en) 2003-05-23 2004-05-24 Selection methodology of de-interlacing algorithm of dynamic image
US10/851,241 Active 2025-09-29 US7190405B2 (en) 2003-05-23 2004-05-24 Method and apparatus of adaptive de-interlacing of dynamic image
US10/851,224 Active 2025-10-14 US7206028B2 (en) 2003-05-23 2004-05-24 Method and apparatus of adaptive de-interlacing of dynamic image

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Families Citing this family (67)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6489998B1 (en) * 1998-08-11 2002-12-03 Dvdo, Inc. Method and apparatus for deinterlacing digital video images
US8698840B2 (en) * 1999-03-05 2014-04-15 Csr Technology Inc. Method and apparatus for processing video and graphics data to create a composite output image having independent and separate layers of video and graphics display planes
US7319754B2 (en) * 2002-06-28 2008-01-15 Stmicroelectronics S.A. Insertion of binary messages in video pictures
DE10340544B4 (en) * 2003-09-01 2006-08-03 Siemens Ag Device for visual support of electrophysiology catheter application in the heart
DE10340546B4 (en) 2003-09-01 2006-04-20 Siemens Ag Method and apparatus for visually assisting electrophysiology catheter application in the heart
JP2005080133A (en) * 2003-09-02 2005-03-24 Sanyo Electric Co Ltd Image signal processing circuit
GB2411784B (en) * 2004-03-02 2006-05-10 Imagination Tech Ltd Motion compensation deinterlacer protection
US7483577B2 (en) * 2004-03-02 2009-01-27 Mitsubishi Electric Research Laboratories, Inc. System and method for joint de-interlacing and down-sampling using adaptive frame and field filtering
JP2005333254A (en) * 2004-05-18 2005-12-02 Sony Corp Apparatus and method for image processing
US20050268226A1 (en) * 2004-05-28 2005-12-01 Lipsky Scott E Method and system for displaying image information
KR100631685B1 (en) * 2004-06-15 2006-10-09 삼성전자주식회사 Image processing apparatus and method
TWI245198B (en) * 2004-09-01 2005-12-11 Via Tech Inc Deinterlace method and method for generating deinterlace algorithm of display system
KR20060021446A (en) * 2004-09-03 2006-03-08 삼성전자주식회사 Method for deinterlacing and apparatus thereof
CN100411422C (en) * 2004-09-13 2008-08-13 威盛电子股份有限公司 Input-output regulating device and method of audio-visual system
JP4366277B2 (en) * 2004-09-21 2009-11-18 キヤノン株式会社 Imaging apparatus and control method thereof
TWI280798B (en) * 2004-09-22 2007-05-01 Via Tech Inc Apparatus and method of adaptive de-interlace of image
US20060268978A1 (en) * 2005-05-31 2006-11-30 Yang Genkun J Synchronized control scheme in a parallel multi-client two-way handshake system
US7657255B2 (en) * 2005-06-23 2010-02-02 Microsoft Corporation Provisioning of wireless connectivity for devices using NFC
US7450184B1 (en) * 2005-06-27 2008-11-11 Magnum Semiconductor, Inc. Circuits and methods for detecting 2:2 encoded video and systems utilizing the same
US7522214B1 (en) * 2005-06-27 2009-04-21 Magnum Semiconductor, Inc. Circuits and methods for deinterlacing video display data and systems using the same
US7420626B1 (en) * 2005-06-27 2008-09-02 Magnum Semiconductor, Inc. Systems and methods for detecting a change in a sequence of interlaced data fields generated from a progressive scan source
US7623183B2 (en) * 2005-06-29 2009-11-24 Novatek Microelectronics Corp. Frame rate adjusting method and apparatus for displaying video on interlace display devices
US7456904B2 (en) * 2005-09-22 2008-11-25 Pelco, Inc. Method and apparatus for superimposing characters on video
US7924345B2 (en) * 2005-10-20 2011-04-12 Broadcom Corp. Method and system for deinterlacing using polarity change count
JP4687404B2 (en) * 2005-11-10 2011-05-25 ソニー株式会社 Image signal processing apparatus, imaging apparatus, and image signal processing method
US8659704B2 (en) * 2005-12-20 2014-02-25 Savant Systems, Llc Apparatus and method for mixing graphics with video images
US20070143801A1 (en) * 2005-12-20 2007-06-21 Madonna Robert P System and method for a programmable multimedia controller
EP1977395B1 (en) 2006-01-27 2018-10-24 Imax Corporation Methods and systems for digitally re-mastering of 2d and 3d motion pictures for exhibition with enhanced visual quality
WO2007129257A1 (en) * 2006-05-04 2007-11-15 Koninklijke Philips Electronics N.V. Controlled frame rate conversion
CA2884702C (en) 2006-06-23 2018-06-05 Samuel Zhou Methods and systems for converting 2d motion pictures for stereoscopic 3d exhibition
JP5053373B2 (en) 2006-06-29 2012-10-17 トムソン ライセンシング Adaptive pixel-based filtering
US7940973B2 (en) * 2006-09-19 2011-05-10 Capso Vision Inc. Capture control for in vivo camera
JP5330246B2 (en) * 2006-09-29 2013-10-30 トムソン ライセンシング Automatic parameter estimation for adaptive pixel-based filtering
US8233087B2 (en) * 2006-11-08 2012-07-31 Marvell International Ltd. Systems and methods for deinterlacing high-definition and standard-definition video
JP4270270B2 (en) * 2006-12-05 2009-05-27 ソニー株式会社 Electronic device, imaging apparatus, electronic device control method and program
EP1931136B1 (en) * 2006-12-08 2016-04-20 Panasonic Intellectual Property Corporation of America Block-based line combination algorithm for de-interlacing
US8115866B2 (en) * 2006-12-29 2012-02-14 Texas Instruments Incorporated Method for detecting film pulldown cadences
US8612857B2 (en) * 2007-01-08 2013-12-17 Apple Inc. Monitor configuration for media device
US8607144B2 (en) * 2007-01-08 2013-12-10 Apple Inc. Monitor configuration for media device
US8233086B2 (en) * 2007-06-08 2012-07-31 Nintendo Co., Ltd. Process for digitizing video over analog component video cables
MX2010002657A (en) * 2007-09-05 2010-04-09 Savant Systems Llc Multimedia control and distribution architechture.
US20090161011A1 (en) * 2007-12-21 2009-06-25 Barak Hurwitz Frame rate conversion method based on global motion estimation
TWI384884B (en) * 2008-01-11 2013-02-01 Ultrachip Inc Method for displaying dynamical colorful picture frame
US8275033B2 (en) * 2008-01-15 2012-09-25 Sony Corporation Picture mode selection for video transcoding
US9204086B2 (en) * 2008-07-17 2015-12-01 Broadcom Corporation Method and apparatus for transmitting and using picture descriptive information in a frame rate conversion processor
KR101467875B1 (en) * 2008-09-04 2014-12-02 삼성전자주식회사 Digital camera for varying frame rate and the controlling method thereof
US10075670B2 (en) * 2008-09-30 2018-09-11 Entropic Communications, Llc Profile for frame rate conversion
TWI384865B (en) * 2009-03-18 2013-02-01 Mstar Semiconductor Inc Image processing method and circuit
TWI452909B (en) * 2009-06-29 2014-09-11 Silicon Integrated Sys Corp Circuit for correcting motion vectors, image generating device and method thereof
US8699778B2 (en) * 2009-07-29 2014-04-15 Panasonic Corporation Image coding method, image coding apparatus, program, and integrated circuit
JP5641743B2 (en) * 2010-02-02 2014-12-17 キヤノン株式会社 Image processing apparatus and image processing apparatus control method
CN103295549B (en) * 2010-04-02 2015-09-02 宏碁股份有限公司 Display and display packing thereof
TWI412278B (en) * 2010-05-03 2013-10-11 Himax Tech Ltd Film-mode frame rate up conversion system and method
JP5810307B2 (en) * 2010-05-10 2015-11-11 パナソニックＩｐマネジメント株式会社 Imaging device
JP2013026727A (en) 2011-07-19 2013-02-04 Sony Corp Display device and display method
US9324170B2 (en) 2011-08-18 2016-04-26 Hewlett-Packard Development Company, L.P. Creating a blended image
WO2014162604A1 (en) * 2013-04-05 2014-10-09 株式会社 東芝 Electronic device and handwriting data processing method
CN106412647B (en) * 2015-07-29 2019-05-31 国基电子（上海）有限公司 The set-top box of signal switching system and application the signal switching system
US9552623B1 (en) * 2015-11-04 2017-01-24 Pixelworks, Inc. Variable frame rate interpolation
CN106569766A (en) * 2016-11-08 2017-04-19 惠州Tcl移动通信有限公司 Method and system for performing virtual dynamic processing based on display interface
JP6958249B2 (en) * 2017-11-06 2021-11-02 セイコーエプソン株式会社 Profile adjustment system, profile adjustment device, profile adjustment method, and profile adjustment program
US10230920B1 (en) * 2017-12-06 2019-03-12 Pixelworks, Inc. Adjusting interpolation phase for MEMC using image analysis
US10977809B2 (en) 2017-12-11 2021-04-13 Dolby Laboratories Licensing Corporation Detecting motion dragging artifacts for dynamic adjustment of frame rate conversion settings
WO2019244326A1 (en) * 2018-06-22 2019-12-26 三菱電機株式会社 Video display device
EP3648059B1 (en) * 2018-10-29 2021-02-24 Axis AB Video processing device and method for determining motion metadata for an encoded video
US11064108B2 (en) * 2019-08-21 2021-07-13 Sony Corporation Frame rate control for media capture based on rendered object speed
US11593061B2 (en) 2021-03-19 2023-02-28 International Business Machines Corporation Internet of things enable operated aerial vehicle to operated sound intensity detector

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4916301A (en) * 1987-02-12 1990-04-10 International Business Machines Corporation Graphics function controller for a high performance video display system
US5175811A (en) * 1987-05-20 1992-12-29 Hitachi, Ltd. Font data processor using addresses calculated on the basis of access parameters
US5557734A (en) * 1994-06-17 1996-09-17 Applied Intelligent Systems, Inc. Cache burst architecture for parallel processing, such as for image processing
US5557733A (en) * 1993-04-02 1996-09-17 Vlsi Technology, Inc. Caching FIFO and method therefor
US5742298A (en) * 1994-12-30 1998-04-21 Cirrus Logic, Inc. 64 bit wide video front cache
US5787466A (en) * 1996-05-01 1998-07-28 Sun Microsystems, Inc. Multi-tier cache and method for implementing such a system
US6198543B1 (en) * 1998-02-05 2001-03-06 Canon Kabushiki Kaisha Color table look-up using compressed image data
US20020080091A1 (en) * 2000-12-22 2002-06-27 Shrikant Acharya Information transmission and display method and system for a handheld computing device

Family Cites Families (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS628193A (en) * 1985-07-04 1987-01-16 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Color image display system
US4829455A (en) * 1986-04-11 1989-05-09 Quantel Limited Graphics system for video and printed images
US5128776A (en) * 1989-06-16 1992-07-07 Harris Corporation Prioritized image transmission system and method
US5631850A (en) * 1992-09-11 1997-05-20 Sony Corporation Audio visual equipment with a digital bus system and method for initializing and confirming connection
US5565929A (en) * 1992-10-13 1996-10-15 Sony Corporation Audio-visual control apparatus for determining a connection of appliances and controlling functions of appliances
JP3272463B2 (en) * 1993-04-15 2002-04-08 株式会社ソニー・コンピュータエンタテインメント Image forming apparatus and method of using the same
US5586236A (en) * 1993-08-11 1996-12-17 Object Technology Licensing Corp. Universal color look up table and method of generation
US5444835A (en) * 1993-09-02 1995-08-22 Apple Computer, Inc. Apparatus and method for forming a composite image pixel through pixel blending
JP3228381B2 (en) * 1993-10-29 2001-11-12 ソニー株式会社 AV selector
US5521644A (en) * 1994-06-30 1996-05-28 Eastman Kodak Company Mechanism for controllably deinterlacing sequential lines of video data field based upon pixel signals associated with four successive interlaced video fields
JPH0944693A (en) * 1995-08-02 1997-02-14 Victor Co Of Japan Ltd Graphic display device
US5721842A (en) * 1995-08-25 1998-02-24 Apex Pc Solutions, Inc. Interconnection system for viewing and controlling remotely connected computers with on-screen video overlay for controlling of the interconnection switch
EP0860080B1 (en) * 1995-11-08 1999-06-09 Genesis Microchip Inc. Method and apparatus for de-interlacing video fields to progressive scan video frames
US6023302A (en) * 1996-03-07 2000-02-08 Powertv, Inc. Blending of video images in a home communications terminal
KR100203264B1 (en) * 1996-06-29 1999-06-15 윤종용 Method and device for subpicture decoding in a digital video disc system
JPH10126702A (en) * 1996-10-23 1998-05-15 Kokusai Electric Co Ltd Signal connection switching device
WO1998025403A2 (en) * 1996-12-06 1998-06-11 Koninklijke Philips Electronics N.V. Mixing a graphics signal and a video signal
KR100238579B1 (en) 1997-04-15 2000-01-15 윤종용 Method and apparatus for automatically selecting bnc/d-sub signal of display device having dpms function
US5864369A (en) * 1997-06-16 1999-01-26 Ati International Srl Method and apparatus for providing interlaced video on a progressive display
KR100249228B1 (en) * 1997-08-28 2000-03-15 구자홍 Aspect Ratio Conversion Apparatus in Digital Television
US6108047A (en) * 1997-10-28 2000-08-22 Stream Machine Company Variable-size spatial and temporal video scaler
KR100287850B1 (en) * 1997-12-31 2001-05-02 구자홍 Deinterlacing system and method of digital tv
JPH11355585A (en) * 1998-06-04 1999-12-24 Toshiba Corp Color image processor
US6489998B1 (en) * 1998-08-11 2002-12-03 Dvdo, Inc. Method and apparatus for deinterlacing digital video images
US6515706B1 (en) * 1998-09-15 2003-02-04 Dvdo, Inc. Method and apparatus for detecting and smoothing diagonal features video images
AU4489400A (en) * 1999-04-26 2000-11-10 Gibson Guitar Corp. Universal audio communications and control system and method
DE60040517D1 (en) * 1999-05-25 2008-11-27 Nxp Bv IMPLEMENTATION OF PICTURE SIGNALS TRIMMING WITH LINE LEVELS IN PROGRESSIVE PICTURED PICTURE SIGNALS
US6331874B1 (en) * 1999-06-29 2001-12-18 Lsi Logic Corporation Motion compensated de-interlacing
US6421090B1 (en) * 1999-08-27 2002-07-16 Trident Microsystems, Inc. Motion and edge adaptive deinterlacing
US6459455B1 (en) * 1999-08-31 2002-10-01 Intel Corporation Motion adaptive deinterlacing
US6330032B1 (en) * 1999-09-30 2001-12-11 Focus Enhancements, Inc. Motion adaptive de-interlace filter
JP3587113B2 (en) * 2000-01-17 2004-11-10 ヤマハ株式会社 Connection setting device and medium
US6480231B1 (en) * 2000-03-24 2002-11-12 Flashpoint Technology, Inc. Efficiently de-interlacing a buffer of image data
WO2001080219A2 (en) * 2000-04-14 2001-10-25 Realnetworks, Inc. A system and method of providing music items to music renderers
US6690425B1 (en) * 2000-06-22 2004-02-10 Thomson Licensing S.A. Aspect ratio control arrangement in a video display
US6661464B1 (en) * 2000-11-21 2003-12-09 Dell Products L.P. Dynamic video de-interlacing
KR100351160B1 (en) * 2000-12-06 2002-09-05 엘지전자 주식회사 Apparatus and method for compensating video motions
EP1356670A1 (en) * 2000-12-11 2003-10-29 Koninklijke Philips Electronics N.V. Motion compensated de-interlacing in video signal processing
US7020213B2 (en) * 2000-12-28 2006-03-28 Teac Corporation Method and apparatus for selectively providing different electric signal paths between circuits
US7030930B2 (en) * 2001-03-06 2006-04-18 Ati Technologies, Inc. System for digitized audio stream synchronization and method thereof
US6859235B2 (en) * 2001-05-14 2005-02-22 Webtv Networks Inc. Adaptively deinterlacing video on a per pixel basis
JP4596222B2 (en) * 2001-06-26 2010-12-08 ソニー株式会社 Image processing apparatus and method, recording medium, and program
KR100412503B1 (en) * 2001-12-13 2003-12-31 삼성전자주식회사 SetTop Box capable of setting easily resolution of digital broadcast signal
US7061540B2 (en) * 2001-12-19 2006-06-13 Texas Instruments Incorporated Programmable display timing generator
KR100902315B1 (en) * 2002-07-25 2009-06-12 삼성전자주식회사 Apparatus and method for deinterlacing
CN1175378C (en) * 2002-07-26 2004-11-10 威盛电子股份有限公司 Deivce and method for processing covered picture to become transparent one
US7113597B2 (en) * 2002-10-24 2006-09-26 Hewlett-Packard Development Company,Lp. System and method for protection of video signals
US7034888B2 (en) * 2003-03-26 2006-04-25 Silicon Integrated Systems Corp. Method for motion pixel detection
US7129987B1 (en) * 2003-07-02 2006-10-31 Raymond John Westwater Method for converting the resolution and frame rate of video data using Discrete Cosine Transforms

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4916301A (en) * 1987-02-12 1990-04-10 International Business Machines Corporation Graphics function controller for a high performance video display system
US5175811A (en) * 1987-05-20 1992-12-29 Hitachi, Ltd. Font data processor using addresses calculated on the basis of access parameters
US5557733A (en) * 1993-04-02 1996-09-17 Vlsi Technology, Inc. Caching FIFO and method therefor
US5557734A (en) * 1994-06-17 1996-09-17 Applied Intelligent Systems, Inc. Cache burst architecture for parallel processing, such as for image processing
US5742298A (en) * 1994-12-30 1998-04-21 Cirrus Logic, Inc. 64 bit wide video front cache
US5787466A (en) * 1996-05-01 1998-07-28 Sun Microsystems, Inc. Multi-tier cache and method for implementing such a system
US6198543B1 (en) * 1998-02-05 2001-03-06 Canon Kabushiki Kaisha Color table look-up using compressed image data
US20020080091A1 (en) * 2000-12-22 2002-06-27 Shrikant Acharya Information transmission and display method and system for a handheld computing device

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