US20060066354A1 - Low power outpur driver - Google Patents

Low power outpur driver Download PDF

Info

Publication number
US20060066354A1
US20060066354A1 US11/234,911 US23491105A US2006066354A1 US 20060066354 A1 US20060066354 A1 US 20060066354A1 US 23491105 A US23491105 A US 23491105A US 2006066354 A1 US2006066354 A1 US 2006066354A1
Authority
US
United States
Prior art keywords
driver
nmos
voltage
output
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US11/234,911
Other versions
US7342420B2 (en
Inventor
Tacettin Isik
Louis Poitras
Daniel Clementi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics America Inc
Original Assignee
ICS Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US11/234,911 priority Critical patent/US7342420B2/en
Application filed by ICS Inc filed Critical ICS Inc
Publication of US20060066354A1 publication Critical patent/US20060066354A1/en
Assigned to INTEGRATED DEVICE TECHNOLOGY, INC. reassignment INTEGRATED DEVICE TECHNOLOGY, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ICS TECHNOLOGIES, INC.
Assigned to ICS TECHNOLOGIES, INC. reassignment ICS TECHNOLOGIES, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CLEMENTI, DANIEL M., ISIK, TACETTIN, POITRAS, LOUIS F.
Priority to US11/931,191 priority patent/US7821297B2/en
Publication of US7342420B2 publication Critical patent/US7342420B2/en
Application granted granted Critical
Priority to US12/342,160 priority patent/US7830177B2/en
Assigned to JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT reassignment JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT SECURITY AGREEMENT Assignors: CHIPX, INCORPORATED, ENDWAVE CORPORATION, GIGPEAK, INC., INTEGRATED DEVICE TECHNOLOGY, INC., MAGNUM SEMICONDUCTOR, INC.
Assigned to ENDWAVE CORPORATION, GIGPEAK, INC., CHIPX, INCORPORATED, MAGNUM SEMICONDUCTOR, INC., INTEGRATED DEVICE TECHNOLOGY, INC. reassignment ENDWAVE CORPORATION RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: JPMORGAN CHASE BANK, N.A.
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0278—Arrangements for impedance matching
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS

Definitions

  • the present invention relates generally to an output driver, and more particularly, to a low power output driver utilizing voltage lower than the supply voltage or rail voltage.
  • CMOS complementary metal oxide semiconductors
  • FIG. 3 e.g., an inverted CML
  • the CMOS can be either n-type or p-type devices.
  • the configuration shown includes a p-type CMOS over an n-type CMOS for each CMOS pair.
  • the n-type CMOS are not really doing anything active, as shown, but are provided for ESD protection.
  • the supply voltage (V DD ) or rail voltage is applied to the supply of the drivers and to the CMOS pairs.
  • Each CMOS pair is connected to a pad.
  • a series resistor R S is connected between each of the pads and a respective transmission line to “decouple” the output capacitance of the driver from the transmission line itself, i.e., it makes the impedance at the source of the transmission line more purely resistive.
  • a termination resistor R T is connected between the junction of the series resistor R S and transmission line T L and ground to create a fixed impedance.
  • a current mirror circuit is connected between the rail voltage and the high side of the CMOS pairs. The current mirror is driven or controlled by a reference current I REF . The power consumption of this prior art circuit is primarily determined by the current constantly being sourced through one or the other terminating resistors R T .
  • a typical current draw through the current mirror is on the order of 14-15 mA.
  • the resulting voltage drop across each terminating resistor R T is on the order of 750 millivolts (mV).
  • the power draw, independent of the load condition is about 50 milliwatts (mW). Since one CMOS pair or the other is always connected to one of the pads, power is constantly dissipated using the conventional circuit due to the bleeding current through the respective terminating resistor R T .
  • driver output that utilizes a reduced voltage supply and has lower power consumption. It is also desirable to provide an on-chip reduced voltage power supply or regulator in combination with a plurality of low power output drivers.
  • the present invention comprises a low power output driver that includes one of a series-regulated and a switching-mode-regulated reduced voltage source.
  • the reduced voltage source receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage.
  • the driver also includes a first driver input that receives a first logic signal, a second driver input that receives a second logic signal, a first driver output that outputs a first output signal and a second driver output that outputs a second output signal.
  • the driver includes first, second, third and fourth n-type metal oxide semiconductor (NMOS).
  • the source and the drain of the first NMOS are electrically coupled between the reduced voltage V L and the first driver output.
  • the gate of the first NMOS is electrically coupled to the first driver input.
  • the source and the drain of the second NMOS are electrically coupled between the first driver output and an internal ground.
  • the gate of the second NMOS is electrically coupled to the second driver input.
  • the source and the drain of the third NMOS are electrically coupled between the reduced voltage V L and the second driver output.
  • the gate of the third NMOS is electrically coupled to the second driver input.
  • the source and the drain of the fourth NMOS are electrically coupled between the second driver output and the internal ground.
  • the gate of the fourth NMOS is electrically coupled to the first driver input.
  • the first driver input is high and the second driver input is low
  • the first NMOS and the fourth NMOS are gated on
  • the first driver output is raised to the reduced voltage and the second driver output is pulled down to the internal ground.
  • the second input is high and the first driver input is low
  • the second NMOS and the third NMOS are gated on
  • the second driver output is raised to the reduced voltage and the first driver output is pulled down to the internal ground.
  • the present invention comprises a low power output driver system that includes a reference voltage supply V REF , a first voltage regulator that receives reference voltage supply V REF and outputs a first regulated reduced voltage V L1 that is a lower voltage than the reference voltage supply V REF and a second voltage regulator that receives reference voltage Supply V REF and outputs a second regulated reduced voltage V L2 that is a lower voltage than the reference voltage supply V REF .
  • the system also includes a first low power output driver and a second low power output driver.
  • Each of the first and second low power output drivers includes a first driver input that receives a first logic signal, a second driver input that receives a second logic signal, a first driver output that outputs a first output signal, and a second driver output that outputs a second output signal.
  • Each of the first and second low power output drivers includes first, second, third and fourth n-type metal oxide semiconductor (NMOS) that each have a gate, a source and a drain.
  • the source and the drain of the first NMOS are electrically coupled between the respective first and second reduced voltage V L1 , V L2 and the first driver output.
  • the gate of the first NMOS is electrically coupled to the first driver input.
  • the source and the drain of the second NMOS are electrically coupled between the first driver output and an internal ground.
  • the gate of the second NMOS is electrically coupled to the second driver input.
  • the source and the drain of the third NMOS are electrically coupled between the respective first and second reduced voltage V L1 , V L2 and the second driver output.
  • the gate of the third NMOS is electrically coupled to the second driver input.
  • the source and the drain of the fourth NMOS are electrically coupled between the second driver output and the internal ground.
  • the gate of the second NMOS is electrically coupled to the first driver input.
  • FIG. 1 is an electrical schematic diagram of a low power output driver and reduced voltage power supply in accordance with a first preferred embodiment of the present invention
  • FIG. 2 is an electrical schematic diagram of a low power output driver with an external reduced voltage supply in accordance with a second preferred embodiment of the present invention
  • FIG. 3 is an electrical schematic diagram of prior art output driver
  • FIGS. 4A-4B are electrical schematic diagrams of a low output power driver system in accordance with a third preferred embodiment of the present invention.
  • FIG. 5 is an electrical schematic diagram of one possible detailed circuit implementation of a programmable current source.
  • FIG. 1 is an electrical schematic diagram of a low power output driver 10 and reduced voltage power supply 30 in accordance with a first preferred embodiment of the present invention.
  • the reduced voltage power supply 30 is within the same integrated circuit (IC) (not shown) as the low power output driver 10 .
  • IC integrated circuit
  • one reduced voltage power supply 30 will supply a plurality of low power output drivers 10 all on the same IC (i.e., on the same chip).
  • the reduced voltage power supply 30 is one of a series-regulated power supply and a switching-mode-regulated power supply.
  • the reduced voltage power supply 30 receives power from an external power source such as an supply voltage (V DD ) (i.e., the rail voltage).
  • an operational amplifier (op-amp) 130 receives an internal reference current on its non-inverting input and outputs a signal to a field effect transistor (FET) 132 .
  • the internal reference may be a bandgap reference, a resistance voltage divider, an external reference, an external bandgap and the like.
  • the FET 132 then provides a reduced voltage output V L to a high-side of the low power output driver 10 and also as a feedback to the inverting input of op-amp 130 .
  • a V DD of 3.3 volts may be controlled down to about 750 mV.
  • the FET 132 may instead be a bipolar transistor and the like.
  • An external capacitor C EXT is coupled between the feedback voltage and ground to reduce line-noise, ripple and the like.
  • the external capacitor C EXT can be formed internally without departing from the present invention.
  • the low power output driver 10 includes four n-type MOS (NMOS) 100 , 102 , 110 , 112 .
  • the NMOS are configured in alternate pairs 100 , 102 and 110 , 112 that are coupled to PAD 1 and PAD 2 , respectively.
  • One NMOS 100 of the first pair 100 , 102 is coupled between the reduced voltage source V L and the first pad PAD 1 and the other NMOS 102 of the first pair 100 , 102 is coupled between the first pad PAD 1 and an internal ground.
  • one NMOS 110 of the second pair 110 , 112 is coupled between the reduced voltage source V L and the second pad PAD 2 and the other NMOS 112 of the second pair 110 , 112 is coupled between the second pad PAD 2 and an internal ground.
  • PAD 1 is pulled up to the reduced voltage V L and NMOS 112 necessarily pulls PAD 2 to ground (i.e., a cross-wire configuration).
  • PAD 2 is pulled up to the reduced voltage V L and NMOS 102 necessarily pulls PAD 1 to ground.
  • PAD 1 is pulled up to the reduced voltage V L and NMOS 102 necessarily pulls PAD 1 to ground.
  • PAD 1 is pulled high, the reduced voltage V L , there is a current draw until the pad PAD 1 , PAD 2 reaches a quiescent voltage with reduced voltage V L . But, there is not a continuous draw of current to ground as in the case of a system with terminating resistors.
  • the low power output driver 10 includes one of a series-regulated and a switching-mode-regulated reduced voltage source 30 .
  • the first supply voltage V DD1 may be 1.2 VDC, 1.5 VDC, 3.3 VDC, 5 VDC or the like.
  • the reduced voltage source 30 receives a second supply voltage V DD2 and outputs a regulated reduced voltage V L that is a lower voltage than the second supply voltage V DD2 .
  • the second supply voltage V DD2 may be the same as the first supply voltage V DD1 , may be derived from the first supply voltage V DD1 or may be from a completely separate source.
  • the second supply voltage V DD2 may be derived from a linear or switching power supply (not shown) that receives the first supply voltage V DD1 and outputs a regulated voltage that is less than or greater than the first supply voltage V DD1 .
  • the driver 10 also includes a first driver input B that receives a first logic signal, a second driver input A that receives a second logic signal, a first driver output PAD 1 that outputs a first output signal and a second driver output PAD 2 that outputs a second output signal.
  • the first and second driver inputs B, A may be applied through an amplifier, buffer or logic gate 120 , 122 , respectively.
  • Supply power for the buffers 120 , 122 is provided by a third supply voltage V DD3 .
  • the third supply voltage V DD3 may be the same as the first supply voltage V DD1 , may be derived from the first supply voltage V DD1 or may be from a completely separate source. Preferably, the third supply voltage V DD3 is greater than the reduced voltage V L .
  • the driver 10 includes first, second, third and fourth NMOS 100 , 102 , 110 , and 112 , respectively.
  • the source and the drain of the first NMOS 100 are electrically coupled between the reduced voltage V L and the first driver output PAD 1 .
  • the gate of the first NMOS 100 is electrically coupled to the first driver input B.
  • the source and the drain of the second NMOS 102 are electrically coupled between the first driver output PAD 1 and an internal ground.
  • the gate of the second NMOS 102 is electrically coupled to the second driver input A.
  • the source and the drain of the third NMOS 110 are electrically coupled between the reduced voltage V L and the second driver output A.
  • the gate of the third NMOS 110 is electrically coupled to the second driver input A.
  • the source and the drain of the fourth NMOS 112 are electrically coupled between the second driver output A and the internal ground.
  • the gate of the fourth NMOS 112 is electrically coupled to the first driver input B.
  • the second driver input A is high and the first driver input B is low, the second NMOS 102 and the third NMOS 110 are gated on, the second driver output PAD 2 is raised to the reduced voltage V L and the first driver output PAD 1 is pulled down to the internal ground.
  • the first and second pads PAD 1 , PAD 2 are typically coupled to transmission lines T L through series resistors R S .
  • the series resistance R S may be internal (before the pads PAD 1 , PAD 2 ) or external (after the pads PAD 1 , PAD 2 ).
  • the series resistance R S may simply be the load of the wire depending on the application.
  • the series resistance R S are normally used to increase the total impedance of the driver circuit 10 , including the transistor resistance plus the series resistance R S to match the impedance of the transmission lines T L1 , T L2 .
  • Driver inputs A and B may be clocks or data and the like. Each driver input A, B is connected to an NMOS pair 100 , 102 or 110 , 112 .
  • FIG. 2 is an electrical schematic diagram of a low power output driver 10 ′ with an external reduced voltage supply EXTERNAL V L in accordance with a second preferred embodiment of the present invention.
  • the low power output driver 10 ′ is substantially similar in functionality to that described above.
  • the external reduced voltage supply EXTERNAL V L is from any reduced voltage source that is external to the driver IC such as an external series-regulated power supply or an external switching-mode-regulated power supply.
  • An advantage of the present invention over a PMOS-NMOS (i.e., a complementary MOS pair or CMOS) output is that, although NMOS can be driven by 3.3 volts, PMOS would see only ⁇ 0.7 volts, assuming that its gates cannot be driven below ground, which would result in minimal enhancement or possibly none at all. Therefore, an NMOS-NMOS with reduced voltage supply V L is more stable and makes reduced power consumption possible.
  • PMOS-NMOS i.e., a complementary MOS pair or CMOS
  • FIGS. 4A-4B show a low output power driver system 200 in accordance with a third preferred embodiment of the present invention.
  • the low power output driver system 200 includes a reference voltage supply V REF , a first programmable current source 214 , a second programmable current source 224 and a third programmable current source 234 .
  • the first programmable current source 214 receives the reference supply voltage V REF and outputs a first reference voltage V REF1 .
  • the second programmable current source 224 receives the reference supply voltage V REF and outputs a second reference voltage V REF2 .
  • the third programmable current source 234 receives the reference supply voltage V REF and outputs a third reference voltage V REF3 .
  • Each of the first, second and third programmable current sources 214 , 224 , 234 may have suitable bias components associated therewith such as resistors R 213 , R 223 and R 233 , respectively.
  • the first, second and third programmable current sources 214 , 224 , 234 may include a simple resistor divider network and switch, amplifiers, transistors or the like.
  • FIG. 5 shows one possible detailed circuit implementation of the first, second and third programmable current sources 214 , 224 , 234 .
  • Each of the programmable current sources 214 , 224 , 234 include an op-amp 252 , a pass transistor T 254 , a drive transistor T 256 , a first selectable source transistor T 261 , a second selectable source transistor T 262 , a third selectable source transistor T 263 , a fourth selectable source transistor T 264 and four switches 271 - 274 .
  • the op-amp 252 receives the reference supply voltage V REF and the output of the op-amp 252 drives the gate of the pass transistor T 254 .
  • the op-amp 252 is configured as a buffer, but the op-amp 252 could be configured as an amplifier with the addition of feedback resistors.
  • the drive transistor T 256 is coupled to the pass transistor T 256 and provides source and gate voltage to each of the first-fourth selectable source transistors T 261 -T 264 .
  • the switches 271 - 274 are connected between the first-fourth selectable source transistors T 261 -T 264 and an output node 258 .
  • the first, second or third reference voltage V REF1 -V REF3 is output from the output node 258 .
  • the switches 271 - 274 can be controlled by external binary signals or can be programmed during manufacturing by jumpers or opening circuit paths, for example. Other detailed circuit implementation of the first, second and third programmable current sources 214 , 224 , 234 can be utilized without departing from the present invention.
  • the low power output driver system 200 also includes a first voltage regulator 210 that receives reference voltage supply V REF1 and outputs a first regulated voltage V L1 that is derived from the reference voltage supply V REF1 , a second voltage regulator 220 that receives reference voltage supply V REF2 and outputs a second regulated voltage V L2 that is derived from the reference voltage supply V REF2 and a third voltage regulator 230 that receives reference voltage supply V REF3 and outputs a third regulated voltage V L3 that is derived from the reference voltage supply V REF3 .
  • the first, second and third regulated voltages V L1 , V L2 , V L3 can be reduced, amplified or the same as the reference supply voltage V REF .
  • the first programmable current source 214 provides the first reference voltage V REF1 to each of the first, second and third voltage regulators 210 , 220 , 230 .
  • the reference supply voltage V REF is provided directly to each of the first, second and third voltage regulators 210 , 220 , 230 .
  • the plurality of voltage regulators 210 , 220 , 230 are provided on a single integrated circuit (IC) chip (on-chip voltage power supply or regulator).
  • IC integrated circuit
  • the voltage regulators 210 , 220 , 230 are configured to accept a relatively wide range of input voltage V in while still outputting approximately the same desired regulated voltage V L1 , V L2 , V L3 .
  • the first, second and third regulated reduced voltages V L1 , V L2 , V L3 may be the same or different voltage potentials depending on the application.
  • the low power output driver system 200 also includes first low power output driver 10 11 , a second low power output driver 10 21 and a third low power output driver 10 31 .
  • Each of the first, second and third low power output drivers 10 11 , 10 21 , 10 31 includes a low output driver circuit 10 , 10 ′ as described above with respect to the first preferred embodiment.
  • the low power output driver system 200 includes a plurality of low output drivers 10 11 - 10 1n , 10 21 - 10 2n , 10 31 - 10 3n and each set of low output drivers 10 11 - 10 1n , 10 21 - 10 2n and 10 31 - 10 3n is connected to a separate voltage regulator 210 , 220 and 230 , respectively. Since each group of low output drivers 10 11 - 10 1n , 10 21 - 10 2n and 10 31 - 10 3n has a dedicated voltage regulator 210 , 220 and 230 , there is better isolation, lower noise and less external coupling.
  • the present invention comprises low power output driver that utilizes a reduced input voltage. It will be appreciated by those skilled in the art that changes could be made to the embodiments described above without departing from the broad inventive concept thereof. It is understood, therefore, that this invention is not limited to the particular embodiments disclosed, but it is intended to cover modifications within the spirit and scope of the present invention as defined by the appended claims.

Abstract

A low power output driver includes one of a regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage. The driver also includes a first driver input that receives a first logic signal, a second driver input that receives a second logic signal, a first driver output that outputs a first output signal and a second driver output that outputs a second output signal. The driver includes first, second, third and fourth n-type metal oxide semiconductor (NMOS) that are cross-connected between the reduced voltage and the first and second driver outputs or ground. When the second input is high, the second NMOS and the third NMOS are gated on, the second driver output is raised to the reduced voltage and the first driver output is pulled down to the internal ground.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application claims priority to U.S. Provisional Patent Application No. 60/612,700 filed on Sep. 24, 2004, entitled “Low Power Output Driver” and U.S. Provisional Patent Application No. 60/712,804 filed on Aug. 31, 2005 entitled “Low Power Output Driver.”
    • BACKGROUND OF THE INVENTION
  • The present invention relates generally to an output driver, and more particularly, to a low power output driver utilizing voltage lower than the supply voltage or rail voltage.
  • Integrated circuits which have output drivers for clock and data are known in the art. A typical prior art configuration is formed with two pairs of complementary metal oxide semiconductors (CMOS) such as the circuit depicted in FIG. 3 (e.g., an inverted CML). The CMOS can be either n-type or p-type devices. The configuration shown includes a p-type CMOS over an n-type CMOS for each CMOS pair. The n-type CMOS are not really doing anything active, as shown, but are provided for ESD protection. The supply voltage (VDD) or rail voltage is applied to the supply of the drivers and to the CMOS pairs. Each CMOS pair is connected to a pad. A series resistor RS is connected between each of the pads and a respective transmission line to “decouple” the output capacitance of the driver from the transmission line itself, i.e., it makes the impedance at the source of the transmission line more purely resistive. A termination resistor RT is connected between the junction of the series resistor RS and transmission line TL and ground to create a fixed impedance. Typically, a current mirror circuit is connected between the rail voltage and the high side of the CMOS pairs. The current mirror is driven or controlled by a reference current IREF. The power consumption of this prior art circuit is primarily determined by the current constantly being sourced through one or the other terminating resistors RT. The power can be calculated as P=V*I=VDD*(N*IREF). A typical current draw through the current mirror is on the order of 14-15 mA. With about 50 ohm terminating resistors RT, the resulting voltage drop across each terminating resistor RT is on the order of 750 millivolts (mV). Thus, the power draw, independent of the load condition, is about 50 milliwatts (mW). Since one CMOS pair or the other is always connected to one of the pads, power is constantly dissipated using the conventional circuit due to the bleeding current through the respective terminating resistor RT.
  • It is desirable to provide a driver output that utilizes a reduced voltage supply and has lower power consumption. It is also desirable to provide an on-chip reduced voltage power supply or regulator in combination with a plurality of low power output drivers.
    • BRIEF SUMMARY OF THE INVENTION
  • Briefly stated, the present invention comprises a low power output driver that includes one of a series-regulated and a switching-mode-regulated reduced voltage source. The reduced voltage source receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage. The driver also includes a first driver input that receives a first logic signal, a second driver input that receives a second logic signal, a first driver output that outputs a first output signal and a second driver output that outputs a second output signal. The driver includes first, second, third and fourth n-type metal oxide semiconductor (NMOS). The source and the drain of the first NMOS are electrically coupled between the reduced voltage VL and the first driver output. The gate of the first NMOS is electrically coupled to the first driver input. The source and the drain of the second NMOS are electrically coupled between the first driver output and an internal ground. The gate of the second NMOS is electrically coupled to the second driver input. The source and the drain of the third NMOS are electrically coupled between the reduced voltage VL and the second driver output. The gate of the third NMOS is electrically coupled to the second driver input. The source and the drain of the fourth NMOS are electrically coupled between the second driver output and the internal ground. The gate of the fourth NMOS is electrically coupled to the first driver input. When the first driver input is high and the second driver input is low, the first NMOS and the fourth NMOS are gated on, the first driver output is raised to the reduced voltage and the second driver output is pulled down to the internal ground. When the second input is high and the first driver input is low, the second NMOS and the third NMOS are gated on, the second driver output is raised to the reduced voltage and the first driver output is pulled down to the internal ground.
  • In another aspect, the present invention comprises a low power output driver system that includes a reference voltage supply VREF, a first voltage regulator that receives reference voltage supply VREF and outputs a first regulated reduced voltage VL1 that is a lower voltage than the reference voltage supply VREF and a second voltage regulator that receives reference voltage Supply VREF and outputs a second regulated reduced voltage VL2 that is a lower voltage than the reference voltage supply VREF. The system also includes a first low power output driver and a second low power output driver. Each of the first and second low power output drivers includes a first driver input that receives a first logic signal, a second driver input that receives a second logic signal, a first driver output that outputs a first output signal, and a second driver output that outputs a second output signal. Each of the first and second low power output drivers includes first, second, third and fourth n-type metal oxide semiconductor (NMOS) that each have a gate, a source and a drain. The source and the drain of the first NMOS are electrically coupled between the respective first and second reduced voltage VL1, VL2 and the first driver output. The gate of the first NMOS is electrically coupled to the first driver input. The source and the drain of the second NMOS are electrically coupled between the first driver output and an internal ground. The gate of the second NMOS is electrically coupled to the second driver input. The source and the drain of the third NMOS are electrically coupled between the respective first and second reduced voltage VL1, VL2 and the second driver output. The gate of the third NMOS is electrically coupled to the second driver input. The source and the drain of the fourth NMOS are electrically coupled between the second driver output and the internal ground. The gate of the second NMOS is electrically coupled to the first driver input.
    • BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
  • The foregoing summary, as well as the following detailed description of preferred embodiments of the invention, will be better understood when read in conjunction with the appended drawings. For the purpose of illustrating the invention, there are shown in the drawings embodiments which are presently preferred. It should be understood, however, that the invention is not limited to the precise arrangements and instrumentalities shown.
  • In the drawings:
  • FIG. 1 is an electrical schematic diagram of a low power output driver and reduced voltage power supply in accordance with a first preferred embodiment of the present invention;
  • FIG. 2 is an electrical schematic diagram of a low power output driver with an external reduced voltage supply in accordance with a second preferred embodiment of the present invention;
  • FIG. 3 is an electrical schematic diagram of prior art output driver;
  • FIGS. 4A-4B are electrical schematic diagrams of a low output power driver system in accordance with a third preferred embodiment of the present invention; and
  • FIG. 5 is an electrical schematic diagram of one possible detailed circuit implementation of a programmable current source.
    • DETAILED DESCRIPTION OF THE INVENTION
  • Certain terminology is used in the following description for convenience only and is not limiting. The words “right,” and “left,” “lower,” and “upper” designate directions in the drawings to which reference is made. The words “inwardly” and “outwardly” refer to directions toward and away from, respectively, the geometric center of the object discussed and designated parts thereof. The terminology includes the words above specifically mentioned, derivatives thereof and words of similar import. Additionally, the word “a” is used in the claims and in the corresponding portions of the Specification, means “at least one.”
  • Referring to the drawings in detail, wherein like reference numerals indicate like elements throughout, there is shown in FIG. 1 is an electrical schematic diagram of a low power output driver 10 and reduced voltage power supply 30 in accordance with a first preferred embodiment of the present invention. In the presently preferred embodiment, the reduced voltage power supply 30 is within the same integrated circuit (IC) (not shown) as the low power output driver 10. Preferably, one reduced voltage power supply 30 will supply a plurality of low power output drivers 10 all on the same IC (i.e., on the same chip). The reduced voltage power supply 30 is one of a series-regulated power supply and a switching-mode-regulated power supply.
  • The reduced voltage power supply 30 receives power from an external power source such as an supply voltage (VDD) (i.e., the rail voltage). As shown, an operational amplifier (op-amp) 130 receives an internal reference current on its non-inverting input and outputs a signal to a field effect transistor (FET) 132. The internal reference may be a bandgap reference, a resistance voltage divider, an external reference, an external bandgap and the like. The FET 132 then provides a reduced voltage output VL to a high-side of the low power output driver 10 and also as a feedback to the inverting input of op-amp 130. For example, a VDD of 3.3 volts may be controlled down to about 750 mV. Of course, other voltage reducing configurations may be utilized without departing from the present invention. For example the FET 132 may instead be a bipolar transistor and the like. An external capacitor CEXT is coupled between the feedback voltage and ground to reduce line-noise, ripple and the like. Alternately, the external capacitor CEXT can be formed internally without departing from the present invention.
  • The low power output driver 10 includes four n-type MOS (NMOS) 100, 102, 110, 112. The NMOS are configured in alternate pairs 100, 102 and 110, 112 that are coupled to PAD1 and PAD2, respectively. One NMOS 100 of the first pair 100, 102 is coupled between the reduced voltage source VL and the first pad PAD1 and the other NMOS 102 of the first pair 100, 102 is coupled between the first pad PAD1 and an internal ground. Likewise, one NMOS 110 of the second pair 110, 112 is coupled between the reduced voltage source VL and the second pad PAD2 and the other NMOS 112 of the second pair 110, 112 is coupled between the second pad PAD2 and an internal ground.
  • Whenever NMOS 100 is on, PAD1 is pulled up to the reduced voltage VL and NMOS 112 necessarily pulls PAD2 to ground (i.e., a cross-wire configuration). Similarly, whenever NMOS 110 is on, PAD2 is pulled up to the reduced voltage VL and NMOS 102 necessarily pulls PAD1 to ground. When a particular pad PAD1, PAD2 is pulled high, the reduced voltage VL, there is a current draw until the pad PAD1, PAD2 reaches a quiescent voltage with reduced voltage VL. But, there is not a continuous draw of current to ground as in the case of a system with terminating resistors.
  • Thus, the low power output driver 10 includes one of a series-regulated and a switching-mode-regulated reduced voltage source 30. There is a first supply voltage VDD1 that provides power for devices such as operational amplifiers 130 and the like. The first supply voltage VDD1 may be 1.2 VDC, 1.5 VDC, 3.3 VDC, 5 VDC or the like. The reduced voltage source 30 receives a second supply voltage VDD2 and outputs a regulated reduced voltage VL that is a lower voltage than the second supply voltage VDD2. The second supply voltage VDD2 may be the same as the first supply voltage VDD1, may be derived from the first supply voltage VDD1 or may be from a completely separate source. For example, the second supply voltage VDD2 may be derived from a linear or switching power supply (not shown) that receives the first supply voltage VDD1 and outputs a regulated voltage that is less than or greater than the first supply voltage VDD1. The driver 10 also includes a first driver input B that receives a first logic signal, a second driver input A that receives a second logic signal, a first driver output PAD1 that outputs a first output signal and a second driver output PAD2 that outputs a second output signal. The first and second driver inputs B, A may be applied through an amplifier, buffer or logic gate 120, 122, respectively. Supply power for the buffers 120, 122 is provided by a third supply voltage VDD3. The third supply voltage VDD3 may be the same as the first supply voltage VDD1, may be derived from the first supply voltage VDD1 or may be from a completely separate source. Preferably, the third supply voltage VDD3 is greater than the reduced voltage VL. The driver 10 includes first, second, third and fourth NMOS 100, 102, 110, and 112, respectively. The source and the drain of the first NMOS 100 are electrically coupled between the reduced voltage VL and the first driver output PAD1. The gate of the first NMOS 100 is electrically coupled to the first driver input B. The source and the drain of the second NMOS 102 are electrically coupled between the first driver output PAD1 and an internal ground. The gate of the second NMOS 102 is electrically coupled to the second driver input A. The source and the drain of the third NMOS 110 are electrically coupled between the reduced voltage VL and the second driver output A. The gate of the third NMOS 110 is electrically coupled to the second driver input A. The source and the drain of the fourth NMOS 112 are electrically coupled between the second driver output A and the internal ground. The gate of the fourth NMOS 112 is electrically coupled to the first driver input B. When the first driver input B is high and the second driver input A is low, the first NMOS 100 and the fourth NMOS 110 are gated on, the first driver output PAD1 is raised to the reduced voltage VL and the second driver output PAD2 is pulled down to the internal ground. When the second driver input A is high and the first driver input B is low, the second NMOS 102 and the third NMOS 110 are gated on, the second driver output PAD2 is raised to the reduced voltage VL and the first driver output PAD1 is pulled down to the internal ground.
  • The first and second pads PAD1, PAD2 are typically coupled to transmission lines TL through series resistors RS. The series resistance RS may be internal (before the pads PAD1, PAD2) or external (after the pads PAD1, PAD2). The series resistance RS may simply be the load of the wire depending on the application. The series resistance RS are normally used to increase the total impedance of the driver circuit 10, including the transistor resistance plus the series resistance RS to match the impedance of the transmission lines TL1, TL2.
  • Driver inputs A and B may be clocks or data and the like. Each driver input A, B is connected to an NMOS pair 100, 102 or 110, 112.
  • FIG. 2 is an electrical schematic diagram of a low power output driver 10′ with an external reduced voltage supply EXTERNAL VL in accordance with a second preferred embodiment of the present invention. The low power output driver 10′ is substantially similar in functionality to that described above. The external reduced voltage supply EXTERNAL VL is from any reduced voltage source that is external to the driver IC such as an external series-regulated power supply or an external switching-mode-regulated power supply.
  • The resulting power consumption for the depicted system in FIG. 2 is:
    P=V L *I AVERAGE =V L 2 *C L *f  (Eq. 1)
      • where f is operating frequency.
        For a reduced voltage of 0.75 volts and a VDD2 of 3.3 volts, there is enough “enhancement” to pull the output pads PAD1, PAD2 to the reduced voltage of VL.
  • An advantage of the present invention over a PMOS-NMOS (i.e., a complementary MOS pair or CMOS) output is that, although NMOS can be driven by 3.3 volts, PMOS would see only −0.7 volts, assuming that its gates cannot be driven below ground, which would result in minimal enhancement or possibly none at all. Therefore, an NMOS-NMOS with reduced voltage supply VL is more stable and makes reduced power consumption possible.
  • FIGS. 4A-4B show a low output power driver system 200 in accordance with a third preferred embodiment of the present invention. The low power output driver system 200 includes a reference voltage supply VREF, a first programmable current source 214, a second programmable current source 224 and a third programmable current source 234. The first programmable current source 214 receives the reference supply voltage VREF and outputs a first reference voltage VREF1. The second programmable current source 224 receives the reference supply voltage VREF and outputs a second reference voltage VREF2. The third programmable current source 234 receives the reference supply voltage VREF and outputs a third reference voltage VREF3. Each of the first, second and third programmable current sources 214, 224, 234 may have suitable bias components associated therewith such as resistors R213, R223 and R233, respectively. The first, second and third programmable current sources 214, 224, 234 may include a simple resistor divider network and switch, amplifiers, transistors or the like.
  • FIG. 5 shows one possible detailed circuit implementation of the first, second and third programmable current sources 214, 224, 234. Each of the programmable current sources 214, 224, 234 include an op-amp 252, a pass transistor T254, a drive transistor T256, a first selectable source transistor T261, a second selectable source transistor T262, a third selectable source transistor T263, a fourth selectable source transistor T264 and four switches 271-274. The op-amp 252 receives the reference supply voltage VREF and the output of the op-amp 252 drives the gate of the pass transistor T254. The op-amp 252 is configured as a buffer, but the op-amp 252 could be configured as an amplifier with the addition of feedback resistors. The drive transistor T256 is coupled to the pass transistor T256 and provides source and gate voltage to each of the first-fourth selectable source transistors T261-T264. The switches 271-274 are connected between the first-fourth selectable source transistors T261-T264 and an output node 258. The first, second or third reference voltage VREF1-VREF3 is output from the output node 258. The switches 271-274 can be controlled by external binary signals or can be programmed during manufacturing by jumpers or opening circuit paths, for example. Other detailed circuit implementation of the first, second and third programmable current sources 214, 224, 234 can be utilized without departing from the present invention.
  • Referring again to FIGS. 4A-4B, the low power output driver system 200 also includes a first voltage regulator 210 that receives reference voltage supply VREF1 and outputs a first regulated voltage VL1 that is derived from the reference voltage supply VREF1, a second voltage regulator 220 that receives reference voltage supply VREF2 and outputs a second regulated voltage VL2 that is derived from the reference voltage supply VREF2 and a third voltage regulator 230 that receives reference voltage supply VREF3 and outputs a third regulated voltage VL3 that is derived from the reference voltage supply VREF3. The first, second and third regulated voltages VL1, VL2, VL3 can be reduced, amplified or the same as the reference supply voltage VREF. Optionally, only the first programmable current source 214 provides the first reference voltage VREF1 to each of the first, second and third voltage regulators 210, 220, 230. Optionally, the reference supply voltage VREF is provided directly to each of the first, second and third voltage regulators 210, 220, 230.
  • There can be any number of additional voltage regulators 210, 220, 230 as a design requires. Preferably, the plurality of voltage regulators 210, 220, 230 are provided on a single integrated circuit (IC) chip (on-chip voltage power supply or regulator).
  • Preferably, the voltage regulators 210, 220, 230 are configured to accept a relatively wide range of input voltage Vin while still outputting approximately the same desired regulated voltage VL1, VL2, VL3. The first, second and third regulated reduced voltages VL1, VL2, VL3 may be the same or different voltage potentials depending on the application.
  • The low power output driver system 200 also includes first low power output driver 10 11, a second low power output driver 10 21 and a third low power output driver 10 31. Each of the first, second and third low power output drivers 10 11, 10 21, 10 31 includes a low output driver circuit 10, 10′ as described above with respect to the first preferred embodiment.
  • Preferably, the low power output driver system 200 includes a plurality of low output drivers 10 11-10 1n, 10 21-10 2n, 10 31-10 3n and each set of low output drivers 10 11-10 1n, 10 21-10 2n and 10 31-10 3n is connected to a separate voltage regulator 210, 220 and 230, respectively. Since each group of low output drivers 10 11-10 1n, 10 21-10 2n and 10 31-10 3n has a dedicated voltage regulator 210, 220 and 230, there is better isolation, lower noise and less external coupling.
  • From the foregoing, it can be seen that the present invention comprises low power output driver that utilizes a reduced input voltage. It will be appreciated by those skilled in the art that changes could be made to the embodiments described above without departing from the broad inventive concept thereof. It is understood, therefore, that this invention is not limited to the particular embodiments disclosed, but it is intended to cover modifications within the spirit and scope of the present invention as defined by the appended claims.

Claims (19)

1. A low power output driver comprising:
(a) one of a series-regulated and a switching-mode-regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage;
(b) a first driver input that receives a first logic signal;
(c) a second driver input that receives a second logic signal;
(d) a first driver output that outputs a first output signal;
(e) a second driver output that outputs a second output signal;
(f) a first n-type metal oxide semiconductor (NMOS) having a gate, a source and a drain, the source and the drain of the first NMOS being electrically coupled between the reduced voltage VL and the first driver output, the gate of the first NMOS being electrically coupled to the first driver input;
(g) a second NMOS having a gate, a source and a drain, the source and the drain of the second NMOS being electrically coupled between the first driver output and an internal ground, the gate of the second NMOS being electrically coupled to the second driver input;
(h) a third NMOS having a gate, a source and a drain, the source and the drain of the third CMOS being electrically coupled between the reduced voltage VL and the second driver output, the gate of the third NMOS being electrically coupled to the second driver input; and
(i) a fourth NMOS having a gate, a source and a drain, the source and the drain of the fourth NMOS being electrically coupled between the second driver output and the internal ground, the gate of the fourth NMOS being electrically coupled to the first driver input,
when the first driver input is high and the second driver input is low, the first NMOS and the fourth NMOS are gated on, the first driver output is raised to the reduced voltage and the second driver output is pulled down to the internal ground, and
when the second input is high and the first driver input is low, the second NMOS and the third NMOS are gated on, the second driver output is raised to the reduced voltage and the first driver output is pulled down to the internal ground.
2. The low power output driver of claim 1, wherein the regulated reduced voltage source includes:
(a1) a voltage source input that receives the supply voltage VDD; and
(a2) a voltage source output that outputs the regulated reduced voltage VL.
3. The low power output driver of claim 2, wherein the regulated reduced voltage source further includes:
(a3) a voltage source MOS having a gate, a source and a drain, the source and the drain of the voltage source MOS being electrically coupled between the voltage source input and voltage source output; and
(a4) an operational amplifier having a non-inverting input, an inverting input and an amplifier output, the non-inverting input being electrically coupled to an internal reference, the inverting input being electrically coupled to the voltage source output and the amplifier output being electrically coupled to the gate of the voltage source NMOS.
4. The low power output driver of claim 2, wherein the regulated reduced voltage source further includes:
(a3) a voltage source bipolar transistor, the voltage source bipolar transistor being electrically coupled between the voltage source input and voltage source output; and
(a4) an operational amplifier having a non-inverting input, an inverting input and an amplifier output, the non-inverting input being electrically coupled to an internal reference, the inverting input being electrically coupled to the voltage source output and the amplifier output being electrically coupled to the gate of the voltage source NMOS.
5. The low power output driver of claim 2, wherein the inverting input of the operational amplifier is capacitively coupled to the internal ground.
6. The low power output driver of claim 2, wherein the internal reference includes one of a bandgap reference, a resistance voltage divider, an external reference and an external bandgap.
7. The low power output driver of claim 1, wherein the supply voltage is between about 1.0 and about 6.0 volts direct current (VDC) and the reduced voltage is between about 0.1 and about 1.5 VDC.
8. The low power output driver of claim 1, wherein the supply voltage is about 3.3 volts direct current (VDC) and the reduced voltage is about 0.75 VDC.
9. The low power output driver of claim 1, wherein the reduced voltage source and the first, second, third and fourth NMOS are disposed in a common integrated circuit (IC).
10. The low power output driver of claim 1, wherein the first, second, third and fourth NMOS are disposed in a common integrated circuit (IC) and the reduced voltage source is disposed external to the IC.
11. The low power output driver of claim 1, wherein the first and second driver outputs form a voltage source.
12. The low power output driver of claim 1, wherein the first logic signal and the second logic signal are complementary.
13. A low power output driver system comprising:
(a) a reference voltage supply;
(b) a first voltage regulator that receives reference voltage supply and outputs a first regulated voltage;
(c) a second voltage regulator that receives reference voltage supply and outputs a second regulated voltage;
(d) a first low power output driver; and
(e) a second low power output driver,
each of the first and second low power output drivers including:
(i) a first driver input that receives a first logic signal;
(ii) a second driver input that receives a second logic signal;
(iii) a first driver output that outputs a first output signal;
(iv) a second driver output that outputs a second output signal;
(v) a first n-type metal oxide semiconductor (NMOS) having a gate, a source and a drain, the source and the drain of the first NMOS being electrically coupled between the respective first and second regulated voltage and the first driver output, the gate of the first NMOS being electrically coupled to the first driver input;
(vi) a second NMOS having a gate, a source and a drain, the source and the drain of the second NMOS being electrically coupled between the first driver output and an internal ground, the gate of the second NMOS being electrically coupled to the second driver input;
(vii) a third NMOS having a gate, a source and a drain, the source and the drain of the third CMOS being electrically coupled between the respective first and second regulated voltage and the second driver output, the gate of the third NMOS being electrically coupled to the second driver input; and
(viii) a fourth NMOS having a gate, a source and a drain, the source and the drain of the fourth NMOS being electrically coupled between the second driver output and the internal ground, the gate of the fourth NMOS being electrically coupled to the first driver input.
14. The low power output driver system of claim 13, further comprising:
(f) a third voltage regulator that receives reference voltage supply and outputs a third regulated voltage;
(g) a third low power output driver, the third low power output driver including:
(i) a first driver input that receives the first logic signal;
(ii) a second driver input that receives the second logic signal;
(iii) a first driver output that outputs a first output signal;
(iv) a second driver output that outputs a second output signal;
(v) a first n-type metal oxide semiconductor (NMOS) having a gate, a source and a drain, the source and the drain of the first NMOS being electrically coupled between the third regulated voltage and the first driver output, the gate of the first NMOS being electrically coupled to the first driver input;
(vi) a second NMOS having a gate, a source and a drain, the source and the drain of the second NMOS being electrically coupled between the first driver output and an internal ground, the gate of the second NMOS being electrically coupled to the second driver input;
(vii) a third NMOS having a gate, a source and a drain, the source and the drain of the third CMOS being electrically coupled between the third regulated voltage and the second driver output, the gate of the third NMOS being electrically coupled to the second driver input; and
(viii) a fourth NMOS having a gate, a source and a drain, the source and the drain of the fourth NMOS being electrically coupled between the second driver output and the internal ground, the gate of the fourth NMOS being electrically coupled to the first driver input.
15. The low power output driver system of claim 14, wherein the first, second and third regulated voltages are different voltage potentials.
16. The low power output driver system of claim 14, wherein at least two of the first, second and third regulated voltages are approximately the same voltage potential.
17. The low power output driver system of claim 13, wherein the first and second regulated voltages are different voltage potentials.
18. The low power output driver system of claim 13, wherein the first and second regulated voltages are approximately the same voltage potential.
19. The low power output driver system of claim 13, further comprising:
a plurality of low power output drivers coupled to the first voltage regulator; and
a plurality of low power output drivers coupled to the second voltage regulator.
US11/234,911 2004-09-24 2005-09-26 Low power output driver Active 2025-10-20 US7342420B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US11/234,911 US7342420B2 (en) 2004-09-24 2005-09-26 Low power output driver
US11/931,191 US7821297B2 (en) 2004-09-24 2007-10-31 Low power output driver
US12/342,160 US7830177B2 (en) 2004-09-24 2008-12-23 Low power output driver

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US61270004P 2004-09-24 2004-09-24
US71280405P 2005-08-31 2005-08-31
US11/234,911 US7342420B2 (en) 2004-09-24 2005-09-26 Low power output driver

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/931,191 Continuation US7821297B2 (en) 2004-09-24 2007-10-31 Low power output driver

Publications (2)

Publication Number Publication Date
US20060066354A1 true US20060066354A1 (en) 2006-03-30
US7342420B2 US7342420B2 (en) 2008-03-11

Family

ID=36098322

Family Applications (3)

Application Number Title Priority Date Filing Date
US11/234,911 Active 2025-10-20 US7342420B2 (en) 2004-09-24 2005-09-26 Low power output driver
US11/931,191 Active US7821297B2 (en) 2004-09-24 2007-10-31 Low power output driver
US12/342,160 Active US7830177B2 (en) 2004-09-24 2008-12-23 Low power output driver

Family Applications After (2)

Application Number Title Priority Date Filing Date
US11/931,191 Active US7821297B2 (en) 2004-09-24 2007-10-31 Low power output driver
US12/342,160 Active US7830177B2 (en) 2004-09-24 2008-12-23 Low power output driver

Country Status (1)

Country Link
US (3) US7342420B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9407268B1 (en) 2015-04-29 2016-08-02 Integrated Device Technology, Inc. Low voltage differential signaling (LVDS) driver with differential output signal amplitude regulation
US9419588B1 (en) 2015-02-21 2016-08-16 Integrated Device Technology, Inc. Output driver having output impedance adaptable to supply voltage and method of use
US9490805B2 (en) 2014-09-02 2016-11-08 Integrated Device Technology, Inc. Low power driver with programmable output impedance
JP2021176216A (en) * 2020-05-01 2021-11-04 インターチップ株式会社 Driver in lphcsl transmission system

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7342420B2 (en) * 2004-09-24 2008-03-11 Integrated Device Technology, Inc. Low power output driver
US7711939B2 (en) * 2005-06-30 2010-05-04 Intel Corporation Serial link apparatus, method, and system
US20080218292A1 (en) * 2007-03-08 2008-09-11 Dong-Uk Park Low voltage data transmitting circuit and associated methods
KR100915830B1 (en) * 2008-03-12 2009-09-07 주식회사 하이닉스반도체 Semiconductor integrated circuit
US8022730B2 (en) * 2009-10-13 2011-09-20 Himax Technologies Limited Driving circuit with slew-rate enhancement circuit
KR20120050262A (en) 2010-11-10 2012-05-18 삼성전자주식회사 Source follower type of transmitter and control method of driving voltage therefrom
US8639193B2 (en) * 2011-12-29 2014-01-28 Qualcomm Incorporated Tri-state control for a line driver
US20140312928A1 (en) * 2013-04-19 2014-10-23 Kool Chip, Inc. High-Speed Current Steering Logic Output Buffer
US9838016B1 (en) * 2016-02-23 2017-12-05 Integrated Device Technology, Inc. Adaptive high-speed current-steering logic (HCSL) drivers

Citations (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3495223A (en) * 1967-07-28 1970-02-10 Gen Electric Read/write circuit for use with a magnetic memory
US4084070A (en) * 1977-01-21 1978-04-11 Rca Corporation Overcurrent protection circuit
US4556805A (en) * 1982-09-07 1985-12-03 Nec Corporation Comparator circuit having hysteresis voltage substantially independent of variation in power supply voltage
US4775844A (en) * 1987-10-13 1988-10-04 William Snyder Bridge amplifier topology
US4791314A (en) * 1986-11-13 1988-12-13 Fairchild Semiconductor Corporation Oscillation-free, short-circuit protection circuit
US4845386A (en) * 1987-02-06 1989-07-04 Kabushiki Kaisha Toshiba Bi-MOS logic circuit having a totem pole type output buffer section
US4884165A (en) * 1988-11-18 1989-11-28 Advanced Micro Devices, Inc. Differential line driver with short circuit protection
US4987318A (en) * 1989-09-18 1991-01-22 International Business Machines Corporation High level clamp driver for wire-or buses
US5083051A (en) * 1990-02-26 1992-01-21 Motorola, Inc. Output driver circuit with improved output stage biasing
US5281869A (en) * 1992-07-01 1994-01-25 Digital Equipment Corporation Reduced-voltage NMOS output driver
US5404051A (en) * 1992-03-12 1995-04-04 Texas Instruments Incorporated Totem-pole load driving circuit with potential rise characteristics control
US5424683A (en) * 1993-03-29 1995-06-13 Sanyo Electric Co., Ltd. Differential amplification circuit wherein a DC level at an output terminal is automatically adjusted and a power amplifier wherein a BTL drive circuit is driven by a half wave
US5444410A (en) * 1993-06-30 1995-08-22 National Semiconductor Corporation Controlled-transitioni-time line driver
US5444446A (en) * 1993-07-01 1995-08-22 Texas Instruments Incorporated Apparatus and method for duplicating currents
US5519728A (en) * 1993-04-15 1996-05-21 National Semiconductor Corporation High-speed low-voltage differential swing transmission line transceiver
US5530271A (en) * 1993-12-13 1996-06-25 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno Integrated structure active clamp for the protection of power semiconductor devices against overvoltages
US5576634A (en) * 1994-10-31 1996-11-19 Nec Corporation Bus driver for high-speed data transmission with waveform adjusting means
US5604417A (en) * 1991-12-19 1997-02-18 Hitachi, Ltd. Semiconductor integrated circuit device
US5632019A (en) * 1994-07-15 1997-05-20 Seagate Technology, Inc. Output buffer with digitally controlled power handling characteristics
US5721504A (en) * 1995-04-21 1998-02-24 Mitsubishi Denki Kabushiki Kaisha Clamping semiconductor circuit
US5767698A (en) * 1996-06-06 1998-06-16 International Business Machines Corporation High speed differential output driver with common reference
US5812021A (en) * 1996-01-26 1998-09-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit device having an internal power supply circuit capable of stably maintaining output level against load fluctuation
US5880599A (en) * 1996-12-11 1999-03-09 Lsi Logic Corporation On/off control for a balanced differential current mode driver
US5939931A (en) * 1996-11-29 1999-08-17 Yamaha Corporation Driving circuit having differential and H-bridge circuits for low voltage power source
US5977796A (en) * 1997-06-26 1999-11-02 Lucent Technologies, Inc. Low voltage differential swing interconnect buffer circuit
US6005438A (en) * 1997-12-10 1999-12-21 National Semiconductor Corporation Output high voltage clamped circuit for low voltage differential swing applications in the case of overload
US6028467A (en) * 1996-11-12 2000-02-22 Lsi Logic Corporation Differential output circuit
US6054874A (en) * 1997-07-02 2000-04-25 Cypress Semiconductor Corp. Output driver circuit with switched current source
US6111431A (en) * 1998-05-14 2000-08-29 National Semiconductor Corporation LVDS driver for backplane applications
US6118302A (en) * 1996-05-28 2000-09-12 Altera Corporation Interface for low-voltage semiconductor devices
US6191994B1 (en) * 1997-08-27 2001-02-20 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US6218884B1 (en) * 2000-03-02 2001-04-17 National Semiconductor Corp. Cancellation of Ron resistance for switching transistor in LVDS driver output
US6232815B1 (en) * 1999-05-06 2001-05-15 Analog Devices, Inc. ATE pin electronics with complementary waveform drivers
US6252435B1 (en) * 2000-10-05 2001-06-26 Pericom Semiconductor Corp. Complementary differential amplifier with resistive loads for wide common-mode input range
US6275107B1 (en) * 1998-10-29 2001-08-14 Fujitisu Limited Differential amplifier circuit and pull up-type differential driver
US6281715B1 (en) * 1998-04-29 2001-08-28 National Semiconductor Corporation Low voltage differential signaling driver with pre-emphasis circuit
US6414518B1 (en) * 1996-05-28 2002-07-02 Altera Corporation Circuitry for a low internal voltage integrated circuit
US6429696B1 (en) * 2000-02-08 2002-08-06 Cheng-Yung Kao Peak hold and calibration circuit
US6437599B1 (en) * 2000-11-06 2002-08-20 Xilinx, Inc. Programmable line driver
US20020120878A1 (en) * 2001-02-28 2002-08-29 Lapidus Peter D. Integrated circuit having programmable voltage level line drivers and method of operation
US6448815B1 (en) * 2000-10-30 2002-09-10 Api Networks, Inc. Low voltage differential receiver/transmitter and calibration method thereof
US20020135404A1 (en) * 2001-03-21 2002-09-26 Payne Robert F. High speed voltage mode differential digital output driver with edge-emphasis and pre-equalization
US20020190770A1 (en) * 1999-06-28 2002-12-19 Broadcom Corporation Current -controlled CMOS circuit using higher voltage supply in low voltage CMOS process
US6545531B1 (en) * 2001-09-20 2003-04-08 Hynix Semiconductor Inc. Power voltage driver circuit for low power operation mode
US6552581B1 (en) * 2000-08-25 2003-04-22 Agere Systems Inc. Current recycling circuit and a method of current recycling
US6590422B1 (en) * 2002-03-27 2003-07-08 Analog Devices, Inc. Low voltage differential signaling (LVDS) drivers and systems
US20030146792A1 (en) * 2000-08-11 2003-08-07 Udo Ausserlechner Two-stage operational amplifier
US6617888B2 (en) * 2002-01-02 2003-09-09 Intel Corporation Low supply voltage differential signal driver
US6683445B2 (en) * 2001-06-29 2004-01-27 Hynix Semiconductor Inc. Internal power voltage generator
US6686772B2 (en) * 2001-11-19 2004-02-03 Broadcom Corporation Voltage mode differential driver and method
US20040145361A1 (en) * 2003-01-28 2004-07-29 Owen William H. Output voltage compensating circuit and method for a floating gate reference voltage generator
US6992508B2 (en) * 2002-04-12 2006-01-31 Stmicroelectronics, Inc. Versatile RSDS-LVDS-miniLVDS-BLVDS differential signal interface circuit
US7012450B1 (en) * 2003-12-15 2006-03-14 Decicon, Inc. Transmitter for low voltage differential signaling
US7129756B2 (en) * 2001-12-07 2006-10-31 Thine Electronics, Inc. Semiconductor integrated circuit

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6294947B1 (en) * 1998-05-29 2001-09-25 Agere Systems Guradian Corp. Asymmetrical current steering output driver with compact dimensions
US6198307B1 (en) * 1998-10-26 2001-03-06 Rambus Inc. Output driver circuit with well-controlled output impedance
US6262620B1 (en) * 1999-11-02 2001-07-17 Ranco Incorporated Of Delaware Driver circuitry for latching type valve and the like
US6696852B1 (en) * 2000-07-25 2004-02-24 Artisan Components, Inc. Low-voltage differential I/O device
US6570415B2 (en) * 2001-06-06 2003-05-27 Texas Instruments Incorporated Reduced voltage swing digital differential driver
US6731135B2 (en) * 2001-06-14 2004-05-04 Artisan Components, Inc. Low voltage differential signaling circuit with mid-point bias
US6552582B1 (en) * 2001-09-27 2003-04-22 Applied Micro Circuits Corporation Source follower for low voltage differential signaling
US6847232B2 (en) * 2001-11-08 2005-01-25 Texas Instruments Incorporated Interchangeable CML/LVDS data transmission circuit
US6700403B1 (en) * 2002-05-15 2004-03-02 Analog Devices, Inc. Data driver systems with programmable modes
US6897699B1 (en) * 2002-07-19 2005-05-24 Rambus Inc. Clock distribution network with process, supply-voltage, and temperature compensation
US7336780B2 (en) * 2002-08-01 2008-02-26 Integrated Device Technology, Inc. Differential signaling transmission circuit
US6900663B1 (en) * 2002-11-04 2005-05-31 Cypress Semiconductor Corporation Low voltage differential signal driver circuit and method
US7145359B2 (en) * 2004-06-28 2006-12-05 Silicon Laboratories Inc. Multiple signal format output buffer
US7342420B2 (en) * 2004-09-24 2008-03-11 Integrated Device Technology, Inc. Low power output driver
US7215173B2 (en) * 2005-01-31 2007-05-08 Intel Corporation Low-swing level shifter
US7358772B1 (en) * 2005-02-28 2008-04-15 Silego Technology, Inc. Reduced power output buffer
US7248079B2 (en) * 2005-11-23 2007-07-24 Agere Systems Inc. Differential buffer circuit with reduced output common mode variation

Patent Citations (63)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3495223A (en) * 1967-07-28 1970-02-10 Gen Electric Read/write circuit for use with a magnetic memory
US4084070A (en) * 1977-01-21 1978-04-11 Rca Corporation Overcurrent protection circuit
US4556805A (en) * 1982-09-07 1985-12-03 Nec Corporation Comparator circuit having hysteresis voltage substantially independent of variation in power supply voltage
US4791314A (en) * 1986-11-13 1988-12-13 Fairchild Semiconductor Corporation Oscillation-free, short-circuit protection circuit
US4845386A (en) * 1987-02-06 1989-07-04 Kabushiki Kaisha Toshiba Bi-MOS logic circuit having a totem pole type output buffer section
US4775844A (en) * 1987-10-13 1988-10-04 William Snyder Bridge amplifier topology
US4884165A (en) * 1988-11-18 1989-11-28 Advanced Micro Devices, Inc. Differential line driver with short circuit protection
US4987318A (en) * 1989-09-18 1991-01-22 International Business Machines Corporation High level clamp driver for wire-or buses
US5083051A (en) * 1990-02-26 1992-01-21 Motorola, Inc. Output driver circuit with improved output stage biasing
US5604417A (en) * 1991-12-19 1997-02-18 Hitachi, Ltd. Semiconductor integrated circuit device
US5614848A (en) * 1991-12-19 1997-03-25 Hitachi, Ltd. High-speed semiconductor integrated circuit device composed of CMOS and bipolar transistors
US5404051A (en) * 1992-03-12 1995-04-04 Texas Instruments Incorporated Totem-pole load driving circuit with potential rise characteristics control
US5281869A (en) * 1992-07-01 1994-01-25 Digital Equipment Corporation Reduced-voltage NMOS output driver
US5424683A (en) * 1993-03-29 1995-06-13 Sanyo Electric Co., Ltd. Differential amplification circuit wherein a DC level at an output terminal is automatically adjusted and a power amplifier wherein a BTL drive circuit is driven by a half wave
US5519728A (en) * 1993-04-15 1996-05-21 National Semiconductor Corporation High-speed low-voltage differential swing transmission line transceiver
US5444410A (en) * 1993-06-30 1995-08-22 National Semiconductor Corporation Controlled-transitioni-time line driver
US5444446A (en) * 1993-07-01 1995-08-22 Texas Instruments Incorporated Apparatus and method for duplicating currents
US5530271A (en) * 1993-12-13 1996-06-25 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno Integrated structure active clamp for the protection of power semiconductor devices against overvoltages
US5632019A (en) * 1994-07-15 1997-05-20 Seagate Technology, Inc. Output buffer with digitally controlled power handling characteristics
US5576634A (en) * 1994-10-31 1996-11-19 Nec Corporation Bus driver for high-speed data transmission with waveform adjusting means
US5721504A (en) * 1995-04-21 1998-02-24 Mitsubishi Denki Kabushiki Kaisha Clamping semiconductor circuit
US5812021A (en) * 1996-01-26 1998-09-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit device having an internal power supply circuit capable of stably maintaining output level against load fluctuation
US20030117174A1 (en) * 1996-05-28 2003-06-26 Altera Corporation, A Corporation Of Delaware Programmable logic with lower internal voltage circuitry
US6724222B2 (en) * 1996-05-28 2004-04-20 Altera Corporation Programmable logic with lower internal voltage circuitry
US6118302A (en) * 1996-05-28 2000-09-12 Altera Corporation Interface for low-voltage semiconductor devices
US6342794B1 (en) * 1996-05-28 2002-01-29 Altera Corporation Interface for low-voltage semiconductor devices
US6414518B1 (en) * 1996-05-28 2002-07-02 Altera Corporation Circuitry for a low internal voltage integrated circuit
US6344758B1 (en) * 1996-05-28 2002-02-05 Altera Corporation Interface for low-voltage semiconductor devices
US5767698A (en) * 1996-06-06 1998-06-16 International Business Machines Corporation High speed differential output driver with common reference
US6028467A (en) * 1996-11-12 2000-02-22 Lsi Logic Corporation Differential output circuit
US5939931A (en) * 1996-11-29 1999-08-17 Yamaha Corporation Driving circuit having differential and H-bridge circuits for low voltage power source
US5880599A (en) * 1996-12-11 1999-03-09 Lsi Logic Corporation On/off control for a balanced differential current mode driver
US5977796A (en) * 1997-06-26 1999-11-02 Lucent Technologies, Inc. Low voltage differential swing interconnect buffer circuit
US6054874A (en) * 1997-07-02 2000-04-25 Cypress Semiconductor Corp. Output driver circuit with switched current source
US6191994B1 (en) * 1997-08-27 2001-02-20 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US20010000309A1 (en) * 1997-08-27 2001-04-19 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US6385124B2 (en) * 1997-08-27 2002-05-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor device including a memory cell array
US6005438A (en) * 1997-12-10 1999-12-21 National Semiconductor Corporation Output high voltage clamped circuit for low voltage differential swing applications in the case of overload
US6281715B1 (en) * 1998-04-29 2001-08-28 National Semiconductor Corporation Low voltage differential signaling driver with pre-emphasis circuit
US6111431A (en) * 1998-05-14 2000-08-29 National Semiconductor Corporation LVDS driver for backplane applications
US6275107B1 (en) * 1998-10-29 2001-08-14 Fujitisu Limited Differential amplifier circuit and pull up-type differential driver
US6232815B1 (en) * 1999-05-06 2001-05-15 Analog Devices, Inc. ATE pin electronics with complementary waveform drivers
US20020190770A1 (en) * 1999-06-28 2002-12-19 Broadcom Corporation Current -controlled CMOS circuit using higher voltage supply in low voltage CMOS process
US6429696B1 (en) * 2000-02-08 2002-08-06 Cheng-Yung Kao Peak hold and calibration circuit
US6218884B1 (en) * 2000-03-02 2001-04-17 National Semiconductor Corp. Cancellation of Ron resistance for switching transistor in LVDS driver output
US20030146792A1 (en) * 2000-08-11 2003-08-07 Udo Ausserlechner Two-stage operational amplifier
US6552581B1 (en) * 2000-08-25 2003-04-22 Agere Systems Inc. Current recycling circuit and a method of current recycling
US6252435B1 (en) * 2000-10-05 2001-06-26 Pericom Semiconductor Corp. Complementary differential amplifier with resistive loads for wide common-mode input range
US6448815B1 (en) * 2000-10-30 2002-09-10 Api Networks, Inc. Low voltage differential receiver/transmitter and calibration method thereof
US6437599B1 (en) * 2000-11-06 2002-08-20 Xilinx, Inc. Programmable line driver
US20020120878A1 (en) * 2001-02-28 2002-08-29 Lapidus Peter D. Integrated circuit having programmable voltage level line drivers and method of operation
US20020135404A1 (en) * 2001-03-21 2002-09-26 Payne Robert F. High speed voltage mode differential digital output driver with edge-emphasis and pre-equalization
US6624670B2 (en) * 2001-03-21 2003-09-23 Texas Instruments Incorporated High speed voltage mode differential digital output driver with edge-emphasis and pre-equalization
US6683445B2 (en) * 2001-06-29 2004-01-27 Hynix Semiconductor Inc. Internal power voltage generator
US6545531B1 (en) * 2001-09-20 2003-04-08 Hynix Semiconductor Inc. Power voltage driver circuit for low power operation mode
US20040150430A1 (en) * 2001-11-19 2004-08-05 Broadcom Corporation Voltage mode differential driver and method
US6686772B2 (en) * 2001-11-19 2004-02-03 Broadcom Corporation Voltage mode differential driver and method
US7129756B2 (en) * 2001-12-07 2006-10-31 Thine Electronics, Inc. Semiconductor integrated circuit
US6617888B2 (en) * 2002-01-02 2003-09-09 Intel Corporation Low supply voltage differential signal driver
US6590422B1 (en) * 2002-03-27 2003-07-08 Analog Devices, Inc. Low voltage differential signaling (LVDS) drivers and systems
US6992508B2 (en) * 2002-04-12 2006-01-31 Stmicroelectronics, Inc. Versatile RSDS-LVDS-miniLVDS-BLVDS differential signal interface circuit
US20040145361A1 (en) * 2003-01-28 2004-07-29 Owen William H. Output voltage compensating circuit and method for a floating gate reference voltage generator
US7012450B1 (en) * 2003-12-15 2006-03-14 Decicon, Inc. Transmitter for low voltage differential signaling

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9490805B2 (en) 2014-09-02 2016-11-08 Integrated Device Technology, Inc. Low power driver with programmable output impedance
US9419588B1 (en) 2015-02-21 2016-08-16 Integrated Device Technology, Inc. Output driver having output impedance adaptable to supply voltage and method of use
US9407268B1 (en) 2015-04-29 2016-08-02 Integrated Device Technology, Inc. Low voltage differential signaling (LVDS) driver with differential output signal amplitude regulation
JP2021176216A (en) * 2020-05-01 2021-11-04 インターチップ株式会社 Driver in lphcsl transmission system
JP7043541B2 (en) 2020-05-01 2022-03-29 インターチップ株式会社 Driver in LPHCSL transmission method

Also Published As

Publication number Publication date
US20090102513A1 (en) 2009-04-23
US7830177B2 (en) 2010-11-09
US7821297B2 (en) 2010-10-26
US20080048724A1 (en) 2008-02-28
US7342420B2 (en) 2008-03-11

Similar Documents

Publication Publication Date Title
US7342420B2 (en) Low power output driver
US6686772B2 (en) Voltage mode differential driver and method
JP2848500B2 (en) Interface system
US8395870B2 (en) Input/output circuit
US5537059A (en) Output circuit of semiconductor integrated circuit device
JP2003235245A (en) Negative voltage output charge pump circuit
JP3182035B2 (en) Automatic control of buffer speed
US6621329B2 (en) Semiconductor device
JP4955021B2 (en) Electronic device and integrated circuit
US6327190B1 (en) Complementary differential input buffer for a semiconductor memory device
JP4920398B2 (en) Voltage generation circuit
US7180331B2 (en) Voltage tolerant structure for I/O cells
JP2748865B2 (en) Output circuit
US6900688B2 (en) Switch circuit
JPH02125523A (en) Ecl-cmos converter
US20090284287A1 (en) Output buffer circuit and integrated circuit
JP3171927B2 (en) Semiconductor integrated circuit
US6329842B1 (en) Output circuit for electronic devices
JP3935266B2 (en) Voltage detection circuit
JP3385100B2 (en) Operational amplifier
JP3002036B2 (en) Analog input channel selection circuit
JP2555046Y2 (en) Output buffer circuit
JPH05327465A (en) Semiconductor integrated circuit
JP3455463B2 (en) Input buffer circuit
US5773992A (en) Output buffer circuit capable of supressing ringing

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTEGRATED DEVICE TECHNOLOGY, INC., CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ICS TECHNOLOGIES, INC.;REEL/FRAME:018279/0284

Effective date: 20060920

AS Assignment

Owner name: ICS TECHNOLOGIES, INC., DELAWARE

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ISIK, TACETTIN;POITRAS, LOUIS F.;CLEMENTI, DANIEL M.;REEL/FRAME:019692/0502

Effective date: 20050922

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

AS Assignment

Owner name: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT, NE

Free format text: SECURITY AGREEMENT;ASSIGNORS:INTEGRATED DEVICE TECHNOLOGY, INC.;GIGPEAK, INC.;MAGNUM SEMICONDUCTOR, INC.;AND OTHERS;REEL/FRAME:042166/0431

Effective date: 20170404

Owner name: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT, NEW YORK

Free format text: SECURITY AGREEMENT;ASSIGNORS:INTEGRATED DEVICE TECHNOLOGY, INC.;GIGPEAK, INC.;MAGNUM SEMICONDUCTOR, INC.;AND OTHERS;REEL/FRAME:042166/0431

Effective date: 20170404

AS Assignment

Owner name: GIGPEAK, INC., CALIFORNIA

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A.;REEL/FRAME:048746/0001

Effective date: 20190329

Owner name: MAGNUM SEMICONDUCTOR, INC., CALIFORNIA

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A.;REEL/FRAME:048746/0001

Effective date: 20190329

Owner name: CHIPX, INCORPORATED, CALIFORNIA

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A.;REEL/FRAME:048746/0001

Effective date: 20190329

Owner name: INTEGRATED DEVICE TECHNOLOGY, INC., CALIFORNIA

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A.;REEL/FRAME:048746/0001

Effective date: 20190329

Owner name: ENDWAVE CORPORATION, CALIFORNIA

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A.;REEL/FRAME:048746/0001

Effective date: 20190329

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 12