US20050223346A1 - Random code generation using genetic algorithms - Google Patents
Random code generation using genetic algorithms Download PDFInfo
- Publication number
- US20050223346A1 US20050223346A1 US11/141,480 US14148005A US2005223346A1 US 20050223346 A1 US20050223346 A1 US 20050223346A1 US 14148005 A US14148005 A US 14148005A US 2005223346 A1 US2005223346 A1 US 2005223346A1
- Authority
- US
- United States
- Prior art keywords
- knob
- synthesized
- configuration files
- value
- configuration file
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation
- G01R31/318357—Simulation
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318307—Generation of test inputs, e.g. test vectors, patterns or sequences computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318385—Random or pseudo-random test pattern
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Techniques are disclosed for automatically generating test instructions for use in testing a microprocessor design. A configuration file includes a plurality of knobs which specify a probability distribution of a plurality of microprocessor instructions. A random code generator takes the configuration file as an input and generates test instructions which are distributed according to the probability distribution specified by the knobs. The test instructions are executed on the microprocessor design. The microprocessor behaviors that are exercised by the test instructions are measured and a fitness value is assigned to the configuration file using a fitness function. The configuration file and its fitness value are added to a pool of configuration files. A configuration file synthesizer uses a genetic algorithm to synthesize a new configuration file from the pool of existing configuration files. This process may be repeated to generate configuration files which increasingly exercise microprocessor behaviors which are of interest.
Description
- This application is a divisional application of commonly-owned U.S. patent application Ser. No. 10/195,993, filed on Jul. 16, 2002, entitled “Random Code Generation Using Genetic Algorithms”.
- 1. Field of the Invention
- The present invention relates to microprocessor design and, more particularly, to the automatic generation of test instructions for microprocessor designs.
- 2. Related Art
- Various electronic design automation (EDA) software tools exist for designing microprocessors and other circuitry. Such tools allow circuit designers to create and modify virtual models of the circuit being designed. A circuit designer may, for example, specify a circuit design using a textual description written in a hardware description language (HDL), such as Verilog or VHDL, or by using a graphical user interface to manipulate a graphical representation of the circuit design.
- Software tools are also frequently used for testing circuit designs, such as microprocessor designs. Referring to
FIG. 1 , for example, a prior artmicroprocessor test system 100 is shown in functional block diagram form. The system includes amicroprocessor design 110, also referred to as a hardware model under test or design under test (DUT). Although themicroprocessor design 110 may be either an actual (hardware) microprocessor or a software (simulated) model of a microprocessor, assume for purposes of the present discussion that themicroprocessor design 110 is a software model of a microprocessor. - The microprocessor design 110 models both the operation of the microprocessor (e.g., the functional relationship between inputs and outputs of the microprocessor) and the state of the microprocessor's machine resources, such as its registers, cache(s), and main memory, at a particular point in time. The
microprocessor design 110 may be implemented, for example, in a data structure in the memory of a computer or in a file stored on a hard disk or other computer-readable medium. - The
system 100 also includes asimulator 114, which is typically implemented as a software program. Thesimulator 114 simulates the operation of the microprocessor modeled by themicroprocessor design 110. A significant advantage of using simulators for testing is that they may detect errors prior to the costly and time-consuming fabrication of the microprocessor itself. - The
system 100 also includes atest case 102, which specifies both initial values for the (simulated) machine resources of themicroprocessor design 110 and test instructions to be executed (in simulation) by themicroprocessor design 110. Thetest case 102 may also specify the outputs that are expected to result from performing the test instructions based on the specified initial values. Thetest case 102 may, for example, be implemented in a file stored on a computer-readable medium or as a data structure in the memory of a computer. - The
simulator 114 receives thetest case 102 as an input and initializes the (simulated) machine resources of themicroprocessor design 110 with the initial values specified by thetest case 102. Thesimulator 114 then simulates execution of the instructions specified by thetest case 102 on themicroprocessor design 110. Thesimulator 114 modifies the state of themicroprocessor design 110 accordingly as the simulation progresses. Thesimulator 114 producessimulation results 118 which indicate, among other things, whether the output produced by executing the test instructions matches the expected output specified by thetest case 102. - Although a
human circuit designer 116 may create thetest case 102 manually, thetest case 102 is typically generated automatically by a software program referred to as arandom code generator 112. Therandom code generator 112 creates random sequences of instructions that are intended to exercise themicroprocessor design 110 more thoroughly than conventional application software. Therandom code generator 112 may generate large numbers of test cases automatically and rapidly, thereby facilitating the testing process. - Test cases (such as test case 102) generated by
random code generator 112 are typically not, however, completely random. Rather, a good random code generator generates test cases which focus on key aspects of themicroprocessor design 110 while retaining enough randomness to test themicroprocessor design 110 thoroughly. Thecircuit designer 116 may use a configuration file 108 (also referred to as a “probability file”) to exercise control over which test instructions are generated by therandom code generator 112. Theconfiguration file 108 may, for example, specify the frequencies with which different microprocessor instructions are to be simulated by thesimulator 114. More specifically,configuration file 108 may include “knobs” 104. Each knob may specify one instruction or class of instructions by name and the frequency with which the instruction or instruction class should occur in thetest case 102. Therandom code generator 112 is designed to generate test cases in which the distribution of instructions and/or instruction classes at least roughly matches the probability distribution specified by theknobs 104. - Microprocessors and microprocessor designs, such as the
microprocessor design 110, typically have a performance monitoring unit (PMU) which includesevent counters 106 that count the number of times that various events occur in themicroprocessor design 110. Examples of events which may be counted byevent counters 106 include, for example, the number of times the microprocessor's current privilege level (CPL) changes, the amount of traffic on the microprocessor's instruction translation lookaside buffer (ITLB) and/or data translation lookaside buffer (DTLB), the number of CPU cycles, the number of retired (executed and committed) null operations, the number of retired load/store operations, and the number ofLevel 1 and/or Level 2 cache hits and/or misses. The execution of particular test instructions, or the results produced by executing such instructions, may cause one or more events to occur. Each time a particular event occurs, the corresponding one of theevent counters 106 is incremented. - When testing the
microprocessor design 110 it is often desirable to thoroughly test (or “exercise”) the entire range of events. In particular circumstances, however, thecircuit designer 116 may wish to focus the simulation on a particular event or events. It is difficult, however, for thecircuit designer 116 to design theconfiguration file 108 to test (or “exercise”) the entire range of events or particular events of interest because, for example, the relationship between the execution of particular instruction sequences and the occurrence of particular events may be complex and difficult to predict. Although thecircuit designer 116 may improve the extent to which theconfiguration file 108 exercises particular events by inspecting theevent counters 106 and/or thesimulation results 118 upon completion of the simulation performed by thesimulator 114 and modifying theconfiguration file 108 manually in response, such a process is tedious, time-consuming, and not guaranteed to improve the extent to which the configuration file 108 exercises events of interest. - What is needed, therefore, are improved techniques for generating test instructions for microprocessor designs.
- Techniques are disclosed for automatically generating test instructions for use in testing a microprocessor design. A configuration file includes a plurality of knobs which specify a probability distribution of a plurality of microprocessor instructions. A random code generator takes the configuration file as an input and generates test instructions based on the probability distribution specified by the knobs. The test instructions are executed on the microprocessor design. The microprocessor behaviors that are exercised by the test instructions are measured and a fitness value is assigned to the configuration file using a fitness function. The configuration file and its fitness value are added to a pool of configuration files. A configuration file synthesizer uses a genetic algorithm to synthesize a new configuration file from the pool of existing configuration files. This process may be repeated to generate configuration files which increasingly exercise microprocessor behaviors which are of interest.
- In one aspect, the present invention features a method for use in a system including a circuit design (e.g., a microprocessor design) and a plurality of circuit input vectors (e.g., a plurality of microprocessor test instructions) which have been applied to the circuit design to produce at least one occurrence of at least one event within the circuit design. The method includes steps of: (A) identifying a plurality of counter values indicating a number of occurrences of each of a plurality of events; and (B) applying a fitness function to the plurality of counter values to produce an aggregate fitness value for the plurality of circuit input vectors. The fitness function may, for example, be the sum of the plurality of counter values, or the sum of the
expression 1+A+B*log(ci) for each counter value ci. The value of A may, for example, be zero and the value of B may, for example, be one. The circuit design may be a physical circuit or a software model of the circuit. The plurality of events may be events monitored by a performance monitoring unit associated with the circuit design. - In another aspect, the present invention features a method for use in a system including a circuit design and a plurality of configuration files, the plurality of configuration files including a plurality of knobs having a plurality of values specifying a plurality of probability distributions of a plurality of circuit input vectors. The method includes steps of: (A) initializing a synthesized configuration file; (B) selecting a first subset of the plurality of configuration files as a potential parent pool; and (C) for each knob KP included in at least one of the plurality of configuration files in the potential parent pool, providing a synthesized value for knob KP in the synthesized configuration file based on at least one value of knob KP in the plurality of configuration files in the potential parent pool. The plurality of configuration files may be associated with a plurality of fitness values, and the step (B) may include a step of: (B)(1) selecting as the first subset the plurality of configuration files having the highest fitness values in the plurality of configuration files.
- The method may further include a step, performed prior to the step (C), of: (D) replacing the plurality of configuration files in the potential parent pool with a subset of the plurality of configuration files in the potential parent pool. The subset may be randomly selected from the plurality of configuration files in the potential parent pool. The step (C) may include a step of: (C)(1) for each knob KP included in at least one of the plurality of configuration files in the potential parent pool, selecting the synthesized value for knob KP in the synthesized configuration file from among the at least one value of knob KP in the plurality of configuration files in the potential parent pool.
- The step (B) may include steps of: (B)(1) for each knob KP which is included in all of the plurality of configuration files in the potential parent pool, selecting the synthesized value for knob KP from the at least one value of knob KP in the plurality of configuration files in the potential parent pool; and (B)(2) for each knob KP which is not included in all of the plurality of configuration files in the potential parent pool, performing steps of: (B)(2)(a) identifying the ratio of the number of configuration files in the potential parent pool which include the knob KP to the number of configuration files in the potential parent pool; and (B)(2)(b) determining whether to provide the synthesized value for knob KP in the synthesized configuration file based on the ratio. The step (B)(2)(b) may include steps of: (B)(2)(b)(i) randomly selecting a number x1; and (B)(2)(b)(ii) deciding to provide the synthesized value for knob KP in the synthesized configuration file only if x1 is less than the ratio.
- In yet another aspect of the present invention, a method is provided for use in a system including a circuit design and a plurality of configuration files, the plurality of configuration files including a plurality of knobs having a plurality of values specifying a plurality of probability distributions of a plurality of circuit input vectors. The method includes steps of: (A) initializing a synthesized configuration file; (B) selecting a subset of the plurality of configuration files having the highest fitness values as a potential parent pool; (C) randomly selecting a subset of the potential parent pool as a plurality of direct parents; and (D) for each knob KP included in at least one of the direct parents, providing a synthesized value for knob KP in the synthesized configuration file based on at least one value of knob KP in the plurality of direct parents.
- The step (D) may include steps of: (D)(1) determining whether knob KP is included in all of the direct parents; (D)(2) selecting the synthesized value for knob KP from among the at least one value of knob KP in the plurality of direct parents if it is determined that knob KP is included in all of the direct parents; and (D)(3) if it is determined that knob KP is not included in all of the direct parents, performing steps of: (D)(3)(a) selecting a probability p1 that the synthesized value for knob KP will not be included in the synthesized configuration file; (D)(3)(b) randomly selecting a number x1; and (D)(3)(c) including the synthesized value for knob KP in the synthesized configuration file only if x1 is less than p1. The step (D)(3)(a) may include a step of selecting as the probability p1 the ratio of the number of direct parents which include the knob KP to the number of direct parents.
- The step (D)(2) may include steps of: (D)(2)(a) selecting a probability p2; (D)(2)(b) randomly selecting a number x2; (D)(2)(c) selecting the synthesized value for knob KP from among the at least one value of knob KP in the direct parents if x2 is greater than p2; and (D)(2)(d) if x2 is not greater than p2, performing steps of: (D)(2)(d)(i) identifying a range RP of values of knob KP in the direct parents; and (D)(2)(d)(ii) selecting the synthesized value for knob KP from within the range RP. The method may further include a step of: (D)(2)(d)(iii) expanding the range RP to generate an expanded range RE; and the step (D)(2)(d)(ii) may include a step of selecting the synthesized value for knob KP from within the expanded range RE.
- In another aspect of the present invention, a method is provided for use in a system including a circuit design and a plurality of configuration files, the plurality of configuration files including a plurality of knobs having a plurality of values specifying a plurality of probability distributions of a plurality of circuit input vectors. The method includes steps of: (A) generating a first synthesized configuration file based on the plurality of configuration files, the first synthesized configuration file specifying a first synthesized probability distribution of a first subset of the plurality of circuit input vectors; (B) using the first synthesized configuration file to generate a first test case comprising the first subset of the plurality of circuit input vectors; (C) providing the first subset of the plurality of circuit input vectors as inputs to the circuit design; (D) generating a fitness value based on at least one event counter in the microprocessor design, the at least one event counter comprising a count of at least one occurrence of at least one event in the microprocessor design in response to provision of the first subset of the plurality of circuit input vectors; (E) generating a graded configuration file including the synthesized configuration file and the fitness value; and (F) adding the graded configuration file to the plurality of configuration files.
- The method may further include steps of: (G) after the step (F), generating a second synthesized configuration file based on the plurality of configuration files, the second synthesized configuration file specifying a second synthesized probability distribution of a second subset of the plurality of circuit input vectors; (H) using the second synthesized configuration file to generate a second test case comprising the second subset of the plurality of circuit input vectors; and (I) providing the second subset of the plurality of circuit input vectors as inputs to the circuit design.
- Other features and advantages of various aspects and embodiments of the present invention will become apparent from the following description and from the claims.
-
FIG. 1 is a data flow diagram of a prior art system for testing a microprocessor design; -
FIG. 2A is a data flow diagram of a system for testing a microprocessor design according to one embodiment of the present invention; -
FIG. 2B is a diagram of a stream of configuration files and corresponding fitness values generated by a fitness calculator according to one embodiment of the present invention; -
FIG. 2C is a diagram of a plurality of graded configuration files according to one embodiment of the present invention; -
FIG. 2D is a data flow diagram of a system for synthesizing a new configuration file from existing graded configuration files according to one embodiment of the present invention; -
FIG. 3A is a flowchart of a method performed by the system ofFIG. 2D for synthesizing a new configuration file from existing graded configuration files, assigning a grade to the synthesized configuration file, and adding the synthesized configuration file and corresponding grade to the graded configuration files according to one embodiment of the present invention; -
FIG. 3B is a flowchart of a method for calculating fitness value for a configuration file according to one embodiment of the present invention; -
FIG. 3C is a flowchart of a method for synthesizing a new configuration file from existing configuration files according to one embodiment of the present invention; -
FIG. 3D is a flowchart of a method for selecting a value for a knob in a synthesized configuration file according to one embodiment of the present invention; -
FIG. 4 is a data flow diagram of a system for generating a fitness value for a configuration file according to one embodiment of the present invention; and -
FIGS. 5A-5B are graphs of fitness values generated by embodiments of the present invention for sequences of configuration files. - Referring to
FIG. 2A , asystem 200 for testing themicroprocessor design 110 according to one embodiment of the present invention is shown. Thesystem 200 includesconfiguration file 108,random code generator 112,test case 102,simulator 114, andmicroprocessor design 110, which may, for example, be conventional elements as described above with respect toFIG. 1 . Thesystem 200 also includes however, afitness calculator 202 which may, for example, be implemented as a software program. Upon completion of the simulation performed by thesimulator 114, thefitness calculator 202 may generate a fitness value 206 (also referred to herein as a “grade”) which indicates the extent to which the test instructions in thetest case 102 exercise events or other behaviors in themicroprocessor design 110 that are of interest to thecircuit designer 116. Thefitness value 206 therefore indirectly indicates the fitness of theknobs 104 in theconfiguration file 108. - The
circuit designer 116 may, for example, provide anevent counter list 204 to thefitness calculator 202. Theevent counter list 204 may specify one or more of the event counters 106 which count events that are of interest to thecircuit designer 116. Thefitness calculator 202 generates thefitness value 206 based on the values of the event counters specified in theevent counter list 204. Theevent counter list 204 may identify particular ones of the event counters in any manner. For example, each of the event counters 106 may have a unique identifier, such as a numerical or textual identifier, in which case theevent counter list 204 may identify event counters using their unique identifiers. - The
circuit designer 116 may also provideadditional fitness parameters 208 to thefitness calculator 202 for use in generating thefitness value 206. Particular examples of thefitness parameters 208 are described below with respect toFIG. 4 . Particular examples of techniques that thefitness calculator 202 may use to generate thefitness value 206 are described in more detail below with respect toFIG. 3B . - A
configuration file manager 212 adds theconfiguration file 108, along with its associatedfitness value 206, to a collection of graded configuration files 210. If thecircuit designer 116 provides a new configuration file to therandom code generator 112, thefitness calculator 202 will generate a new fitness value corresponding to the new configuration file. Theconfiguration file manager 212 will add the new configuration file, along with its associatedfitness value 206, to the graded configuration files 210. - For example, referring to
FIG. 2B , a stream ofconfiguration files 108 a-n is shown along withcorresponding fitness values 206 a-n, in which n is the number of configuration files and corresponding fitness values. Each of theconfiguration files 108 a-n is used by therandom code generator 112 to generate corresponding test cases. AlthoughFIG. 2A shows only onetest case 102 corresponding to theconfiguration file 108, therandom code generator 112 typically generates many test cases from a single configuration file. Returning toFIG. 2B , for each of theconfiguration files 108 a-n: (1) thesimulator 114 simulates execution of each of the corresponding test cases on themicroprocessor design 110, and (2) thefitness calculator 202 generates a corresponding one of thefitness values 206 a-n. In other words, upon execution of all of the test cases corresponding to a particular one of theconfiguration files 108 a-n, thefitness calculator 202 generates a fitness value for the configuration file. Although theconfiguration files 108 a-n are illustrated as inputs to thefitness calculator 202 inFIG. 2B for ease of illustration, in practice the information contained in theconfiguration files 108 a-n is only input to thefitness calculator 202 indirectly through the sequence of events illustrated inFIG. 2A . - Referring to
FIG. 2C , an example of the graded configuration files 210 is shown. In the example illustrated inFIG. 2C , graded configuration files 210 include gradedconfiguration files 210 a-n, each of which includes one of theconfiguration files 108 a-n and a corresponding one of thefitness values 206 a-n. For example, gradedconfiguration file 210 a includes configuration file 108 a and thecorresponding fitness value 206 a. Although in the example described above theconfiguration files 108 a-n are generated manually by thecircuit designer 116, one or more of theconfiguration files 108 a-n may be generated automatically, as described in more detail below. - Referring to
FIG. 2D , asystem 220 for synthesizing anew configuration file 224 from existing gradedconfiguration files 210 a-n is shown according to one embodiment of the present invention. Referring toFIG. 3A , a flowchart is shown of amethod 300 that is performed by thesystem 220 according to one embodiment of the present invention. Aconfiguration file synthesizer 222 takes as input the existing gradedconfiguration files 210 a-n (illustrated in solid outline inFIG. 2D ) and synthesizes from them the synthesizedconfiguration file 224, containing knobs 226 (step 302). In particular, theconfiguration file synthesizer 222 may synthesize the synthesizedconfiguration file 224 from the existing gradedconfiguration files 210 a-n having the highest fitness values. As described in more detail below, the existing graded configuration files having the highest fitness values are referred to as the “potential parent pool.” Various techniques that theconfiguration file synthesizer 222 may use to generate the synthesizedconfiguration file 224 will be described in more detail below with respect toFIG. 3C-5D . - The synthesized
configuration file 224 is provided as input to therandom code generator 112, which generatestest case 226 based on the synthesizedconfiguration file 224 in the manner described above with respect toFIG. 2A (step 304). Although only onetest case 226 is shown inFIG. 2D , in practice therandom code generator 112 may generate many test cases based on the synthesizedconfiguration file 224. Thesimulator 114 simulates execution of the instructions in the test case 226 (and any other test cases which have been generated) on themicroprocessor design 110, thereby causing the values of event counters 106 to change appropriately (step 306). Thefitness calculator 202 generates afitness value 228 for the synthesized configuration file 224 (step 308). (Thefitness parameters 208 and theevent counter list 204, shown inFIG. 2A , are also input to thefitness calculator 202 but are omitted fromFIG. 2D for ease of illustration.) - The
configuration file manager 212 generates a graded configuration file 230 corresponding to the synthesizedconfiguration file 224 and its corresponding fitness value 228 (step 310), and adds the graded configuration file 230 to the graded configuration files 210 (step 312). In this way, the synthesizedconfiguration file 224 becomes available for use in synthesizing additional synthesized configuration files (by repeatedly performing method 300), which may in turn be used to synthesized additional synthesized configuration files, and so on. - As described in more detail below, the
configuration file synthesizer 222 may synthesize the most fit ones of the existing gradedconfiguration files 210 a-n in such a manner that theknobs 226 in the synthesizedconfiguration file 224 specify an instruction probability distribution that results in test cases which tend to better exercise the events that are of interest to thecircuit designer 116 than the existing gradedconfiguration files 210 a-n. By generating synthesized configuration files in this way and using them as inputs to therandom code generator 112, thesystem 220 tends to increasingly exercise the events that are of interest to thecircuit designer 116. - Having described in general overview the operation of various embodiments of the present invention, embodiments of the present invention will now be described in more detail. For example, referring to
FIG. 3B , a flow chart is shown of amethod 308 that is performed by thefitness calculator 202 to calculate the fitness value 206 (referred to below by the variable V) according to one embodiment of the present invention. - The
method 308 initializes the fitness value V (step 322). The fitness value V may be initialized to any appropriate value, such as zero or one. Themethod 308 enters a loop over each event counter e specified in the event counter list 204 (step 324). As described above, theevent counter list 204 may specify a subset of the event counters 106 that is of interest to thecircuit designer 116. Themethod 308 identifies the value ci of event counter e (step 326). As described above, the value ci represents the number of times that the corresponding event occurred while executing the test instructions in thetest case 102. - The
fitness calculator 202 may include a fitness function. For example, referring toFIG. 4 , one embodiment of thefitness calculator 202 is illustrated in more detail. As shown inFIG. 4 , the fitness calculator includes afitness function 408. In the particular embodiment illustrated inFIG. 4 , thefitness parameters 208 include twoparameters event counter list 204. Specified event counters 406 includes event counter values c0, c1, c2, . . . , cm, where m is the number of event counters specified in theevent counter list 204. Themethod 308 may, for example, generate the list of specified event counters 406 prior to execution of themethod 308 or retrieve each of the specified event counter values from the event counters 106 as needed. - The
fitness function 408 may be any function. For example, the fitness function may simply be the sum of each of the counter values ci. Such a fitness function provides a straightforward measure of fitness by making the fitness value equal to the total number of times that any event specified in the event counter list occurs during simulation. - Referring to
FIG. 4 , the fitness function alternatively may be the sum of the expression (1+A+B*log(ci)) for each counter value ci. Such a function reflects a relatively strong interest in any event counter which has a non-zero value (corresponding to events which occurred at least once during simulation) and a relatively weak interest in additional occurrences of such events. In the event that thecircuit designer 116 does not specify values for one or more of thefitness parameters 208, thefitness calculator 202 may provide default values. For example, in one embodiment default value for the A parameter is zero and the default value for the B parameter is one. - The
fitness function 408 may, for example, include both: (1) a counter fitness function f1 which generates a counter fitness value Vi based on the value of the current event counter ci, and (2) a combination function f2 for combining the results of the counter fitness function f1 for each of the error counter values. For example, returning toFIG. 3B , themethod 308 may calculate counter fitness value Vi based on the counter value ci using counter fitness function f1 (step 328). Themethod 308 may update the value of V based on the current value of V and the value of Vi using the combination function f2 (step 330). Themethod 308 repeats steps 326-330 (step 332) to generate the final fitness value V, which is output asfitness value 206. - For example, in the embodiment illustrated in
FIG. 4 , the counter fitness function f1(ci)=1+A+B*log(ci) and the combination function f2(V,Vi)=V+Vi. In other words, if thefitness function 408 generates thefitness value 206 by summing the values of the specified event counters 406, the counter fitness function f1(ci)=ci and the combination function f2(V,Vi)=V+Vi. - The
method 308 illustrated inFIG. 3B may be applied to generate thefitness value 206 when thetest case 102 is either a single test case or a plurality of test cases. If thetest case 102 is a single test case, themethod 308 may be applied to the generate thefitness value 206 based on the values of the event counters 106 after execution of thetest case 102. If thetest case 102 is a plurality of test cases, the values of the event counters 106 after execution of each test case may be combined in any of a variety of ways prior to being input to themethod 308. For example, in one embodiment, themethod 308 may be performed after the execution of each test case to generate a fitness value for each test case. The fitness values for each test case may then be combined by addition or some other function to generate theoverall fitness value 206 for theconfiguration file 108. - As described above with respect to
FIG. 3A , theconfiguration file synthesizer 222 may generate the synthesizedconfiguration file 224 based on the existing gradedconfiguration files 210 a-n (FIG. 3A , step 302). Referring toFIG. 3C , a flow chart is shown of a method that may be used to implementstep 302. Themethod 302 selects the N graded configuration files having the highest fitness values (step 342). The configuration files selected instep 342 are referred to herein as the “potential parent pool.” Theconfiguration file synthesizer 222 may performstep 342 by, for example, sorting the gradedconfiguration files 210 a-n in descending order of fitness value and selecting the first N graded configuration files in the sorted list as the potential parent pool. Theconfiguration file synthesizer 222 may select the value N in any manner. Referring toFIG. 2D , for example, thecircuit designer 116 may provide the value of N to theconfiguration file synthesizer 222 as one of a plurality ofconfiguration parameters 232. - Returning to
FIG. 3C , themethod 302 randomly selects P graded configuration files from the potential parent pool (step 344). The graded configuration files selected instep 344 are referred to herein as “direct parents.” Theconfiguration file synthesizer 222 may select the value P in any manner. For example, thecircuit designer 116 may provide the value of P as one of theconfiguration parameters 232. As described in more detail below, theconfiguration file synthesizer 222 synthesizes knob values from the direct parents to generate knob values for the synthesizedconfiguration file 224. - As described above, the
knobs 104 may specify individual instructions or instruction classes and corresponding probabilities. Each knob typically consists of a knob name and corresponding knob value. The knobs in a configuration file may therefore be represented as a list of knob name-value pairs. A knob name may, for example, be the name or other identifier of an instruction or a class of instructions. Examples of instruction classes include, but are not limited to, data transfer instructions, Arithmetic-Logic Unit (ALU) instructions, string instructions, floating point instructions, flag manipulation instructions, system instructions, semaphore instructions, Intel MMX™ instructions, instruction set switching branches, inter-segment branches, and intra-segment branches. - Returning to
FIG. 3C , themethod 302 initializes the synthesized configuration file 224 (step 346). Initializing the synthesizedconfiguration file 224 may include, for example, creating an empty list of knob name-value pairs or creating a list of knob name-value pairs in which the values are undefined (such as null values). According to the description herein, a configuration file “includes” a knob if the configuration file includes a defined value for the knob. If, for example, a configuration file includes a knob name-value pair for a particular knob, but the value of the name-value pair is undefined (such as a null value), then the configuration file does not “include” the knob as that term is used herein. Similarly, a configuration file does not “include” a knob if the configuration file does not include a name-value pair for the knob. - The
method 302 enters a loop over each knob KP which is included in at least one of the direct parents (step 348). Themethod 302 determines whether the knob KP is in all of the direct parents (step 350). If it is, themethod 302 adds knob KP to the synthesized configuration file 224 (step 352). As described above, each knob in a configuration file typically consists of a knob name and corresponding knob value. Theknobs 226 in the synthesizedconfiguration file 224 may therefore be represented as a list of knob name-value pairs. Themethod 302 may “add” knob KP to the synthesizedconfiguration file 224 instep 352 by, for example, adding a name-value pair having the name of knob KP to theknobs 226 in the synthesizedconfiguration file 224. - The
method 302 selects a value VK for knob KP based on the values of knob KP in the direct parents (step 354). Themethod 302 may select the value VK in any of a variety of ways, one example of which is described below with respect toFIG. 3D . Themethod 302 assigns the value VK to the knob KP in theknobs 226 of the synthesized configuration file 224 (step 356). Themethod 302 may, for example, performstep 356 by assigning value VK to the value of the name-value pair for knob KP in theknobs 226. - If the
method 302 determines that the knob KP is not in all direct parents instep 350, then the knob KP is in at least one but not all of the direct parents. When a configuration file does not include (e.g., does not specify a value for) a particular knob, therandom code generator 112 may provide a default value for that knob. Typically it is not possible, however, to determine ahead of time which default value therandom code generator 112 will assign to a particular knob. In one embodiment, if a particular knob is included in at least one but not all of the direct parents, themethod 302 excludes the knob from the synthesizedconfiguration file 224 with a probability that is directly proportional to the percentage of direct parents which do not include the knob. - For example, referring again to
FIG. 3C , if the knob KP is in at least one (step 348) but not all (step 350) of the direct parents, themethod 302 selects a probability p1 that knob KP will not be included in theknobs 226 of the synthesized configuration file 224 (step 358). Theconfiguration file synthesizer 222 may select the value p1 in any manner. For example, themethod 302 may calculate the probability p1 as the percentage of direct parents which do not contain the knob KP (i.e., the number of direct parents which do not contain the knob KP divided by the number P of direct parents). Alternatively, referring toFIG. 2D , thecircuit designer 116 may, for example, include the value of p1 as one of theconfiguration parameters 232. Assuming for purposes of example that the probability p1 is expressed as a decimal number between zero and one, themethod 302 randomly selects a number x1 between zero and one (step 360). If x1<p1, (step 362), themethod 302 adds knob KP to theknobs 226 of the synthesized configuration file 224 (steps 352-356) as described above. Otherwise, themethod 302 does not add knob KP to theknobs 226 of the synthesizedconfiguration file 224. The effect of steps 358-362 is that, in the case of any knob which is in at least one but fewer than all of the direct parents, there is a probability p1 that the knob will not be added to theknobs 226 of the synthesizedconfiguration file 224. The purpose of steps 358-362 is to make the probability that a particular knob will be included in the synthesizedconfiguration file 224 the same as the probability that the knob will be found in a particular one of the direct parents. - The
method 302 repeats steps 350-362 for the remaining knobs KP which are in at least one of the direct parents (step 364). Upon the completion ofmethod 302, theknobs 226 include knobs whose values have been synthesized from the values of knobs in the most fit ones of the gradedconfiguration files 210 a-n. As described above with respect toFIG. 2D , the synthesizedconfiguration file 224 generated by themethod 302 may be used to test themicroprocessor design 110 and to generate yet another graded configuration file which may be added to the graded configuration files 210. In this way, each new synthesized configuration file generated by theconfiguration file synthesizer 222 is likely to have a higher fitness value than previous configuration files and therefore to better exercise the features of themicroprocessor design 110 that are of interest to thecircuit designer 116 than the previous configuration files. - As described above with respect to
FIG. 3C , theconfiguration file synthesizer 222 may select a value VK for the knob KP based on the values of knob KP in the direct parents (step 354). Referring toFIG. 3D , a flow chart is shown of amethod 354 that is used to select the value VK according to one embodiment of the present invention. - The
method 354 selects a probability p2 (step 370). Themethod 354 may select the value p2 in any manner. Referring toFIG. 2D , for example, thecircuit designer 116 may provide the value of p2 as one of theconfiguration parameters 232. - Assuming for purposes of example that the probability p2 is a decimal number between zero and one, the
method 354 randomly selects a number x2 between zero and one (step 372). Themethod 354 determines whether x2>p2 (step 374). If it is, themethod 354 selects the value VK randomly from the values of knob KP in the direct parents (step 376). - If x2 is not greater than p2, the
method 354 identifies the range RP of values of knob KP in the direct parents (i.e., the difference between the maximum and minimum values of knob KP in the direct parents) (step 378). Themethod 354 identifies an expansion percentage E (step 380). Themethod 354 may select the value E in any manner. Referring toFIG. 2D , for example, thecircuit designer 116 may provide the value of E as one of theconfiguration parameters 232. Themethod 354 expands the range RP by E percent to generate an expanded range RE (step 382). Themethod 354 may, for example, expand the range RP at the bottom of range RP, at the top of range RP, or a combination of both to generate the expanded range RE. Themethod 354 selects the value of VK randomly within the expanded range RE (step 384). - Selection of the value VK is complete upon completion of
step method 302 illustrated inFIG. 3C . - According to the
method 354, there is a probability of p2 that the value of knob KP will be chosen at random in the range RE, and a probability of 1-p2 that the value of knob KP will be chosen randomly from the values of knob KP in the direct parents. Advantages of choosing the knob value in this way will be described below. - As described above, the
fitness values 206 a-n (FIG. 2C ) that are assigned to theconfiguration files 108 a-n reflect the degree to which the test instructions generated based on theconfiguration files 108 a-n exercise the events that are of interest to thecircuit designer 116. If the techniques disclosed herein are implemented appropriately, the fitness values of new synthesized configuration files generated by theconfiguration file synthesizer 222 should tend to increase over time. - For example, referring to
FIGS. 5A-5B , graphs are shown of the fitness values of a sequence of configuration files CFi over time, in which the index i is referred to herein as a “configuration file number.” For example, the first configuration file in the sequence has configuration file number zero, the second configuration file number has configuration file number one, and so on. In bothFIGS. 5A and 5B , the x axis represents the configuration file number, and the y axis represents the fitness value of the corresponding configuration file. In the particular examples illustrated inFIG. 5A-5B , the fitness function illustrated inFIG. 4 was used to calculate fitness values, in which A=0 and B=1. The graphs shown inFIGS. 5A-5B are merely examples, and the actual results obtained in particular implementations may vary depending upon the details of the implementation, such as theparticular configuration parameters 232,fitness parameters 208, andevent counter list 204 that are used. - Referring to
FIG. 5A , a graph is shown in which all configuration files in the sequence were generated using theconfiguration file synthesizer 222. As may be seen fromFIG. 5A , the fitness values of the configuration files generated by theconfiguration file synthesizer 222 generally increase over time, leveling off after the generation of approximately eighty configuration files. - Referring to
FIG. 5B , a graph is shown in which approximately the first 480 configuration files (i.e., from x=0 through x=480 in the graph) were generated manually using conventional techniques, and in which theconfiguration file synthesizer 222 was used to generate configuration files beginning at approximately x=480, using the previous 480 configuration files as a starting point. As may be seen fromFIG. 5B , the fitness values of the configuration files increased rapidly upon commencing use of theconfiguration file synthesizer 222, with fitness values leveling off at approximately x=700. - Among the advantages of the invention are one or more of the following.
- It is difficult to manually design configuration files which exercise behaviors (e.g., events) in the
microprocessor design 110 which are of interest to thecircuit designer 116. One reason for this difficulty is that the relationship between the test instruction probabilities that are specified in configuration files and the behaviors which are exercised by the resulting test instructions is complex and difficult to predict. For example, a particular event may occur as the result of a long and/or complex sequence of instructions, and the relationship between the event and the sequence of instructions may not be apparent. The techniques described above in effect both: (1) identify the relationship between test instructions and events, and (2) create new configuration files which more closely specify test instruction distributions which will exercise the events of interest to thecircuit designer 116. The techniques disclosed herein use the actual event counter values resulting from the application of a particular configuration file as feedback which is used to generate subsequent configuration files. This feedback is applied automatically, rapidly, and repeatedly to improve the ability of configuration files to exercise the behaviors that are of interest to thecircuit designer 116, thereby relieving thecircuit designer 116 of the responsibility for manually inspecting the event counters 106 and determining how to modify the configuration file in response. - Although the use of a conventional random code generator, by itself, does represent an improvement over purely manual generation of code, conventional random code generators do not provide any feedback about the effectiveness of the code they produce for testing events of interest. Even when a conventional random code generator is used, it is typically necessary for the
circuit designer 116 to manually inspect the simulation results 118 and/or the event counters 106 manually and attempt to modify theconfiguration file 108 in response. This can be a tedious and time-consuming process. - The techniques disclosed herein subject the configuration files 210 to an evolutionary process which identifies the configuration files which are most “fit” and which selects knob values from the fittest configuration files for use in subsequent configuration files. This is an example of what is referred to as a “genetic algorithm.” Furthermore, the techniques disclosed herein are not limited to using knob values which explicitly appear in the direct parent configuration files. Rather, as described above with respect to
FIG. 3D , in some cases theconfiguration file synthesizer 222 “mutates” knob values from the direct parents to produce a knob value in the new graded configuration file 230 which does not exist in any of the direct parents (FIG. 3D , step 378-384). This use of mutation strikes a balance between breadth of behavior coverage and focusing on desired behaviors. - By improving the fitness of the configuration files that are used to test the
microprocessor design 110 over time, the techniques disclosed herein increase the likelihood that interesting behaviors and decreases the likelihood that uninteresting behaviors will be tested. The techniques disclosed herein in effect guide therandom code generator 112 to generate instructions that exercise certain behaviors that are of interest to thecircuit designer 116. - It is to be understood that although the invention has been described above in terms of particular embodiments, the foregoing embodiments are provided as illustrative only, and do not limit or define the scope of the invention. Various other embodiments, including but not limited to the following, are also within the scope of the claims.
- Although the techniques disclosed herein as described with respect to the
microprocessor design 110, the same techniques may be applied to other kinds of circuit designs. More generally, for example, thetest case 102 may be any set of circuit input vectors provided to a circuit design. Similarly, the event counters 106 may be any output produced by the circuit design. Alternatively, the event counters 106 may, for example, be internal signals or resource values (such as the values of memory locations) within a circuit design. Thefitness calculator 202 may generate thefitness value 206 based on any function of the event counters. - Furthermore, although the examples disclosed herein describe the
microprocessor design 110 as a software model of a microprocessor, the techniques disclosed herein may also be applied to physical microprocessors. The event counters 106 may, for example, be hardware rather than software event counters, and the test instructions in thetest case 102 may be provided directly to themicroprocessor design 110 for execution without the use of thesimulator 114. - The various knobs described herein (such as the
knobs 104 and the knobs 226) may each correspond to a particular instruction or to a class (type) of instruction. Similarly, each of the events counted by the event counters 106 may either be an individual event or a class (type) of event. More generally, the term “event” refers herein generally to any behavior of themicroprocessor design 110 which may be characterized by a numerical value or other data structure. The event counters 106 are not limited, for example, to counting events which are typically counted by hardware PMUs. Furthermore, the event counters 106 may count occurrences of event which do not strictly occur within themicroprocessor design 110 but which are derived from events which occur within themicroprocessor design 110. For example, the event counters 106 may count events generated by external analysis tools which analyze the operation of themicroprocessor design 110. - Although the drawings illustrate various data structures (e.g., the
configuration file 108,test case 102,fitness value 206,fitness parameters 208,event counter list 208, graded configuration files 210, and configuration parameters 208) as having particular logical structures, these are provided merely for purposes of example and do not constitute limitations of the present invention. Rather, alternative data structures for representing equivalent information and for performing equivalent functions will be apparent to those of ordinary skill in the art. Furthermore, although various data structures are described as being implementable as files in a computer file system, this is not a limitation of the present invention. Rather, such data structures may be implemented as binary files, database files, tables generated by word processing or spreadsheet software, header files or other source code files written in a programming language such as C, or using any appropriate data structure stored on any appropriate computer-readable medium. In particular, the term configuration “file” refers not only to a file stored in a computer file system, but more generally to any computer-implemented means for specifying a probability distribution of test instructions to execute on themicroprocessor design 110. - Elements and components described herein may be further divided into additional components or joined together to form fewer components for performing the same functions. For example, the
fitness calculator 202,configuration file manager 212,random code generator 112,simulator 114, andconfiguration file synthesizer 222 may be combined and/or separated into one or more components. - Although the examples described herein are described in relation to the
microprocessor design 110, it should be appreciated that the techniques described herein may be applied more broadly to any kind of circuit design. - The techniques described above may be implemented, for example, in hardware, software, firmware, or any combination thereof. For example, the
fitness calculator 202,configuration file manager 212,random code generator 112,simulator 114, and theconfiguration file synthesizer 222 may be implemented as computer programs. The techniques described above may be implemented in one or more computer programs executing on a programmable computer including a processor, a storage medium readable by the processor (including, for example, volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device. Program code may be applied to input entered using the input device to perform the functions described and to generate output. The output may be provided to one or more output devices. - Each computer program within the scope of the claims below may be implemented in any programming language, such as assembly language, machine language, a high-level procedural programming language, or an object-oriented programming language. The programming language may, for example, be a compiled or interpreted programming language.
- Each such computer program may be implemented in a computer program product tangibly embodied in a machine-readable storage device for execution by a computer processor. Method steps of the invention may be performed by a computer processor executing a program tangibly embodied on a computer-readable medium to perform functions of the invention by operating on input and generating output. Suitable processors include, by way of example, both general and special purpose microprocessors. Generally, the processor receives instructions and data from a read-only memory and/or a random access memory. Storage devices suitable for tangibly embodying computer program instructions include, for example, all forms of non-volatile memory, such as semiconductor memory devices, including EPROM, EEPROM, and flash memory devices; magnetic disks such as internal hard disks and removable disks; magneto-optical disks; and CD-ROMs. Any of the foregoing may be supplemented by, or incorporated in, specially-designed ASICs (application-specific integrated circuits). A computer can generally also receive programs and data from a storage medium such as an internal disk (not shown) or a removable disk. These elements will also be found in a conventional desktop or workstation computer as well as other computers suitable for executing computer programs implementing the methods described herein, which may be used in conjunction with any digital print engine or marking engine, display monitor, or other raster output device capable of producing color or gray scale pixels on paper, film, display screen, or other output medium.
Claims (34)
1. In a system including a circuit design and a plurality of configuration files, the plurality of configuration files including a plurality of knobs having a plurality of values specifying a plurality of probability distributions of a plurality of circuit input vectors, a method comprising steps of:
(A) initializing a synthesized configuration file;
(B) selecting a first subset of the plurality of configuration files as a potential parent pool; and
(C) for each knob KP included in at least one of the plurality of configuration files in the potential parent pool, providing a synthesized value for knob KP in the synthesized configuration file based on at least one value of knob KP in the plurality of configuration files in the potential parent pool.
2. The method of claim 1 , wherein the plurality of configuration files are associated with a plurality of fitness values, and wherein the step (B) comprises steps of:
(B)(1) selecting as the first subset the plurality of configuration files having the highest fitness values in the plurality of configuration files.
3. The method of claim 1 , further comprising a step of:
(D) prior to the step (C), replacing the plurality of configuration files in the potential parent pool with a subset of the plurality of configuration files in the potential parent pool.
4. The method of claim 3 , wherein the step (D) comprises a step of replacing the plurality of configuration files in the potential parent pool with a randomly-selected subset of the plurality of configuration files in the potential parent pool.
5. The method of claim 1 , wherein the step (C) comprises a step of:
(C)(1) for each knob KP included in at least one of the plurality of configuration files in the potential parent pool, selecting the synthesized value for knob KP in the synthesized configuration file from among the at least one value of knob KP in the plurality of configuration files in the potential parent pool.
6. The method of claim 1 , wherein the step (B) comprises steps of:
(B)(1) for each knob KP which is included in all of the plurality of configuration files in the potential parent pool, selecting the synthesized value for knob KP from the at least one value of knob KP in the plurality of configuration files in the potential parent pool; and
(B)(2) for each knob KP which is not included in all of the plurality of configuration files in the potential parent pool, performing steps of:
(B)(2)(a) identifying the ratio of the number of configuration files in the potential parent pool which include the knob KP to the number of configuration files in the potential parent pool; and
(B)(2)(b) determining whether to provide the synthesized value for knob KP in the synthesized configuration file based on the ratio.
7. The method of claim 6 , wherein the step (B)(2)(b) comprises steps of:
(B)(2)(b)(i) randomly selecting a number x1; and
(B)(2)(b)(ii) deciding to provide the synthesized value for knob KP in the synthesized configuration file only if x1 is less than the ratio.
8. The method of claim 1 , wherein the circuit design comprises a microprocessor design and wherein the plurality of circuit input vectors comprises a plurality of test instructions for execution on the microprocessor design.
9. A system comprising:
a circuit design;
a plurality of configuration files, the plurality of configuration files including a plurality of knobs having a plurality of values specifying a plurality of probability distributions of a plurality of circuit input vectors;
means for initializing a synthesized configuration file;
first selection means for selecting a first subset of the plurality of configuration files as a potential parent pool; and
synthesizing means for providing a synthesized value in the synthesized configuration file for each knob KP included in at least one of the plurality of configuration files in the potential parent pool based on at least one value of knob KP in the plurality of configuration files in the potential parent pool.
10. The system of claim 9 , wherein the plurality of configuration files are associated with a plurality of fitness values, and wherein the first selection means comprises:
second selection means for selecting as the first subset the plurality of configuration files having the highest fitness values in the plurality of configuration files.
11. The system of claim 9 , further comprising:
means for replacing the plurality of configuration files in the potential parent pool with a subset of the plurality of configuration files in the potential parent pool prior to execution of the synthesizing means.
12. The system of claim 11 , wherein the means for replacing the plurality of configuration files comprises means for replacing the plurality of configuration files in the potential parent pool with a randomly-selected subset of the plurality of configuration files in the potential parent pool.
13. The system of claim 9 , wherein the synthesizing means comprises:
means for selecting, for each knob KP included in at least one of the plurality of configuration files in the potential parent pool, the synthesized value for knob KP in the synthesized configuration file from among the at least one value of knob KP in the plurality of configuration files in the potential parent pool.
14. The system of claim 9 , wherein the first selection means comprises:
means for selecting, for each knob KP which is included in all of the plurality of configuration files in the potential parent pool, the synthesized value for knob KP from the at least one value of knob KP in the plurality of configuration files in the potential parent pool; and
inclusion determination means for performing the following steps for each knob KP which is not included in all of the plurality of configuration files in the potential parent pool: (a) identifying the ratio of the number of configuration files in the potential parent pool which include the knob KP to the number of configuration files in the potential parent pool; and (b) determining whether to provide the synthesized value for knob KP in the synthesized configuration file based on the ratio.
15. The system of claim 14 , wherein the inclusion determination means comprises:
means for randomly selecting a number x1; and
means for deciding to provide the synthesized value for knob KP in the synthesized configuration file only if x1 is less than the ratio.
16. The system of claim 9 , wherein the circuit design comprises a microprocessor design and wherein the plurality of circuit input vectors comprises a plurality of test instructions for execution on the microprocessor design.
17. In a system including a circuit design and a plurality of configuration files, the plurality of configuration files including a plurality of knobs having a plurality of values specifying a plurality of probability distributions of a plurality of circuit input vectors, a method comprising steps of:
(A) initializing a synthesized configuration file;
(B) selecting a subset of the plurality of configuration files having the highest fitness values as a potential parent pool;
(C) randomly selecting a subset of the potential parent pool as a plurality of direct parents;
(D) for each knob KP included in at least one of the direct parents, providing a synthesized value for knob KP in the synthesized configuration file based on at least one value of knob KP in the plurality of direct parents.
18. The method of claim 17 , wherein step (D) comprises steps of:
(D)(1) determining whether knob KP is included in all of the direct parents;
(D)(2) selecting the synthesized value for knob KP from among the at least one value of knob KP in the plurality of direct parents if it is determined that knob KP is included in all of the direct parents; and
(D)(3) if it is determined that knob KP is not included in all of the direct parents, performing steps of:
(D)(3)(a) selecting a probability p1 that the synthesized value for knob KP will not be included in the synthesized configuration file;
(D)(3)(b) randomly selecting a number x1; and
(D)(3)(c) including the synthesized value for knob KP in the synthesized configuration file only if x1 is less than p1.
19. The method of claim 18 , wherein the step (D)(3)(a) comprises a step of selecting as the probability p1 the ratio of the number of direct parents which include the knob KP to the number of direct parents.
20. The method of claim 18 , wherein the step (D)(2) comprises steps of:
(D)(2)(a) selecting a probability p2;
(D)(2)(b) randomly selecting a number x2;
(D)(2)(c) selecting the synthesized value for knob KP from among the at least one value of knob KP in the direct parents if x2 is greater than p2; and
(D)(2)(d) if x2 is not greater than p2, performing steps of:
(D)(2)(d)(i) identifying a range RP of values of knob KP in the direct parents; and
(D)(2)(d)(ii) selecting the synthesized value for knob KP from within the range RP.
21. The method of claim 20 , further comprising a step of:
(D)(2)(d)(iii) expanding the range RP to generate an expanded range RE; and
wherein the step (D)(2)(d)(ii) comprises a step of selecting the synthesized value for knob KP from within the expanded range RE.
22. The method of claim 17 , wherein the circuit design comprises a microprocessor design and wherein the plurality of circuit input vectors comprises a plurality of test instructions for execution on the microprocessor design.
23. A system comprising:
a circuit design;
a plurality of configuration files, the plurality of configuration files including a plurality of knobs having a plurality of values specifying a plurality of probability distributions of a plurality of circuit input vectors;
means for initializing a synthesized configuration file;
means for selecting a subset of the plurality of configuration files having the highest fitness values as a potential parent pool;
means for randomly selecting a subset of the potential parent pool as a plurality of direct parents;
synthesizing means for providing, for each knob KP included in at least one of the direct parents, a synthesized value for knob KP in the synthesized configuration file based on at least one value of knob KP in the plurality of direct parents.
24. The system of claim 23 , wherein synthesizing means comprises:
means for determining whether knob KP is included in all of the direct parents;
selection means for selecting the synthesized value for knob KP from among the at least one value of knob KP in the plurality of direct parents if it is determined that knob KP is included in all of the direct parents; and
means for performing the following steps if it is determined that knob KP is not included in all of the direct parents: (a) selecting a probability p1 that the synthesized value for knob KP will not be included in the synthesized configuration file; (b) randomly selecting a number x1; and (c) including the synthesized value for knob KP in the synthesized configuration file only if x1 is less than p1.
25. The system of claim 24 , wherein the means for selecting the probability p1 comprises means for selecting as the probability p1 the ratio of the number of direct parents which include the knob KP to the number of direct parents.
26. The system of claim 24 , wherein the selection means comprises:
means for selecting a probability p2;
means for randomly selecting a number x2;
means for selecting the synthesized value for knob KP from among the at least one value of knob KP in the direct parents if x2 is greater than p2; and
means for performing the following steps if x2 is not greater than p2: (i) identifying a range RP of values of knob KP in the direct parents; and (ii) selecting the synthesized value for knob KP from within the range RP.
27. The system of claim 26 , further comprising:
means for expanding the range RP to generate an expanded range RE; and
wherein the selecting the synthesized value for knob KP from within the range RP comprises means for selecting the synthesized value for knob KP from within the expanded range RE.
28. The system of claim 23 , wherein the circuit design comprises a microprocessor design and wherein the plurality of circuit input vectors comprises a plurality of test instructions for execution on the microprocessor design.
29. In a system including a circuit design and a plurality of configuration files, the plurality of configuration files including a plurality of knobs having a plurality of values specifying a plurality of probability distributions of a plurality of circuit input vectors, a method comprising steps of:
(A) generating a first synthesized configuration file based on the plurality of configuration files, the first synthesized configuration file specifying a first synthesized probability distribution of a first subset of the plurality of circuit input vectors;
(B) using the first synthesized configuration file to generate a first test case comprising the first subset of the plurality of circuit input vectors;
(C) providing the first subset of the plurality of circuit input vectors as inputs to the circuit design;
(D) generating a fitness value based on at least one event counter in the microprocessor design, the at least one event counter comprising a count of at least one occurrence of at least one event in the microprocessor design in response to provision of the first subset of the plurality of circuit input vectors;
(E) generating a graded configuration file including the synthesized configuration file and the fitness value; and
(F) adding the graded configuration file to the plurality of configuration files.
30. The method of claim 29 , further comprising steps of:
(G) after the step (F), generating a second synthesized configuration file based on the plurality of configuration files, the second synthesized configuration file specifying a second synthesized probability distribution of a second subset of the plurality of circuit input vectors;
(H) using the second synthesized configuration file to generate a second test case comprising the second subset of the plurality of circuit input vectors; and
(I) providing the second subset of the plurality of circuit input vectors as inputs to the circuit design.
31. The method of claim 29 , wherein the circuit design comprises a microprocessor design and wherein the plurality of circuit input vectors comprises a plurality of test instructions for execution on the microprocessor design.
32. A system comprising:
a circuit design;
a plurality of configuration files, the plurality of configuration files including a plurality of knobs having a plurality of values specifying a plurality of probability distributions of a plurality of circuit input vectors;
means for generating a first synthesized configuration file based on the plurality of configuration files, the first synthesized configuration file specifying a first synthesized probability distribution of a first subset of the plurality of circuit input vectors;
means for using the first synthesized configuration file to generate a first test case comprising the first subset of the plurality of circuit input vectors;
means for providing the first subset of the plurality of circuit input vectors as inputs to the circuit design;
means for generating a fitness value based on at least one event counter in the microprocessor design, the at least one event counter comprising a count of at least one occurrence of at least one event in the microprocessor design in response to provision of the first subset of the plurality of circuit input vectors;
means for generating a graded configuration file including the synthesized configuration file and the fitness value; and
means for adding the graded configuration file to the plurality of configuration files.
33. The system of claim 32 , further comprising:
means for generating a second synthesized configuration file based on the plurality of configuration files, the second synthesized configuration file specifying a second synthesized probability distribution of a second subset of the plurality of circuit input vectors;
means for using the second synthesized configuration file to generate a second test case comprising the second subset of the plurality of circuit input vectors; and
means for providing the second subset of the plurality of circuit input vectors as inputs to the circuit design.
34. The system of claim 32 , wherein the circuit design comprises a microprocessor design and wherein the plurality of circuit input vectors comprises a plurality of test instructions for execution on the microprocessor design.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/141,480 US20050223346A1 (en) | 2002-07-16 | 2005-05-31 | Random code generation using genetic algorithms |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/195,993 US6918098B2 (en) | 2002-07-16 | 2002-07-16 | Random code generation using genetic algorithms |
US11/141,480 US20050223346A1 (en) | 2002-07-16 | 2005-05-31 | Random code generation using genetic algorithms |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/195,993 Division US6918098B2 (en) | 2002-07-16 | 2002-07-16 | Random code generation using genetic algorithms |
Publications (1)
Publication Number | Publication Date |
---|---|
US20050223346A1 true US20050223346A1 (en) | 2005-10-06 |
Family
ID=27757344
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/195,993 Expired - Fee Related US6918098B2 (en) | 2002-07-16 | 2002-07-16 | Random code generation using genetic algorithms |
US11/141,480 Abandoned US20050223346A1 (en) | 2002-07-16 | 2005-05-31 | Random code generation using genetic algorithms |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/195,993 Expired - Fee Related US6918098B2 (en) | 2002-07-16 | 2002-07-16 | Random code generation using genetic algorithms |
Country Status (2)
Country | Link |
---|---|
US (2) | US6918098B2 (en) |
GB (1) | GB2390919A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8438000B2 (en) | 2009-11-29 | 2013-05-07 | International Business Machines Corporation | Dynamic generation of tests |
US9117023B2 (en) | 2009-11-29 | 2015-08-25 | International Business Machines Corporation | Dynamic generation of test segments |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6894762B1 (en) * | 2002-09-17 | 2005-05-17 | Lsi Logic Corporation | Dual source lithography for direct write application |
US7065676B1 (en) * | 2002-12-27 | 2006-06-20 | Unisys Corporation | Multi-threaded memory management test system with feedback to adjust input parameters in response to performance |
US7051301B2 (en) * | 2003-10-01 | 2006-05-23 | Hewlett-Packard Development Company, L.P. | System and method for building a test case including a summary of instructions |
US7574341B1 (en) * | 2003-11-12 | 2009-08-11 | Hewlett-Packard Development Company, L.P. | Speculative expectation based event verification |
US7548068B2 (en) * | 2004-11-30 | 2009-06-16 | Intelliserv International Holding, Ltd. | System for testing properties of a network |
US7644399B2 (en) * | 2004-12-03 | 2010-01-05 | Arm Limited | Forming an executable program from a list of program instructions |
US7444271B2 (en) * | 2004-12-03 | 2008-10-28 | Arm Limited | Scoring mechanism for automatically generated test programs |
US20060136783A1 (en) * | 2004-12-03 | 2006-06-22 | Arm Limited | Automatically reducing test program size |
US20060195681A1 (en) * | 2004-12-06 | 2006-08-31 | Arm Limited | Test program instruction generation |
US20060150154A1 (en) * | 2004-12-06 | 2006-07-06 | Arm Limited | Test program instruction generation |
US7373550B2 (en) * | 2005-02-03 | 2008-05-13 | Arm Limited | Generation of a computer program to test for correct operation of a data processing apparatus |
US20060184914A1 (en) * | 2005-02-17 | 2006-08-17 | Microsoft Corporation | Random code generation |
EP1814025A1 (en) | 2006-01-18 | 2007-08-01 | Microsoft Corporation | Random code generation |
US8001473B1 (en) * | 2008-01-18 | 2011-08-16 | Adobe Systems Incorporated | Methods and systems for generating a composition |
US8391421B2 (en) * | 2008-06-19 | 2013-03-05 | Simon Fraser University | EDA-based detection of communication signals |
US20110191129A1 (en) * | 2010-02-04 | 2011-08-04 | Netzer Moriya | Random Number Generator Generating Random Numbers According to an Arbitrary Probability Density Function |
US11609935B2 (en) * | 2020-07-16 | 2023-03-21 | Red Hat, Inc. | Managing configuration datasets from multiple, distinct computing systems |
US11507393B2 (en) * | 2020-09-16 | 2022-11-22 | Red Hat, Inc. | Facilitating automatic deployment and configuration of computing environments |
Citations (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3719885A (en) * | 1971-12-13 | 1973-03-06 | Ibm | Statistical logic test system having a weighted random test pattern generator |
US4697242A (en) * | 1984-06-11 | 1987-09-29 | Holland John H | Adaptive computing system capable of learning and discovery |
US5136686A (en) * | 1990-03-28 | 1992-08-04 | Koza John R | Non-linear genetic algorithms for solving problems by finding a fit composition of functions |
US5202889A (en) * | 1990-04-18 | 1993-04-13 | International Business Machines Corporation | Dynamic process for the generation of biased pseudo-random test patterns for the functional verification of hardware designs |
US5245550A (en) * | 1991-01-25 | 1993-09-14 | Hitachi, Ltd. | Apparatus for wire routing of VLSI |
US5323400A (en) * | 1991-09-09 | 1994-06-21 | Northern Telecom Limited | Scan cell for weighted random pattern generation and method for its operation |
US5488573A (en) * | 1993-09-02 | 1996-01-30 | Matsushita Electric Industrial Co., Ltd. | Method for generating test programs |
US5490249A (en) * | 1992-12-23 | 1996-02-06 | Taligent, Inc. | Automated testing system |
US5526517A (en) * | 1992-05-15 | 1996-06-11 | Lsi Logic Corporation | Concurrently operating design tools in an electronic computer aided design system |
US5542043A (en) * | 1994-10-11 | 1996-07-30 | Bell Communications Research, Inc. | Method and system for automatically generating efficient test cases for systems having interacting elements |
US5572666A (en) * | 1995-03-28 | 1996-11-05 | Sun Microsystems, Inc. | System and method for generating pseudo-random instructions for design verification |
US5646949A (en) * | 1996-06-04 | 1997-07-08 | Motorola, Inc. | Method and apparatus for generating instructions for use in testing a microprocessor |
US5708774A (en) * | 1996-07-23 | 1998-01-13 | International Business Machines Corporation | Automated testing of software application interfaces, object methods and commands |
US5729554A (en) * | 1996-10-01 | 1998-03-17 | Hewlett-Packard Co. | Speculative execution of test patterns in a random test generator |
US5754760A (en) * | 1996-05-30 | 1998-05-19 | Integrity Qa Software, Inc. | Automatic software testing tool |
US5764857A (en) * | 1994-08-02 | 1998-06-09 | Honda Giken Kogyo Kabushiki Kaisha | Method of and apparatus for generating program |
US5774726A (en) * | 1995-04-24 | 1998-06-30 | Sun Microsystems, Inc. | System for controlled generation of assembly language instructions using assembly language data types including instruction types in a computer language as input to compiler |
US5819074A (en) * | 1996-12-05 | 1998-10-06 | Hewlett-Packard Co. | Method of eliminating unnecessary code generation in a circuit compiler |
US5880975A (en) * | 1996-12-05 | 1999-03-09 | Hewlett-Packard, Co. | Method of producing simplified code from a circuit compiler |
US5913023A (en) * | 1997-06-30 | 1999-06-15 | Siemens Corporate Research, Inc. | Method for automated generation of tests for software |
US5956477A (en) * | 1996-11-25 | 1999-09-21 | Hewlett-Packard Company | Method for processing information in a microprocessor to facilitate debug and performance monitoring |
US5956478A (en) * | 1995-09-11 | 1999-09-21 | Digital Equipment Corporation | Method for generating random test cases without causing infinite loops |
US5958072A (en) * | 1997-01-13 | 1999-09-28 | Hewlett-Packard Company | Computer-system processor-to-memory-bus interface having repeating-test-event generation hardware |
US6058385A (en) * | 1988-05-20 | 2000-05-02 | Koza; John R. | Simultaneous evolution of the architecture of a multi-part program while solving a problem using architecture altering operations |
US6088510A (en) * | 1992-07-02 | 2000-07-11 | Thinking Machines Corporation | Computer system and method for generating and mutating objects by iterative evolution |
US6212493B1 (en) * | 1998-12-01 | 2001-04-03 | Compaq Computer Corporation | Profile directed simulation used to target time-critical crossproducts during random vector testing |
US6253344B1 (en) * | 1998-10-29 | 2001-06-26 | Hewlett Packard Company | System and method for testing a microprocessor with an onboard test vector generator |
US6349393B1 (en) * | 1999-01-29 | 2002-02-19 | International Business Machines Corporation | Method and apparatus for training an automated software test |
US6374367B1 (en) * | 1997-11-26 | 2002-04-16 | Compaq Computer Corporation | Apparatus and method for monitoring a computer system to guide optimization |
US6381740B1 (en) * | 1997-09-16 | 2002-04-30 | Microsoft Corporation | Method and system for incrementally improving a program layout |
US20020065640A1 (en) * | 2000-11-30 | 2002-05-30 | Ramsey Clinton M. | Method and apparatus for generating transaction-based stimulus for simulation of VLSI circuits using event coverage analysis |
US6574727B1 (en) * | 1999-11-04 | 2003-06-03 | International Business Machines Corporation | Method and apparatus for instruction sampling for performance monitoring and debug |
US6625501B2 (en) * | 1996-05-06 | 2003-09-23 | Pavilion Technologies, Inc. | Kiln thermal and combustion control |
US20030188268A1 (en) * | 2002-03-15 | 2003-10-02 | Sun Microsystems, Inc. | Low Vt transistor substitution in a semiconductor device |
US6691080B1 (en) * | 1999-03-23 | 2004-02-10 | Kabushiki Kaisha Toshiba | Task execution time estimating method |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5978358A (en) * | 1996-10-01 | 1999-11-02 | Nortel Networks Corporation | Method for determining network switch capacity |
-
2002
- 2002-07-16 US US10/195,993 patent/US6918098B2/en not_active Expired - Fee Related
-
2003
- 2003-07-07 GB GB0315869A patent/GB2390919A/en not_active Withdrawn
-
2005
- 2005-05-31 US US11/141,480 patent/US20050223346A1/en not_active Abandoned
Patent Citations (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3719885A (en) * | 1971-12-13 | 1973-03-06 | Ibm | Statistical logic test system having a weighted random test pattern generator |
US4697242A (en) * | 1984-06-11 | 1987-09-29 | Holland John H | Adaptive computing system capable of learning and discovery |
US6058385A (en) * | 1988-05-20 | 2000-05-02 | Koza; John R. | Simultaneous evolution of the architecture of a multi-part program while solving a problem using architecture altering operations |
US5136686A (en) * | 1990-03-28 | 1992-08-04 | Koza John R | Non-linear genetic algorithms for solving problems by finding a fit composition of functions |
US5202889A (en) * | 1990-04-18 | 1993-04-13 | International Business Machines Corporation | Dynamic process for the generation of biased pseudo-random test patterns for the functional verification of hardware designs |
US5245550A (en) * | 1991-01-25 | 1993-09-14 | Hitachi, Ltd. | Apparatus for wire routing of VLSI |
US5323400A (en) * | 1991-09-09 | 1994-06-21 | Northern Telecom Limited | Scan cell for weighted random pattern generation and method for its operation |
US5526517A (en) * | 1992-05-15 | 1996-06-11 | Lsi Logic Corporation | Concurrently operating design tools in an electronic computer aided design system |
US6088510A (en) * | 1992-07-02 | 2000-07-11 | Thinking Machines Corporation | Computer system and method for generating and mutating objects by iterative evolution |
US5490249A (en) * | 1992-12-23 | 1996-02-06 | Taligent, Inc. | Automated testing system |
US5488573A (en) * | 1993-09-02 | 1996-01-30 | Matsushita Electric Industrial Co., Ltd. | Method for generating test programs |
US5764857A (en) * | 1994-08-02 | 1998-06-09 | Honda Giken Kogyo Kabushiki Kaisha | Method of and apparatus for generating program |
US5542043A (en) * | 1994-10-11 | 1996-07-30 | Bell Communications Research, Inc. | Method and system for automatically generating efficient test cases for systems having interacting elements |
US5572666A (en) * | 1995-03-28 | 1996-11-05 | Sun Microsystems, Inc. | System and method for generating pseudo-random instructions for design verification |
US5774726A (en) * | 1995-04-24 | 1998-06-30 | Sun Microsystems, Inc. | System for controlled generation of assembly language instructions using assembly language data types including instruction types in a computer language as input to compiler |
US5956478A (en) * | 1995-09-11 | 1999-09-21 | Digital Equipment Corporation | Method for generating random test cases without causing infinite loops |
US6625501B2 (en) * | 1996-05-06 | 2003-09-23 | Pavilion Technologies, Inc. | Kiln thermal and combustion control |
US5754760A (en) * | 1996-05-30 | 1998-05-19 | Integrity Qa Software, Inc. | Automatic software testing tool |
US5646949A (en) * | 1996-06-04 | 1997-07-08 | Motorola, Inc. | Method and apparatus for generating instructions for use in testing a microprocessor |
US5708774A (en) * | 1996-07-23 | 1998-01-13 | International Business Machines Corporation | Automated testing of software application interfaces, object methods and commands |
US5729554A (en) * | 1996-10-01 | 1998-03-17 | Hewlett-Packard Co. | Speculative execution of test patterns in a random test generator |
US5956477A (en) * | 1996-11-25 | 1999-09-21 | Hewlett-Packard Company | Method for processing information in a microprocessor to facilitate debug and performance monitoring |
US5880975A (en) * | 1996-12-05 | 1999-03-09 | Hewlett-Packard, Co. | Method of producing simplified code from a circuit compiler |
US5819074A (en) * | 1996-12-05 | 1998-10-06 | Hewlett-Packard Co. | Method of eliminating unnecessary code generation in a circuit compiler |
US5958072A (en) * | 1997-01-13 | 1999-09-28 | Hewlett-Packard Company | Computer-system processor-to-memory-bus interface having repeating-test-event generation hardware |
US5913023A (en) * | 1997-06-30 | 1999-06-15 | Siemens Corporate Research, Inc. | Method for automated generation of tests for software |
US6381740B1 (en) * | 1997-09-16 | 2002-04-30 | Microsoft Corporation | Method and system for incrementally improving a program layout |
US6374367B1 (en) * | 1997-11-26 | 2002-04-16 | Compaq Computer Corporation | Apparatus and method for monitoring a computer system to guide optimization |
US6253344B1 (en) * | 1998-10-29 | 2001-06-26 | Hewlett Packard Company | System and method for testing a microprocessor with an onboard test vector generator |
US6212493B1 (en) * | 1998-12-01 | 2001-04-03 | Compaq Computer Corporation | Profile directed simulation used to target time-critical crossproducts during random vector testing |
US6349393B1 (en) * | 1999-01-29 | 2002-02-19 | International Business Machines Corporation | Method and apparatus for training an automated software test |
US6691080B1 (en) * | 1999-03-23 | 2004-02-10 | Kabushiki Kaisha Toshiba | Task execution time estimating method |
US6574727B1 (en) * | 1999-11-04 | 2003-06-03 | International Business Machines Corporation | Method and apparatus for instruction sampling for performance monitoring and debug |
US20020065640A1 (en) * | 2000-11-30 | 2002-05-30 | Ramsey Clinton M. | Method and apparatus for generating transaction-based stimulus for simulation of VLSI circuits using event coverage analysis |
US20030188268A1 (en) * | 2002-03-15 | 2003-10-02 | Sun Microsystems, Inc. | Low Vt transistor substitution in a semiconductor device |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8438000B2 (en) | 2009-11-29 | 2013-05-07 | International Business Machines Corporation | Dynamic generation of tests |
US9117023B2 (en) | 2009-11-29 | 2015-08-25 | International Business Machines Corporation | Dynamic generation of test segments |
Also Published As
Publication number | Publication date |
---|---|
GB0315869D0 (en) | 2003-08-13 |
US20040015791A1 (en) | 2004-01-22 |
GB2390919A (en) | 2004-01-21 |
US6918098B2 (en) | 2005-07-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20050223346A1 (en) | Random code generation using genetic algorithms | |
Vasudevan et al. | Goldmine: Automatic assertion generation using data mining and static analysis | |
US7428715B2 (en) | Hole query for functional coverage analysis | |
Jyu et al. | Statistical timing analysis of combinational logic circuits | |
Corno et al. | Testability analysis and ATPG on behavioral RT-level VHDL | |
JP2549266B2 (en) | Method and apparatus for debugging digital circuit design | |
US6308299B1 (en) | Method and system for combinational verification having tight integration of verification techniques | |
Chen et al. | Simulation knowledge extraction and reuse in constrained random processor verification | |
US6567959B2 (en) | Method and device for verification of VLSI designs | |
US20050086565A1 (en) | System and method for generating a test case | |
US7155691B2 (en) | Apparatus and methods for compiled static timing analysis | |
Di Guglielmo et al. | Semi-formal functional verification by EFSM traversing via NuSMV | |
Plaza et al. | Node mergers in the presence of don't cares | |
US20070005533A1 (en) | Method and apparatus for improving efficiency of constraint solving | |
US7366951B2 (en) | Method and apparatus for test program generation based on an instruction set description of a processor | |
Damiano et al. | Checking satisfiability of a conjunction of BDDs | |
US7257786B1 (en) | Method and apparatus for solving constraints | |
Akkouche et al. | Analog/RF test ordering in the early stages of production testing | |
US7051301B2 (en) | System and method for building a test case including a summary of instructions | |
Habibi et al. | Efficient assertion based verification using TLM | |
Alladi et al. | Efficient selection of critical paths for delay defects in the presence of process variations | |
Fine et al. | Enhancing the control and efficiency of the covering process [logic verification] | |
Drechsler et al. | Genetic Alogrithms in Computer Aided Design of Integrated Circuits | |
US7454680B2 (en) | Method, system and computer program product for improving efficiency in generating high-level coverage data for a circuit-testing scheme | |
Ganai et al. | Rarity based guided state space search |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: EXPRESSLY ABANDONED -- DURING EXAMINATION |