US20050073803A1 - Methods of manufacturing integrated circuit devices that include a metal oxide layer disposed on another layer to protect the other layer from diffusion of impurities and integrated circuit devices manufactured using same - Google Patents

Methods of manufacturing integrated circuit devices that include a metal oxide layer disposed on another layer to protect the other layer from diffusion of impurities and integrated circuit devices manufactured using same Download PDF

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US20050073803A1
US20050073803A1 US10/967,835 US96783504A US2005073803A1 US 20050073803 A1 US20050073803 A1 US 20050073803A1 US 96783504 A US96783504 A US 96783504A US 2005073803 A1 US2005073803 A1 US 2005073803A1
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integrated circuit
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Hag-Ju Cho
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/55Capacitors with a dielectric comprising a perovskite structure material
    • H01L28/56Capacitors with a dielectric comprising a perovskite structure material the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314Inorganic layers
    • H01L21/316Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604Deposition from a gas or vapour
    • H01L21/31616Deposition of Al2O3
    • H01L21/3162Deposition of Al2O3 on a silicon body

Definitions

  • the present invention relates generally to methods of manufacturing integrated circuit devices and integrated circuit devices manufactured using same, and, more particularly, to reducing the diffusion of impurities, such as hydrogen, into integrated circuit device layers during manufacturing.
  • Ferroelectric capacitors may be used in integrated circuit memory devices. Specifically, non-volatile integrated circuit memory devices often make use of the remnant polarization (P r ) phenomenon of a ferroelectric layer, which corresponds to the concept of a binary memory. Two materials that are commonly used to form ferroelectric layers are PZT(Pb(Zr, Ti)O 3 ) and SBT(SrBi 2 Ta 2 O 9 ).
  • a potential problem in forming a capacitor dielectric layer using a ferroelectric material is that the ferroelectric characteristic of the material used for the capacitor dielectric layer maybe degraded during additional integration processes, which are performed after the formation of the ferroelectric capacitor. This potential problem is described in more detail hereinafter.
  • an InterLayer Dielectric (ILD) process In manufacturing an integrated circuit memory device, the following processes are typically performed after the formation of a capacitor: 1) an InterLayer Dielectric (ILD) process, 2) an InterMetal Dielectric (IMD) process, and 3) a passivation process.
  • impurities may be generated, such as hydrogen, which can degrade a capacitor dielectric layer.
  • the generated hydrogen may immediately infiltrate the capacitor dielectric layer during the foregoing processes or the hydrogen may gradually infiltrate the capacitor dielectric layer after the hydrogen has been introduced into an ILD layer, an IMD layer, or a passivation layer. As a result, the P r of the ferroelectric dielectric layer may decrease.
  • the dielectric layer of the capacitor may be degraded.
  • silane (SiH 4 ) gas and oxygen (O 2 ) gas may be used.
  • Hydrogen is generated as a by-product of the reaction between the silane gas and the oxygen gas. The generated hydrogen may immediately diffuse into the dielectric layer of the ferroelectric capacitor and degrade the dielectric layer, or may be introduced into an interlayer insulation layer formed from the ILD process and gradually degrade the capacitor dielectric layer.
  • the P r value of the capacitor dielectric layer may decrease to an extent that the capacitor dielectric layer may lose its ferroelectric characteristics.
  • a ferroelectric dielectric layer may be similarly degraded as a result of performing an IMD process for forming an intermetal insulation layer and/or performing a passivation process for forming a passivation layer.
  • an integrated circuit device is manufactured by exposing at least a portion of an insulation layer that comprises oxygen to a metal precursor that is reactive with oxygen so as to form a metal oxide layer on the portion of the insulation layer.
  • the metal oxide layer may reduce the diffusion of impurities, such as hydrogen, into the insulation layer, which may degrade the electrical characteristics of the insulation layer.
  • Exposing the portion of the insulation layer to the metal precursor may comprise pulsing the metal precursor over the integrated circuit device for about 0.1 to 2 seconds at a flow rate of about 50 to 300 sccm, and then exposing the integrated circuit device to an inert gas for a duration of about 0.1 to 10 seconds and at a flow rate of about 50 to 300 sccm.
  • the integrated circuit device may be thermally treated in an oxygen atmosphere using a rapid thermal processing apparatus or a furnace type thermal processing apparatus.
  • the thermal treatment may be performed at a temperature of about 400 to 600° C. for a duration of about 10 seconds to 10 minutes.
  • the metal precursor may comprise a gas selected from the following group of gases: TriMethyl Aluminum (TMA), DiMethylAluminum Hydride (DMAH), DiMethylEthylAmine Alane (DMEAA), TriIsoButylAluminum (TIBA), TriEthyl Aluminum (TEA), TaCl 5 , Ta(OC 2 H 5 ) 4 ,TiCl 4 , Ti(OC 2 H 5 ) 4 , ZrCl 4 , HfCl 4 , Nb(OC 2 H 5 ) 5 , Mg(thd) 2 , Ce(thd) 3 , and Y(thd) 3 , wherein thd is given by the following structural formula:
  • the insulation layer may comprise a capacitor dielectric layer and/or may comprise a material selected from the following group of materials: TiO 2 , SiO 2 , Ta 2 O 5 , Al 2 O 3 , BaTiO 3 , SrTiO 3 , (Ba, Sr)TiO 3 , Bi 4 Ti 3 O 12 , PbTiO 3 , PZT((Pb, La)(Zr, Ti)O 3 ), and (SrBi 2 Ta 2 O 9 )(SBT).
  • a second metal oxide layer may be disposed on the insulation layer and the first metal oxide layer to further reduce the diffusion of impurities, such as hydrogen, into the insulation layer due to subsequent integration processing operations.
  • the second metal oxide layer may be formed by pulsing a second metal precursor over the integrated circuit device, exposing the integrated circuit device to an inert gas, pulsing oxygen gas over the integrated circuit device, and then exposing the integrated circuit device to an inert gas.
  • the second metal oxide layer may be denser than the first metal oxide layer.
  • FIGS. 1-4 are cross-section views that illustrate methods of manufacturing integrated circuit devices that include a metal oxide layer to reduce the diffusion of impurities and integrated circuit devices manufactured using same in accordance with various embodiments of the present invention
  • FIG. 5 is a graph that illustrates a result of analyzing an integrated circuit device manufactured in accordance with an embodiment of the present invention using X-ray photoelectron spectroscopy (XPS); and
  • FIG. 6 is a graph that illustrates remnant polarization values of ferroelectric dielectric layers in integrated circuit devices manufactured in accordance with embodiments of the present invention.
  • a capacitor C is formed on a semiconductor substrate S.
  • the capacitor C comprises a lower electrode 100 , a capacitor dielectric layer 110 , and an upper electrode 120 , which are sequentially stacked as shown.
  • the semiconductor substrate S comprises a device isolation layer 130 for defining an active region; a field effect transistor T, which comprises a gate electrode 160 , an underlying gate oxide layer 140 interposed between the gate electrode 160 and the semiconductor substrate S, nitride spacers 150 disposed on the sidewalls of the gate electrode 160 , and source and drain regions 170 and 171 ; an interlayer insulation layer 180 on the device isolation layer 130 and the field effect transistor T; and a contact plug 190 formed in the interlayer insulation layer 180 and electrically connected to the source region 170 .
  • a field effect transistor T which comprises a gate electrode 160 , an underlying gate oxide layer 140 interposed between the gate electrode 160 and the semiconductor substrate S, nitride spacers 150 disposed on the sidewalls of the gate electrode 160 , and source and drain regions 170 and 171 ; an interlayer insulation layer 180 on the device isolation layer 130 and the field effect transistor T; and a contact plug 190 formed in the interlayer insulation layer 180 and electrically connected to the source region 170 .
  • the semiconductor substrate S may be prepared by conventional methods. Although not shown, other elements besides the above-mentioned elements may be provided on the semiconductor substrate S.
  • an interface layer may be interposed between the interlayer insulation layer 180 and the lower electrode 100 , and between the contact plug 190 and the lower electrode 100 .
  • the interface layer may include an adhesive layer and a diffusion-preventing layer, which are sequentially stacked.
  • the adhesive layer may comprise a material layer for enhancing the adhesive strength between the interlayer insulation layer 180 and the diffusion preventing layer, and between the contact plug 190 and the diffusion preventing layer.
  • the adhesive layer may be a transition metal layer (e.g., a Ti layer).
  • the diffusion preventing layer may prevent a material layer formed on the interface layer from reacting with the contact plug 190 during subsequent processing and may also prevent the contact plug 190 from degrading due to the diffusion of oxygen during subsequent processing performed in an oxygen atmosphere.
  • the diffusion-preventing layer may be a nitride layer (e.g., a TiN layer) of a transition metal.
  • a capping insulation layer comprising a nitride layer may be formed on the surface of the gate electrode 160 .
  • the lower electrode 100 and the upper electrode 120 may each be, for example, a metal layer, a conductive metal oxide layer, or a compound of a metal layer and a metal oxide layer.
  • the metal layer may be, for example, a Pt layer, a Ir layer, a Ru layer, a Rh layer, a Os layer, or a Pd layer.
  • the conductive metal oxide layer may be, for example, a IrO 2 layer, a RuO 2 layer, a (Ca, Sr)RuO 3 layer, or a LaSrCoO 3 layer.
  • the lower electrode 100 may be a Pt layer
  • the upper electrode 120 may be a double layer in which an IrO 2 layer and an Ir layer are sequentially stacked.
  • the capacitor dielectric layer 110 may be a TiO 2 layer, a SiO 2 layer, a Ta 2 O 5 layer, a Al 2 O 3 layer, a BaTiO 3 layer, a SrTiO 3 layer, a (Ba, Sr)TiO 3 layer, a Bi 4 Ti 3 O 12 layer, a PbTiO 3 layer, a PZT((Pb, La)(Zr, Ti)O 3 ) layer, a (SrBi 2 Ta 2 O 9 )(SBT) layer, or a compound layer of two or more of the foregoing materials.
  • FIG. 2 an enlarged view of portion II of FIG. 1 is shown in which a metal oxide layer, such as an Al 2 O 3 layer, is selectively formed on the capacitor dielectric layer 110 in accordance with embodiments of the present invention.
  • the semiconductor substrate S is loaded in atomic layer deposition equipment (not shown) and is heated to a temperature of about 100-400° C., preferably, about 300° C., under a state in which the pressure of a reaction chamber is maintained at about 0.1-1 torr.
  • a metal precursor gas as a pulsing gas, which is reactive with oxygen, and an inert gas as a purge gas.
  • a metal precursor such as an aluminum precursor
  • the aluminum precursor may be TriMethyl Aluminum (TMA), DiMethyLAluminum Hydride (DMAH), DiMethylEthylAmine Alane (DMEAA), TriIsoButylAluminum (TIBA), TriEthyl Aluminum (TEA), or a mixture of two or more of the foregoing gases.
  • the pulsing time may be about 0.1-2 seconds and the pulsing flow rate may be about 50-300 sccm.
  • the aluminum precursor is preferably pulsed together with a carrier gas such as argon gas.
  • TaCl 5 or Ta(OC 2 H 5 ) 4 may be used as a tantalum precursor; TiCl 4 or Ti(OC 2 H 5 ) 4 may be used as a titanium precursor; ZrCl 4 may be used as a zirconium precursor; HfCl 4 may be used as a hafnium precursor; Nb(OC 2 H 5 ) 5 may be used as a niobium precursor; Mg(thd) 2 may be used as a magnesium precursor; Ce(thd) 3 may be used as a cerium precursor; and Y(thd) 3 may be used as a yttrium precursor.
  • the structural formula of “thd” is as follows:
  • the pulsed aluminum precursor is chemically or physically adsorbed by the surface of the semiconductor substrate S. Because the aluminum precursor is reactive with oxygen, it tends to change into an Al 2 O 3 layer at the adsorption interface when it is adsorbed by a material layer containing oxygen.
  • the exposed surface of the capacitor dielectric layer 110 may chemically adsorb the aluminum precursor as structural atoms react with the oxygen contained in the capacitor dielectric layer 110 .
  • an Al 2 O 3 layer 200 is selectively formed on the exposed surface of the capacitor dielectric layer 110 at an atomic layer level.
  • the aluminum precursor that is chemically or physically adsorbed by the exposed portions of the upper and lower electrodes 120 and 100 generally does not change into a metal oxide layer.
  • the upper and/or lower electrodes 120 or 100 include a conductive metal oxide layer, such as an IrO 2 layer, an Al 2 O 3 layer may be formed on the exposed portion of the conductive metal oxide layer at an atomic layer level.
  • the surface of the semiconductor substrate S is purged using inert gas.
  • the inert gas may be argon gas, and the purging time and flow rate of the inert gas may be about 0.5-10 seconds and about 50-300 sccm, respectively.
  • the aluminum precursor chemically adsorbed by surfaces of the lower electrode 100 and the upper electrode 120 is generally not purged and mostly remains.
  • the purge time and flow rate of the inert gas may be adjusted to substantially remove the metal precursor adsorbed by the surfaces of the upper electrode 120 and the lower electrode 100 .
  • the aluminum precursor pulsing operation and the inert gas purging operation constitute a single cycle of the atomic layer deposition process.
  • the cycle may be repeated until an Al 2 O 3 layer 200 ′ having a desired thickness is obtained.
  • an aluminum precursor reacts with oxygen atoms contained in the capacitor dielectric layer 110 through diffusion so that the Al 2 O 3 layer 200 ′ is continuously formed on the capacitor dielectric layer 110 at an atomic layer level.
  • the aluminum precursor is adsorbed by surfaces of the upper electrode 120 and the lower electrode 100 , and an Al 2 O 3 layer is generally not formed thereon.
  • An aluminum precursor usually contains hydrogen atoms. Accordingly, during a process of selectively forming an Al 2 O 3 layer on the capacitor dielectric layer 110 , in accordance with embodiments of the present invention, the dielectric characteristics of the capacitor dielectric layer 110 may be degraded. In particular, when the capacitor dielectric layer 110 is formed of a ferroelectric material such as a PZT layer or a SBT layer, the ferroelectric characteristics of the capacitor dielectric layer 110 may be degraded due to diffusion of hydrogen contained in the aluminum precursor. For example, the remnant polarization value of the capacitor dielectric layer 110 may decrease.
  • thermal treatment may be performed in an oxygen atmosphere after the Al 2 O 3 layer is formed on the capacitor dielectric layer 110 to a desired thickness.
  • the thermal treatment may be performed in a rapid thermal processing apparatus or a furnace type thermal processing apparatus.
  • the temperature may be about 400-600° C. and the treatment may be performed for about 10 seconds to about 10 minutes.
  • an encapsulating layer 210 is formed on the surface of the semiconductor substrate S and the capacitor C.
  • the encapsulating layer 210 may comprise a metal oxide and may prevent hydrogen from diffusing into the capacitor dielectric layer 110 during a subsequent InterLayer Dielectric (ILD) process, InterMetal Dielectric (IMD) process, and/or passivation process.
  • the encapsulating layer 210 may have a density associated therewith that is greater than the density of the layer 200 ′. Because the semiconductor substrate S on which the encapsulating layer 210 is formed has the capacitor C on the surface thereof, it has a generally large surface topology. Accordingly, the encapsulating layer is preferably formed using an atomic layer deposition method.
  • a single cycle for forming the encapsulating layer 210 as an Al 2 O 3 layer may comprise the following operations: 1) pulsing aluminum source gas over the surface of the semiconductor substrate S, 2) purging with inert gas, 3) pulsing oxygen source gas, and 4) purging with inert gas. The cycle is repeated until the encapsulating layer 210 reaches a desired thickness.
  • One of the aluminum precursors discussed above may be used as the aluminum source gas.
  • H 2 O gas, O 3 gas or N 2 O gas may be used as the oxygen source gas.
  • Argon gas may be used as the inert gas.
  • the pulsing time of the TMA gas may be about 0.1-2 seconds
  • the pulsing time of the H 2 O gas may be about 0.1-2 seconds
  • the purging time and flow rate of the argon gas may be about 1-10 seconds and about 50-300 sccm, respectively
  • the temperature of the semiconductor substrate S may be about 300° C.
  • an Al 2 O 3 layer is selectively formed on a capacitor dielectric layer 110 that may reduce diffusion of impurities into the dielectric layer 110 .
  • the layer 200 ′ and the encapsulating layer 210 may comprise Ta, Ti, Zr, Mg, Ce, Y, Nb, Hf, Sr, or Ca.
  • a metal precursor containing Ta, Ti, Zr, Mg, Ce, Y, Nb, Hf, Sr or Ca may be used in the aluminum precursor pulsing operation of the first embodiment.
  • an integrated circuit devices comprises a semiconductor substrate S, a conductive region 220 , which contains little or no oxygen, an interlayer insulation layer 230 , which is disposed on the conductive region 220 and contains oxygen, and an opening 240 , which exposes the conductive region 220 .
  • the conductive region 220 may be the upper or lower electrode of a capacitor, a gate electrode, a bit line, a word line, or the lower conductive line of a multi-layered interconnection layer.
  • the interlayer insulation layer 230 may be a silicon oxide layer or a silicon oxynitride layer.
  • a metal oxide layer 250 (e.g., an Al 2 O 3 layer) is selectively formed on the exposed surface of the interlayer insulation layer 230 using atomic layer deposition as discussed hereinabove with respect to FIGS. 1-3 .
  • the oxide layer may comprise alternative metals, such as Ta, Ti, Zr, Mg, Ce, Y, Nb, Hf, Sr, or Ca.
  • a thermal treatment may be performed in an oxygen atmosphere after the metal oxide layer 250 is selectively formed to enhance the dielectric characteristic of the metal oxide layer 250 .
  • the metal oxide layer 250 When the metal oxide layer 250 is selectively formed exclusively on the exposed surface of the interlayer insulation layer 230 , the metal oxide layer 250 can inhibit substances that can degrade a semiconductor device by diffusing to structures below the metal oxide layer 250 during subsequent processes of forming material layer(s) on the interlayer insulation layer 230 . Examples of integrated circuit devices formed in accordance with embodiments of the present invention are described hereafter.
  • a capacitor in which a Pt layer (a lower electrode), a PZT layer (a capacitor dielectric layer), and an Ir/IrO 2 layer (an upper electrode) were sequentially stacked, was formed on a semiconductor substrate. Thereafter, the semiconductor substrate was loaded in an atomic layer deposition apparatus, and a stabilizing step was performed such that the pressure of a chamber was maintained at about 0.1-1 torr, and the temperature of the semiconductor substrate was maintained at about 300° C. Next, an atomic layer deposition process cycle, as discussed above with respect to FIG. 2 , was repeated 100 times and a test sample was obtained. TMA gas was used as an aluminum precursor and the pulsing time in each cycle was about 0.1 second.
  • Argon gas was used as a purge gas, and the purging time in each cycle was about 1 second.
  • an X-ray photoelectron spectroscopy analysis was performed on the integrated circuit device to check whether an Al 2 O 3 layer was formed on the capacitor dielectric layer.
  • the result of the analysis is shown in FIG. 5 .
  • the horizontal axis denotes binding energy and the vertical axis denotes arbitrary intensity.
  • an aluminum 2p peak (see III) indicating binding energy between aluminum and oxygen may be observed. Accordingly, these results indicate that an Al 2 O 3 layer was selectively formed on the capacitor dielectric layer of the sample.
  • oxygen source gas was not pulsed, it can be inferred that the oxygen contained in the Al 2 O 3 layer was supplied by the capacitor dielectric layer.
  • a capacitor pattern was formed on a semiconductor substrate as discussed hereinabove with respect to FIGS. 1-3 and a Sample 1 and a Sample 2 were separately manufactured. Thereafter, the following operations were sequentially performed on the Samples 1 and 2, and the remnant polarization values of their capacitor dielectric layers were measured after completion of each operation. The results of the measurements are shown in FIG. 6 .
  • the horizontal axis denotes the operations performed on the Samples 1 and 2
  • the vertical axis denotes the remnant polarization values.
  • step A 1 an Al 2 O 3 layer was selectively formed on a capacitor dielectric layer as discussed hereinabove with respect to FIGS. 1-3 .
  • the process conditions of step A 1 were approximately the same as those used in Example 1.
  • step A 2 the semiconductor substrate was loaded in a rapid thermal processing apparatus and thermally treated for about 10 seconds at a temperature of about 700° C. in an oxygen atmosphere.
  • step A 3 an Al 2 O 3 layer that encapsulates the capacitor pattern was formed as discussed hereinabove with respect to FIGS. 1-3 .
  • TMA gas, H 2 O gas, and argon gas were used as the aluminum source gas, the oxygen source gas, and the purge gas, respectively.
  • the pulsing time of the TMA gas was about 0.5 seconds.
  • the pulsing time of the H 2 O gas was about 0.3 seconds.
  • the purging time and purging flow rate of the argon gas were about 6 seconds and about 150 sccm, respectively.
  • the temperature of the wafer was about 300° C.
  • step B 1 a semiconductor substrate including a capacitor disposed thereon was loaded in a rapid thermal processing apparatus and thermally treated.
  • the process conditions of step B 1 were the same as those of step A 2 .
  • step B 2 an Al 2 O 3 layer was formed that encapsulates the capacitor.
  • the process conditions of step B 2 were the same as those of step A 3 .
  • the remnant polarization value of the capacitor dielectric layer in Sample 1 decreases a little after step A 1 due to the influence of the TMA gas and the H 2 O gas, which contain hydrogen.
  • the remnant polarization value increases over the initial value after performing the rapid thermal process in an oxygen atmosphere in step A 2 .
  • the remnant polarization value decreases a little after encapsulating the capacitor in step A 3
  • the decreased remnant polarization value is almost the same as the initial value.
  • the remnant polarization value of the capacitor dielectric layer in Sample 1 rarely decreased even though TMA gas and H 2 O gas, which contain hydrogen, were used in step A 3 .
  • the remnant polarization value of the capacitor dielectric layer in Sample 2 increases over the initial value after performing a rapid thermal process in an oxygen atmosphere in step B 1 .
  • the remnant polarization value greatly decreases with respect to Sample 1, however, after encapsulating the capacitor in step B 2 .
  • Sample 1 is different from Sample 2 in that it has a selectively formed metal oxide layer that has been thermal-treated in an oxygen atmosphere.
  • the remnant polarization value in Sample 1 did not decrease even though Sample 1 had undergone Step A 3 in which hydrogen-base gas was supplied. This suggests that the thermal-treated metal oxide layer effectively reduced the diffusion of hydrogen into the capacitor dielectric layer. Accordingly, the thermal-treated metal oxide layer may reduce diffusion of hydrogen into the capacitor dielectric layer in subsequent ILD, IMD, and passivation processes.
  • a metal oxide layer may be selectively formed exclusively on an insulation layer containing oxygen.
  • the degradation of a capacitor dielectric layer may be reduced, even if a source gas containing hydrogen is used.
  • degradation of a capacitor dielectric layer due to diffusion of hydrogen during an ILD process, an IMD process, or a passivation process, which are performed after encapsulating the capacitor may be effectively reduced.

Abstract

Integrated circuit devices are manufactured by exposing at least a portion of an insulation layer that comprises oxygen to a metal precursor that is reactive with oxygen so as to form a metal oxide layer on the portion of the insulation layer. The metal oxide layer may reduce the diffusion of impurities, such as hydrogen, into the insulation layer, which may degrade the electrical characteristics of the insulation layer.

Description

    RELATED APPLICATION
  • This application claims the benefit of Korean Patent Application No. 00-35708, filed Jun. 27, 2000, the disclosure of which is hereby incorporated herein by reference.
  • 1. Field of the Invention
  • The present invention relates generally to methods of manufacturing integrated circuit devices and integrated circuit devices manufactured using same, and, more particularly, to reducing the diffusion of impurities, such as hydrogen, into integrated circuit device layers during manufacturing.
  • 2. Background of the Invention
  • Ferroelectric capacitors may be used in integrated circuit memory devices. Specifically, non-volatile integrated circuit memory devices often make use of the remnant polarization (Pr) phenomenon of a ferroelectric layer, which corresponds to the concept of a binary memory. Two materials that are commonly used to form ferroelectric layers are PZT(Pb(Zr, Ti)O3) and SBT(SrBi2 Ta2O9).
  • A potential problem in forming a capacitor dielectric layer using a ferroelectric material is that the ferroelectric characteristic of the material used for the capacitor dielectric layer maybe degraded during additional integration processes, which are performed after the formation of the ferroelectric capacitor. This potential problem is described in more detail hereinafter.
  • In manufacturing an integrated circuit memory device, the following processes are typically performed after the formation of a capacitor: 1) an InterLayer Dielectric (ILD) process, 2) an InterMetal Dielectric (IMD) process, and 3) a passivation process. During these processes, impurities may be generated, such as hydrogen, which can degrade a capacitor dielectric layer. The generated hydrogen may immediately infiltrate the capacitor dielectric layer during the foregoing processes or the hydrogen may gradually infiltrate the capacitor dielectric layer after the hydrogen has been introduced into an ILD layer, an IMD layer, or a passivation layer. As a result, the Pr of the ferroelectric dielectric layer may decrease.
  • For example, when an ILD process is used to form a silicon oxide interlayer insulation layer after a ferroelectric capacitor is formed on a semiconductor substrate, the dielectric layer of the capacitor may be degraded. In other words, in the process of forming a silicon oxide interlayer insulation layer using, for example, a plasma enhanced chemical vapor deposition (PECVD) method, silane (SiH4) gas and oxygen (O2) gas may be used. Hydrogen is generated as a by-product of the reaction between the silane gas and the oxygen gas. The generated hydrogen may immediately diffuse into the dielectric layer of the ferroelectric capacitor and degrade the dielectric layer, or may be introduced into an interlayer insulation layer formed from the ILD process and gradually degrade the capacitor dielectric layer. As a result, the Pr value of the capacitor dielectric layer may decrease to an extent that the capacitor dielectric layer may lose its ferroelectric characteristics. Unfortunately, a ferroelectric dielectric layer may be similarly degraded as a result of performing an IMD process for forming an intermetal insulation layer and/or performing a passivation process for forming a passivation layer.
  • SUMMARY OF THE INVENTION
  • According to embodiments of the present invention, an integrated circuit device is manufactured by exposing at least a portion of an insulation layer that comprises oxygen to a metal precursor that is reactive with oxygen so as to form a metal oxide layer on the portion of the insulation layer. The metal oxide layer may reduce the diffusion of impurities, such as hydrogen, into the insulation layer, which may degrade the electrical characteristics of the insulation layer.
  • Exposing the portion of the insulation layer to the metal precursor may comprise pulsing the metal precursor over the integrated circuit device for about 0.1 to 2 seconds at a flow rate of about 50 to 300 sccm, and then exposing the integrated circuit device to an inert gas for a duration of about 0.1 to 10 seconds and at a flow rate of about 50 to 300 sccm.
  • In accordance with further embodiments of the present invention, the integrated circuit device may be thermally treated in an oxygen atmosphere using a rapid thermal processing apparatus or a furnace type thermal processing apparatus. The thermal treatment may be performed at a temperature of about 400 to 600° C. for a duration of about 10 seconds to 10 minutes.
  • The metal precursor may comprise a gas selected from the following group of gases: TriMethyl Aluminum (TMA), DiMethylAluminum Hydride (DMAH), DiMethylEthylAmine Alane (DMEAA), TriIsoButylAluminum (TIBA), TriEthyl Aluminum (TEA), TaCl5, Ta(OC2H5)4,TiCl4, Ti(OC2H5)4, ZrCl4, HfCl4, Nb(OC2H5)5, Mg(thd)2, Ce(thd)3, and Y(thd)3, wherein thd is given by the following structural formula:
    Figure US20050073803A1-20050407-C00001
  • The insulation layer may comprise a capacitor dielectric layer and/or may comprise a material selected from the following group of materials: TiO2, SiO2, Ta2O5, Al2O3, BaTiO3, SrTiO3, (Ba, Sr)TiO3, Bi4Ti3O12, PbTiO3, PZT((Pb, La)(Zr, Ti)O3), and (SrBi2Ta2O9)(SBT).
  • A second metal oxide layer may be disposed on the insulation layer and the first metal oxide layer to further reduce the diffusion of impurities, such as hydrogen, into the insulation layer due to subsequent integration processing operations.
  • The second metal oxide layer may be formed by pulsing a second metal precursor over the integrated circuit device, exposing the integrated circuit device to an inert gas, pulsing oxygen gas over the integrated circuit device, and then exposing the integrated circuit device to an inert gas. In accordance with particular embodiments of the present invention, the second metal oxide layer may be denser than the first metal oxide layer.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • Other features of the present invention will be more readily understood from the following detailed description of specific embodiments thereof when read in conjunction with the accompanying drawings, in which:
  • FIGS. 1-4 are cross-section views that illustrate methods of manufacturing integrated circuit devices that include a metal oxide layer to reduce the diffusion of impurities and integrated circuit devices manufactured using same in accordance with various embodiments of the present invention;
  • FIG. 5 is a graph that illustrates a result of analyzing an integrated circuit device manufactured in accordance with an embodiment of the present invention using X-ray photoelectron spectroscopy (XPS); and
  • FIG. 6 is a graph that illustrates remnant polarization values of ferroelectric dielectric layers in integrated circuit devices manufactured in accordance with embodiments of the present invention.
  • DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
  • While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that there is no intent to limit the invention to the particular forms disclosed, but on the contrary, the invention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the claims. Like numbers refer to like elements throughout the description of the figures. It will also be understood that when an element, such as a layer, region, or substrate, is referred to as being “on” another element, it can be directly on the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.
  • Referring to FIGS. 1-3, methods of manufacturing integrated circuit devices that include a metal oxide layer to reduce the diffusion of impurities and integrated circuit devices manufactured using same, in accordance with embodiments of the present invention, will now be described. As shown in FIG. 1, a capacitor C is formed on a semiconductor substrate S. The capacitor C comprises a lower electrode 100, a capacitor dielectric layer 110, and an upper electrode 120, which are sequentially stacked as shown. The semiconductor substrate S comprises a device isolation layer 130 for defining an active region; a field effect transistor T, which comprises a gate electrode 160, an underlying gate oxide layer 140 interposed between the gate electrode 160 and the semiconductor substrate S, nitride spacers 150 disposed on the sidewalls of the gate electrode 160, and source and drain regions 170 and 171; an interlayer insulation layer 180 on the device isolation layer 130 and the field effect transistor T; and a contact plug 190 formed in the interlayer insulation layer 180 and electrically connected to the source region 170.
  • The semiconductor substrate S may be prepared by conventional methods. Although not shown, other elements besides the above-mentioned elements may be provided on the semiconductor substrate S. For example, an interface layer may be interposed between the interlayer insulation layer 180 and the lower electrode 100, and between the contact plug 190 and the lower electrode 100. The interface layer may include an adhesive layer and a diffusion-preventing layer, which are sequentially stacked. The adhesive layer may comprise a material layer for enhancing the adhesive strength between the interlayer insulation layer 180 and the diffusion preventing layer, and between the contact plug 190 and the diffusion preventing layer. For example, the adhesive layer may be a transition metal layer (e.g., a Ti layer). The diffusion preventing layer may prevent a material layer formed on the interface layer from reacting with the contact plug 190 during subsequent processing and may also prevent the contact plug 190 from degrading due to the diffusion of oxygen during subsequent processing performed in an oxygen atmosphere. For example, the diffusion-preventing layer may be a nitride layer (e.g., a TiN layer) of a transition metal. In addition, a capping insulation layer comprising a nitride layer may be formed on the surface of the gate electrode 160.
  • The lower electrode 100 and the upper electrode 120 may each be, for example, a metal layer, a conductive metal oxide layer, or a compound of a metal layer and a metal oxide layer. The metal layer may be, for example, a Pt layer, a Ir layer, a Ru layer, a Rh layer, a Os layer, or a Pd layer. The conductive metal oxide layer may be, for example, a IrO2 layer, a RuO2 layer, a (Ca, Sr)RuO3 layer, or a LaSrCoO3 layer. For example, the lower electrode 100 may be a Pt layer, and the upper electrode 120 may be a double layer in which an IrO2 layer and an Ir layer are sequentially stacked.
  • The capacitor dielectric layer 110 may be a TiO2 layer, a SiO2 layer, a Ta2O5 layer, a Al2O3 layer, a BaTiO3 layer, a SrTiO3 layer, a (Ba, Sr)TiO3 layer, a Bi4Ti3O12 layer, a PbTiO3 layer, a PZT((Pb, La)(Zr, Ti)O3) layer, a (SrBi2Ta2O9)(SBT) layer, or a compound layer of two or more of the foregoing materials.
  • Referring now to FIG. 2 an enlarged view of portion II of FIG. 1 is shown in which a metal oxide layer, such as an Al2O3 layer, is selectively formed on the capacitor dielectric layer 110 in accordance with embodiments of the present invention. The semiconductor substrate S is loaded in atomic layer deposition equipment (not shown) and is heated to a temperature of about 100-400° C., preferably, about 300° C., under a state in which the pressure of a reaction chamber is maintained at about 0.1-1 torr.
  • An atomic layer deposition process is then performed using a metal precursor gas as a pulsing gas, which is reactive with oxygen, and an inert gas as a purge gas. In more detail, a metal precursor, such as an aluminum precursor, is pulsed over the surface of the semiconductor substrate S. The aluminum precursor may be TriMethyl Aluminum (TMA), DiMethyLAluminum Hydride (DMAH), DiMethylEthylAmine Alane (DMEAA), TriIsoButylAluminum (TIBA), TriEthyl Aluminum (TEA), or a mixture of two or more of the foregoing gases. The pulsing time may be about 0.1-2 seconds and the pulsing flow rate may be about 50-300 sccm. The aluminum precursor is preferably pulsed together with a carrier gas such as argon gas.
  • Instead of using an aluminum precursor as the metal precursor for the atomic layer deposition process other gases may be used in accordance with embodiments of the present invention. For example, TaCl5 or Ta(OC2H5)4 may be used as a tantalum precursor; TiCl4 or Ti(OC2H5)4 may be used as a titanium precursor; ZrCl4 may be used as a zirconium precursor; HfCl4 may be used as a hafnium precursor; Nb(OC2H5)5 may be used as a niobium precursor; Mg(thd)2 may be used as a magnesium precursor; Ce(thd)3 may be used as a cerium precursor; and Y(thd)3 may be used as a yttrium precursor. The structural formula of “thd” is as follows:
    Figure US20050073803A1-20050407-C00002
  • The pulsed aluminum precursor is chemically or physically adsorbed by the surface of the semiconductor substrate S. Because the aluminum precursor is reactive with oxygen, it tends to change into an Al2O3 layer at the adsorption interface when it is adsorbed by a material layer containing oxygen. In particular, the exposed surface of the capacitor dielectric layer 110 may chemically adsorb the aluminum precursor as structural atoms react with the oxygen contained in the capacitor dielectric layer 110. As a result, an Al2O3 layer 200 is selectively formed on the exposed surface of the capacitor dielectric layer 110 at an atomic layer level. If, however, the upper electrode 120 and the lower electrode 100 do not contain oxygen atoms, then the aluminum precursor that is chemically or physically adsorbed by the exposed portions of the upper and lower electrodes 120 and 100 generally does not change into a metal oxide layer. Although not shown, if the upper and/or lower electrodes 120 or 100 include a conductive metal oxide layer, such as an IrO2 layer, an Al2O3 layer may be formed on the exposed portion of the conductive metal oxide layer at an atomic layer level.
  • After selectively forming the Al2O3 layer 200 exclusively on the capacitor dielectric layer 110 at an atomic layer level by pulsing the aluminum precursor, the surface of the semiconductor substrate S is purged using inert gas. The inert gas may be argon gas, and the purging time and flow rate of the inert gas may be about 0.5-10 seconds and about 50-300 sccm, respectively. When the surface of the semiconductor substrate S is purged with inert gas, the aluminum precursor, which has been physically adsorbed by surfaces of the lower electrode 100 and the upper electrode 120 and has not reacted with the capacitor dielectric layer 110, is substantially discharged from the reaction chamber. The aluminum precursor chemically adsorbed by surfaces of the lower electrode 100 and the upper electrode 120 is generally not purged and mostly remains. In accordance with embodiments of the present invention, however, the purge time and flow rate of the inert gas may be adjusted to substantially remove the metal precursor adsorbed by the surfaces of the upper electrode 120 and the lower electrode 100.
  • The aluminum precursor pulsing operation and the inert gas purging operation constitute a single cycle of the atomic layer deposition process. The cycle may be repeated until an Al2O3 layer 200′ having a desired thickness is obtained. During succeeding cycles, an aluminum precursor reacts with oxygen atoms contained in the capacitor dielectric layer 110 through diffusion so that the Al2O3 layer 200′ is continuously formed on the capacitor dielectric layer 110 at an atomic layer level. The aluminum precursor is adsorbed by surfaces of the upper electrode 120 and the lower electrode 100, and an Al2O3 layer is generally not formed thereon.
  • An aluminum precursor usually contains hydrogen atoms. Accordingly, during a process of selectively forming an Al2O3 layer on the capacitor dielectric layer 110, in accordance with embodiments of the present invention, the dielectric characteristics of the capacitor dielectric layer 110 may be degraded. In particular, when the capacitor dielectric layer 110 is formed of a ferroelectric material such as a PZT layer or a SBT layer, the ferroelectric characteristics of the capacitor dielectric layer 110 may be degraded due to diffusion of hydrogen contained in the aluminum precursor. For example, the remnant polarization value of the capacitor dielectric layer 110 may decrease. To improve the ferroelectric characteristics of the capacitor dielectric layer 110 and to enhance the dielectric characteristic, such as the density of the Al2O3 layer, thermal treatment (illustrated by arrows) may be performed in an oxygen atmosphere after the Al2O3 layer is formed on the capacitor dielectric layer 110 to a desired thickness. In accordance with embodiments of the present invention, the thermal treatment may be performed in a rapid thermal processing apparatus or a furnace type thermal processing apparatus. When the thermal treatment is performed in a rapid thermal processing apparatus, the temperature may be about 400-600° C. and the treatment may be performed for about 10 seconds to about 10 minutes.
  • Referring to FIG. 3, in accordance with embodiments of the present invention, after the Al2O3 layer 200′ is selectively formed exclusively on the surface of the capacitor dielectric layer 110 as described above, an encapsulating layer 210 is formed on the surface of the semiconductor substrate S and the capacitor C. The encapsulating layer 210 may comprise a metal oxide and may prevent hydrogen from diffusing into the capacitor dielectric layer 110 during a subsequent InterLayer Dielectric (ILD) process, InterMetal Dielectric (IMD) process, and/or passivation process. In accordance with particular embodiments of the present invention, the encapsulating layer 210 may have a density associated therewith that is greater than the density of the layer 200′. Because the semiconductor substrate S on which the encapsulating layer 210 is formed has the capacitor C on the surface thereof, it has a generally large surface topology. Accordingly, the encapsulating layer is preferably formed using an atomic layer deposition method.
  • A single cycle for forming the encapsulating layer 210 as an Al2O3 layer may comprise the following operations: 1) pulsing aluminum source gas over the surface of the semiconductor substrate S, 2) purging with inert gas, 3) pulsing oxygen source gas, and 4) purging with inert gas. The cycle is repeated until the encapsulating layer 210 reaches a desired thickness. One of the aluminum precursors discussed above may be used as the aluminum source gas. H2O gas, O3 gas or N2O gas may be used as the oxygen source gas. Argon gas may be used as the inert gas.
  • In accordance with embodiments of the present invention, when TMA gas, H2O gas, and argon gas are used as the aluminum source gas, the oxygen source gas, and the inert gas, respectively, the pulsing time of the TMA gas may be about 0.1-2 seconds, the pulsing time of the H2O gas may be about 0.1-2 seconds, the purging time and flow rate of the argon gas may be about 1-10 seconds and about 50-300 sccm, respectively, and the temperature of the semiconductor substrate S may be about 300° C.
  • In accordance with embodiments of the present invention discussed hereinabove, an Al2O3 layer is selectively formed on a capacitor dielectric layer 110 that may reduce diffusion of impurities into the dielectric layer 110. The layer 200′ and the encapsulating layer 210 may comprise Ta, Ti, Zr, Mg, Ce, Y, Nb, Hf, Sr, or Ca. In this case, a metal precursor containing Ta, Ti, Zr, Mg, Ce, Y, Nb, Hf, Sr or Ca may be used in the aluminum precursor pulsing operation of the first embodiment.
  • With reference to FIG. 4, methods of manufacturing integrated circuit devices that include a metal oxide layer to reduce the diffusion of impurities and integrated circuit devices manufactured using same, in accordance with further embodiments of the present invention, will be described hereafter. As shown in FIG. 4, an integrated circuit devices comprises a semiconductor substrate S, a conductive region 220, which contains little or no oxygen, an interlayer insulation layer 230, which is disposed on the conductive region 220 and contains oxygen, and an opening 240, which exposes the conductive region 220. The conductive region 220 may be the upper or lower electrode of a capacitor, a gate electrode, a bit line, a word line, or the lower conductive line of a multi-layered interconnection layer. The interlayer insulation layer 230 may be a silicon oxide layer or a silicon oxynitride layer.
  • Subsequently, a metal oxide layer 250 (e.g., an Al2O3 layer) is selectively formed on the exposed surface of the interlayer insulation layer 230 using atomic layer deposition as discussed hereinabove with respect to FIGS. 1-3. In accordance with embodiments of the present invention, the oxide layer may comprise alternative metals, such as Ta, Ti, Zr, Mg, Ce, Y, Nb, Hf, Sr, or Ca. A thermal treatment may be performed in an oxygen atmosphere after the metal oxide layer 250 is selectively formed to enhance the dielectric characteristic of the metal oxide layer 250.
  • When the metal oxide layer 250 is selectively formed exclusively on the exposed surface of the interlayer insulation layer 230, the metal oxide layer 250 can inhibit substances that can degrade a semiconductor device by diffusing to structures below the metal oxide layer 250 during subsequent processes of forming material layer(s) on the interlayer insulation layer 230. Examples of integrated circuit devices formed in accordance with embodiments of the present invention are described hereafter.
  • EXAMPLE 1
  • A capacitor, in which a Pt layer (a lower electrode), a PZT layer (a capacitor dielectric layer), and an Ir/IrO2 layer (an upper electrode) were sequentially stacked, was formed on a semiconductor substrate. Thereafter, the semiconductor substrate was loaded in an atomic layer deposition apparatus, and a stabilizing step was performed such that the pressure of a chamber was maintained at about 0.1-1 torr, and the temperature of the semiconductor substrate was maintained at about 300° C. Next, an atomic layer deposition process cycle, as discussed above with respect to FIG. 2, was repeated 100 times and a test sample was obtained. TMA gas was used as an aluminum precursor and the pulsing time in each cycle was about 0.1 second. Argon gas was used as a purge gas, and the purging time in each cycle was about 1 second. After obtaining the sample through the above series of steps, an X-ray photoelectron spectroscopy analysis was performed on the integrated circuit device to check whether an Al2O3 layer was formed on the capacitor dielectric layer. The result of the analysis is shown in FIG. 5. In FIG. 5, the horizontal axis denotes binding energy and the vertical axis denotes arbitrary intensity. Referring to FIG. 5, an aluminum 2p peak (see III) indicating binding energy between aluminum and oxygen may be observed. Accordingly, these results indicate that an Al2O3 layer was selectively formed on the capacitor dielectric layer of the sample. In particular, because oxygen source gas was not pulsed, it can be inferred that the oxygen contained in the Al2O3 layer was supplied by the capacitor dielectric layer.
  • EXAMPLE 2
  • A capacitor pattern was formed on a semiconductor substrate as discussed hereinabove with respect to FIGS. 1-3 and a Sample 1 and a Sample 2 were separately manufactured. Thereafter, the following operations were sequentially performed on the Samples 1 and 2, and the remnant polarization values of their capacitor dielectric layers were measured after completion of each operation. The results of the measurements are shown in FIG. 6. In FIG. 6, the horizontal axis denotes the operations performed on the Samples 1 and 2, and the vertical axis denotes the remnant polarization values.
  • Sample 1
  • In step A1, an Al2O3 layer was selectively formed on a capacitor dielectric layer as discussed hereinabove with respect to FIGS. 1-3. The process conditions of step A1 were approximately the same as those used in Example 1. Thereafter, in step A2, the semiconductor substrate was loaded in a rapid thermal processing apparatus and thermally treated for about 10 seconds at a temperature of about 700° C. in an oxygen atmosphere. Next, in step A3, an Al2O3 layer that encapsulates the capacitor pattern was formed as discussed hereinabove with respect to FIGS. 1-3. TMA gas, H2O gas, and argon gas were used as the aluminum source gas, the oxygen source gas, and the purge gas, respectively. The pulsing time of the TMA gas was about 0.5 seconds. The pulsing time of the H2O gas was about 0.3 seconds. The purging time and purging flow rate of the argon gas were about 6 seconds and about 150 sccm, respectively. The temperature of the wafer was about 300° C.
  • Sample 2
  • In step B1, a semiconductor substrate including a capacitor disposed thereon was loaded in a rapid thermal processing apparatus and thermally treated. The process conditions of step B1 were the same as those of step A2. Thereafter, in step B2, an Al2O3 layer was formed that encapsulates the capacitor. The process conditions of step B2 were the same as those of step A3.
  • Referring now to FIG. 6, the remnant polarization value of the capacitor dielectric layer in Sample 1 decreases a little after step A1 due to the influence of the TMA gas and the H2O gas, which contain hydrogen. The remnant polarization value, however, increases over the initial value after performing the rapid thermal process in an oxygen atmosphere in step A2. Although the remnant polarization value decreases a little after encapsulating the capacitor in step A3, the decreased remnant polarization value is almost the same as the initial value. The remnant polarization value of the capacitor dielectric layer in Sample 1 rarely decreased even though TMA gas and H2O gas, which contain hydrogen, were used in step A3.
  • The remnant polarization value of the capacitor dielectric layer in Sample 2 increases over the initial value after performing a rapid thermal process in an oxygen atmosphere in step B1. The remnant polarization value greatly decreases with respect to Sample 1, however, after encapsulating the capacitor in step B2.
  • Sample 1 is different from Sample 2 in that it has a selectively formed metal oxide layer that has been thermal-treated in an oxygen atmosphere. In contrast with Sample 2, the remnant polarization value in Sample 1 did not decrease even though Sample 1 had undergone Step A3 in which hydrogen-base gas was supplied. This suggests that the thermal-treated metal oxide layer effectively reduced the diffusion of hydrogen into the capacitor dielectric layer. Accordingly, the thermal-treated metal oxide layer may reduce diffusion of hydrogen into the capacitor dielectric layer in subsequent ILD, IMD, and passivation processes.
  • Although the invention has been described with reference to exemplary embodiments, it will be apparent to one of ordinary skill in the art that modifications of the described embodiments may be made without departing from the spirit and scope of the invention. For example, principles of the present invention may be applied when selectively forming a metal oxide layer exclusively on the exposed surface of a gate oxide layer in a gate electrode pattern.
  • According to embodiments of the present invention, a metal oxide layer may be selectively formed exclusively on an insulation layer containing oxygen. In particular, by encapsulating a capacitor of a semiconductor memory device using an atomic layer deposition method, in accordance with embodiments of the present invention, the degradation of a capacitor dielectric layer may be reduced, even if a source gas containing hydrogen is used. In addition, degradation of a capacitor dielectric layer due to diffusion of hydrogen during an ILD process, an IMD process, or a passivation process, which are performed after encapsulating the capacitor, may be effectively reduced.
  • In concluding the detailed description, it should be noted that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of the present invention. All such variations and modifications are intended to be included herein within the scope of the present invention, as set forth in the following claims.

Claims (12)

1-13. (Canceled)
14. An integrated circuit device, comprising:
a capacitor that comprises a lower electrode layer, a dielectric layer on the lower electrode layer, and an upper electrode layer on the dielectric layer;
a first metal oxide layer that is disposed on an exposed portion of the dielectric layer and has a first density associated therewith; and
a second metal oxide layer that encapsulates the capacitor and the first metal oxide layer and has a second density associated therewith that is greater than the first density.
15. The integrated circuit device of claim 14, wherein the first and second metal oxide layers each comprise an element selected from the group of elements consisting of: Al, Ta, Ti, Zr, Mg, Ce, Y, Nb, Hf, Sr, and Ca.
16. The integrated circuit device of claim 14, wherein the dielectric layer comprises a material selected from the group of materials consisting of: TiO2, SiO2, Ta2O5, Al2O3, BaTiO3, SrTiO3, (Ba, Sr)TiO3, Bi4Ti3O12, PbTiO3, PZT((Pb, La)(Zr, Ti)O3), and (SrBi2Ta2O9)(SBT).
17. The integrated circuit device of claim 14, wherein the first metal oxide layer is disposed on a sidewall of the dielectric layer and a portion of a surface of the dielectric layer that is adjacent to the upper electrode.
18. A method of manufacturing an integrated circuit device, comprising:
forming an insulation layer that comprises oxygen on a substrate; and
forming a first metal oxide layer on at least a portion of the insulation layer by exposing the at least a portion of the insulation layer to a first metal precursor that is reactive with the oxygen in the insulation layer.
19. The method of claim 18, further comprising:
forming a lower electrode on the substrate; and
forming an upper electrode on the insulation layer;
wherein forming the insulation layer that comprises oxygen on the substrate comprises:
forming the insulation layer that comprises oxygen on the lower electrode.
20. The method of claim 19, further comprising:
forming a second metal oxide layer on the substrate that encapsulates the lower electrode, the insulation layer, the first metal oxide layer, and the upper electrode.
21. The method of claim 20, wherein forming the first metal oxide layer comprises:
pulsing the first metal precursor over the integrated circuit device; and
exposing the integrated circuit device to an inert gas.
22. The method of claim 21, wherein forming the second metal oxide layer comprises:
pulsing a second metal precursor over the integrated circuit device;
exposing the integrated circuit device to an inert gas; then
pulsing oxygen gas over the integrated circuit device; then
exposing the integrated circuit device to an inert gas.
23. The method of claim 18, further comprising:
thermally treating the integrated circuit device in an oxygen atmosphere using one of a rapid thermal processing apparatus and a furnace type thermal processing apparatus.
24. The method of claim 18, further comprising:
forming a conductive region on the substrate, the insulation layer being disposed on the conductive region and the substrate;
forming an opening in the insulation layer so as to expose at least a portion of the conductive region; and
forming the first metal oxide layer on the at least a portion of the insulation layer while maintaining the exposed portion of the conductive region substantially devoid of the first metal oxide layer by exposing the at least a portion of the insulation layer and the exposed portion of the conductive region to the first metal precursor that is reactive with the oxygen in the insulation layer.
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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060274477A1 (en) * 2003-05-20 2006-12-07 Cem Basceri DRAM cells and electronic systems
US20090109598A1 (en) * 2007-10-30 2009-04-30 Spansion Llc Metal-insulator-metal (MIM) device and method of formation thereof
US20090200533A1 (en) * 2008-02-08 2009-08-13 Klaus-Dieter Ufert Resistive Memory Element and Method of Fabrication
US20090297696A1 (en) * 2008-05-29 2009-12-03 Viljami Pore Methods for forming conductive titanium oxide thin films
US20110193194A1 (en) * 2008-10-28 2011-08-11 Taiyo Yuden Co., Ltd. Thin film mim capacitors and manufacturing method therefor
US20150264815A1 (en) * 2014-03-11 2015-09-17 Ibiden Co., Ltd. Substrate with built-in capacitor and method for manufacturing substrate with built-in capacitor
US9523148B1 (en) 2015-08-25 2016-12-20 Asm Ip Holdings B.V. Process for deposition of titanium oxynitride for use in integrated circuit fabrication
US9540729B1 (en) 2015-08-25 2017-01-10 Asm Ip Holding B.V. Deposition of titanium nanolaminates for use in integrated circuit fabrication

Families Citing this family (257)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7554829B2 (en) 1999-07-30 2009-06-30 Micron Technology, Inc. Transmission lines for CMOS integrated circuits
US6852167B2 (en) * 2001-03-01 2005-02-08 Micron Technology, Inc. Methods, systems, and apparatus for uniform chemical-vapor depositions
US6844203B2 (en) * 2001-08-30 2005-01-18 Micron Technology, Inc. Gate oxides, and methods of forming
US7068544B2 (en) * 2001-08-30 2006-06-27 Micron Technology, Inc. Flash memory with low tunnel barrier interpoly insulators
US8026161B2 (en) * 2001-08-30 2011-09-27 Micron Technology, Inc. Highly reliable amorphous high-K gate oxide ZrO2
KR100424710B1 (en) * 2001-11-21 2004-03-27 주식회사 하이닉스반도체 Fabricating method of semiconductor device
US6900122B2 (en) * 2001-12-20 2005-05-31 Micron Technology, Inc. Low-temperature grown high-quality ultra-thin praseodymium gate dielectrics
US6953730B2 (en) * 2001-12-20 2005-10-11 Micron Technology, Inc. Low-temperature grown high quality ultra-thin CoTiO3 gate dielectrics
US6767795B2 (en) * 2002-01-17 2004-07-27 Micron Technology, Inc. Highly reliable amorphous high-k gate dielectric ZrOXNY
US7589029B2 (en) * 2002-05-02 2009-09-15 Micron Technology, Inc. Atomic layer deposition and conversion
US7045430B2 (en) 2002-05-02 2006-05-16 Micron Technology Inc. Atomic layer-deposited LaAlO3 films for gate dielectrics
US7160577B2 (en) * 2002-05-02 2007-01-09 Micron Technology, Inc. Methods for atomic-layer deposition of aluminum oxides in integrated circuits
US7135421B2 (en) * 2002-06-05 2006-11-14 Micron Technology, Inc. Atomic layer-deposited hafnium aluminum oxide
US7205218B2 (en) 2002-06-05 2007-04-17 Micron Technology, Inc. Method including forming gate dielectrics having multiple lanthanide oxide layers
US7221586B2 (en) * 2002-07-08 2007-05-22 Micron Technology, Inc. Memory utilizing oxide nanolaminates
KR100464855B1 (en) * 2002-07-26 2005-01-06 삼성전자주식회사 method for forming a thin film, and method for forming a capacitor and a transistor of a semiconductor device using the same
US6921702B2 (en) * 2002-07-30 2005-07-26 Micron Technology Inc. Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics
US6884739B2 (en) 2002-08-15 2005-04-26 Micron Technology Inc. Lanthanide doped TiOx dielectric films by plasma oxidation
US6790791B2 (en) * 2002-08-15 2004-09-14 Micron Technology, Inc. Lanthanide doped TiOx dielectric films
US7199023B2 (en) * 2002-08-28 2007-04-03 Micron Technology, Inc. Atomic layer deposited HfSiON dielectric films wherein each precursor is independendently pulsed
US7084078B2 (en) * 2002-08-29 2006-08-01 Micron Technology, Inc. Atomic layer deposited lanthanide doped TiOx dielectric films
US6958302B2 (en) * 2002-12-04 2005-10-25 Micron Technology, Inc. Atomic layer deposited Zr-Sn-Ti-O films using TiI4
US7101813B2 (en) * 2002-12-04 2006-09-05 Micron Technology Inc. Atomic layer deposited Zr-Sn-Ti-O films
US7192892B2 (en) * 2003-03-04 2007-03-20 Micron Technology, Inc. Atomic layer deposited dielectric layers
US7135369B2 (en) * 2003-03-31 2006-11-14 Micron Technology, Inc. Atomic layer deposited ZrAlxOy dielectric layers including Zr4AlO9
US20040206993A1 (en) * 2003-04-17 2004-10-21 Infineon Technologies Ag Process for fabrication of ferroelectric devices with reduced hydrogen ion damage
US7183186B2 (en) * 2003-04-22 2007-02-27 Micro Technology, Inc. Atomic layer deposited ZrTiO4 films
US7049192B2 (en) * 2003-06-24 2006-05-23 Micron Technology, Inc. Lanthanide oxide / hafnium oxide dielectrics
US7192824B2 (en) * 2003-06-24 2007-03-20 Micron Technology, Inc. Lanthanide oxide / hafnium oxide dielectric layers
JP2005217044A (en) * 2004-01-28 2005-08-11 Fujitsu Ltd Semiconductor device and method for manufacturing the same
JP2006005234A (en) * 2004-06-18 2006-01-05 Seiko Epson Corp Semiconductor device and method of manufacturing the same
US7601649B2 (en) 2004-08-02 2009-10-13 Micron Technology, Inc. Zirconium-doped tantalum oxide films
US7081421B2 (en) 2004-08-26 2006-07-25 Micron Technology, Inc. Lanthanide oxide dielectric layer
US7588988B2 (en) * 2004-08-31 2009-09-15 Micron Technology, Inc. Method of forming apparatus having oxide films formed using atomic layer deposition
US7494939B2 (en) * 2004-08-31 2009-02-24 Micron Technology, Inc. Methods for forming a lanthanum-metal oxide dielectric layer
US20060125030A1 (en) * 2004-12-13 2006-06-15 Micron Technology, Inc. Hybrid ALD-CVD of PrxOy/ZrO2 films as gate dielectrics
US7235501B2 (en) * 2004-12-13 2007-06-26 Micron Technology, Inc. Lanthanum hafnium oxide dielectrics
US7560395B2 (en) * 2005-01-05 2009-07-14 Micron Technology, Inc. Atomic layer deposited hafnium tantalum oxide dielectrics
US7508648B2 (en) * 2005-02-08 2009-03-24 Micron Technology, Inc. Atomic layer deposition of Dy doped HfO2 films as gate dielectrics
US7374964B2 (en) 2005-02-10 2008-05-20 Micron Technology, Inc. Atomic layer deposition of CeO2/Al2O3 films as gate dielectrics
US7399666B2 (en) * 2005-02-15 2008-07-15 Micron Technology, Inc. Atomic layer deposition of Zr3N4/ZrO2 films as gate dielectrics
US7498247B2 (en) 2005-02-23 2009-03-03 Micron Technology, Inc. Atomic layer deposition of Hf3N4/HfO2 films as gate dielectrics
US7687409B2 (en) 2005-03-29 2010-03-30 Micron Technology, Inc. Atomic layer deposited titanium silicon oxide films
US7365027B2 (en) * 2005-03-29 2008-04-29 Micron Technology, Inc. ALD of amorphous lanthanide doped TiOx films
US7390756B2 (en) 2005-04-28 2008-06-24 Micron Technology, Inc. Atomic layer deposited zirconium silicon oxide films
US7662729B2 (en) * 2005-04-28 2010-02-16 Micron Technology, Inc. Atomic layer deposition of a ruthenium layer to a lanthanide oxide dielectric layer
US7572695B2 (en) * 2005-05-27 2009-08-11 Micron Technology, Inc. Hafnium titanium oxide films
WO2006129366A1 (en) * 2005-06-02 2006-12-07 Fujitsu Limited Semiconductor device and method for manufacturing same
US7927948B2 (en) 2005-07-20 2011-04-19 Micron Technology, Inc. Devices with nanocrystals and methods of formation
JP4445446B2 (en) * 2005-09-13 2010-04-07 株式会社東芝 Manufacturing method of semiconductor device
US7972974B2 (en) 2006-01-10 2011-07-05 Micron Technology, Inc. Gallium lanthanide oxide films
US7709402B2 (en) * 2006-02-16 2010-05-04 Micron Technology, Inc. Conductive layers for hafnium silicon oxynitride films
US7563730B2 (en) 2006-08-31 2009-07-21 Micron Technology, Inc. Hafnium lanthanide oxynitride films
US7605030B2 (en) 2006-08-31 2009-10-20 Micron Technology, Inc. Hafnium tantalum oxynitride high-k dielectric and metal gates
JP2012124322A (en) * 2010-12-08 2012-06-28 Elpida Memory Inc Method of manufacturing semiconductor storage
US20130023129A1 (en) 2011-07-20 2013-01-24 Asm America, Inc. Pressure transmitter for a semiconductor processing environment
US10714315B2 (en) 2012-10-12 2020-07-14 Asm Ip Holdings B.V. Semiconductor reaction chamber showerhead
US11015245B2 (en) 2014-03-19 2021-05-25 Asm Ip Holding B.V. Gas-phase reactor and system having exhaust plenum and components thereof
US10941490B2 (en) 2014-10-07 2021-03-09 Asm Ip Holding B.V. Multiple temperature range susceptor, assembly, reactor and system including the susceptor, and methods of using the same
US10276355B2 (en) 2015-03-12 2019-04-30 Asm Ip Holding B.V. Multi-zone reactor, system including the reactor, and method of using the same
US10458018B2 (en) 2015-06-26 2019-10-29 Asm Ip Holding B.V. Structures including metal carbide material, devices including the structures, and methods of forming same
US10211308B2 (en) 2015-10-21 2019-02-19 Asm Ip Holding B.V. NbMC layers
US11139308B2 (en) 2015-12-29 2021-10-05 Asm Ip Holding B.V. Atomic layer deposition of III-V compounds to form V-NAND devices
US10529554B2 (en) 2016-02-19 2020-01-07 Asm Ip Holding B.V. Method for forming silicon nitride film selectively on sidewalls or flat surfaces of trenches
US10367080B2 (en) 2016-05-02 2019-07-30 Asm Ip Holding B.V. Method of forming a germanium oxynitride film
US11453943B2 (en) 2016-05-25 2022-09-27 Asm Ip Holding B.V. Method for forming carbon-containing silicon/metal oxide or nitride film by ALD using silicon precursor and hydrocarbon precursor
US9859151B1 (en) 2016-07-08 2018-01-02 Asm Ip Holding B.V. Selective film deposition method to form air gaps
US10612137B2 (en) 2016-07-08 2020-04-07 Asm Ip Holdings B.V. Organic reactants for atomic layer deposition
US9887082B1 (en) 2016-07-28 2018-02-06 Asm Ip Holding B.V. Method and apparatus for filling a gap
US9812320B1 (en) 2016-07-28 2017-11-07 Asm Ip Holding B.V. Method and apparatus for filling a gap
KR102532607B1 (en) 2016-07-28 2023-05-15 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus and method of operating the same
US11532757B2 (en) 2016-10-27 2022-12-20 Asm Ip Holding B.V. Deposition of charge trapping layers
US10714350B2 (en) 2016-11-01 2020-07-14 ASM IP Holdings, B.V. Methods for forming a transition metal niobium nitride film on a substrate by atomic layer deposition and related semiconductor device structures
KR102546317B1 (en) 2016-11-15 2023-06-21 에이에스엠 아이피 홀딩 비.브이. Gas supply unit and substrate processing apparatus including the same
KR20180068582A (en) 2016-12-14 2018-06-22 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus
US11581186B2 (en) 2016-12-15 2023-02-14 Asm Ip Holding B.V. Sequential infiltration synthesis apparatus
US11447861B2 (en) 2016-12-15 2022-09-20 Asm Ip Holding B.V. Sequential infiltration synthesis apparatus and a method of forming a patterned structure
KR20180070971A (en) 2016-12-19 2018-06-27 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus
US10269558B2 (en) 2016-12-22 2019-04-23 Asm Ip Holding B.V. Method of forming a structure on a substrate
US11390950B2 (en) 2017-01-10 2022-07-19 Asm Ip Holding B.V. Reactor system and method to reduce residue buildup during a film deposition process
US10468261B2 (en) 2017-02-15 2019-11-05 Asm Ip Holding B.V. Methods for forming a metallic film on a substrate by cyclical deposition and related semiconductor device structures
US10529563B2 (en) 2017-03-29 2020-01-07 Asm Ip Holdings B.V. Method for forming doped metal oxide films on a substrate by cyclical deposition and related semiconductor device structures
US10770286B2 (en) 2017-05-08 2020-09-08 Asm Ip Holdings B.V. Methods for selectively forming a silicon nitride film on a substrate and related semiconductor device structures
US11306395B2 (en) 2017-06-28 2022-04-19 Asm Ip Holding B.V. Methods for depositing a transition metal nitride film on a substrate by atomic layer deposition and related deposition apparatus
KR20190009245A (en) 2017-07-18 2019-01-28 에이에스엠 아이피 홀딩 비.브이. Methods for forming a semiconductor device structure and related semiconductor device structures
US11374112B2 (en) 2017-07-19 2022-06-28 Asm Ip Holding B.V. Method for depositing a group IV semiconductor and related semiconductor device structures
US10541333B2 (en) 2017-07-19 2020-01-21 Asm Ip Holding B.V. Method for depositing a group IV semiconductor and related semiconductor device structures
US11018002B2 (en) 2017-07-19 2021-05-25 Asm Ip Holding B.V. Method for selectively depositing a Group IV semiconductor and related semiconductor device structures
US10590535B2 (en) 2017-07-26 2020-03-17 Asm Ip Holdings B.V. Chemical treatment, deposition and/or infiltration apparatus and method for using the same
US10770336B2 (en) 2017-08-08 2020-09-08 Asm Ip Holding B.V. Substrate lift mechanism and reactor including same
US10692741B2 (en) 2017-08-08 2020-06-23 Asm Ip Holdings B.V. Radiation shield
US11769682B2 (en) 2017-08-09 2023-09-26 Asm Ip Holding B.V. Storage apparatus for storing cassettes for substrates and processing apparatus equipped therewith
US11139191B2 (en) 2017-08-09 2021-10-05 Asm Ip Holding B.V. Storage apparatus for storing cassettes for substrates and processing apparatus equipped therewith
US11830730B2 (en) 2017-08-29 2023-11-28 Asm Ip Holding B.V. Layer forming method and apparatus
KR102491945B1 (en) 2017-08-30 2023-01-26 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus
US11295980B2 (en) 2017-08-30 2022-04-05 Asm Ip Holding B.V. Methods for depositing a molybdenum metal film over a dielectric surface of a substrate by a cyclical deposition process and related semiconductor device structures
US11056344B2 (en) 2017-08-30 2021-07-06 Asm Ip Holding B.V. Layer forming method
US10658205B2 (en) 2017-09-28 2020-05-19 Asm Ip Holdings B.V. Chemical dispensing apparatus and methods for dispensing a chemical to a reaction chamber
US10403504B2 (en) 2017-10-05 2019-09-03 Asm Ip Holding B.V. Method for selectively depositing a metallic film on a substrate
US10927459B2 (en) 2017-10-16 2021-02-23 Asm Ip Holding B.V. Systems and methods for atomic layer deposition
US11022879B2 (en) 2017-11-24 2021-06-01 Asm Ip Holding B.V. Method of forming an enhanced unexposed photoresist layer
CN111344522B (en) 2017-11-27 2022-04-12 阿斯莫Ip控股公司 Including clean mini-environment device
CN111316417B (en) 2017-11-27 2023-12-22 阿斯莫Ip控股公司 Storage device for storing wafer cassettes for use with batch ovens
US10872771B2 (en) 2018-01-16 2020-12-22 Asm Ip Holding B. V. Method for depositing a material film on a substrate within a reaction chamber by a cyclical deposition process and related device structures
WO2019142055A2 (en) 2018-01-19 2019-07-25 Asm Ip Holding B.V. Method for depositing a gap-fill layer by plasma-assisted deposition
TWI799494B (en) 2018-01-19 2023-04-21 荷蘭商Asm 智慧財產控股公司 Deposition method
US11081345B2 (en) 2018-02-06 2021-08-03 Asm Ip Holding B.V. Method of post-deposition treatment for silicon oxide film
US10896820B2 (en) 2018-02-14 2021-01-19 Asm Ip Holding B.V. Method for depositing a ruthenium-containing film on a substrate by a cyclical deposition process
EP3737779A1 (en) 2018-02-14 2020-11-18 ASM IP Holding B.V. A method for depositing a ruthenium-containing film on a substrate by a cyclical deposition process
KR102636427B1 (en) 2018-02-20 2024-02-13 에이에스엠 아이피 홀딩 비.브이. Substrate processing method and apparatus
US11473195B2 (en) 2018-03-01 2022-10-18 Asm Ip Holding B.V. Semiconductor processing apparatus and a method for processing a substrate
US11629406B2 (en) 2018-03-09 2023-04-18 Asm Ip Holding B.V. Semiconductor processing apparatus comprising one or more pyrometers for measuring a temperature of a substrate during transfer of the substrate
US11114283B2 (en) 2018-03-16 2021-09-07 Asm Ip Holding B.V. Reactor, system including the reactor, and methods of manufacturing and using same
US10847371B2 (en) 2018-03-27 2020-11-24 Asm Ip Holding B.V. Method of forming an electrode on a substrate and a semiconductor device structure including an electrode
US11088002B2 (en) 2018-03-29 2021-08-10 Asm Ip Holding B.V. Substrate rack and a substrate processing system and method
US11230766B2 (en) 2018-03-29 2022-01-25 Asm Ip Holding B.V. Substrate processing apparatus and method
TWI811348B (en) 2018-05-08 2023-08-11 荷蘭商Asm 智慧財產控股公司 Methods for depositing an oxide film on a substrate by a cyclical deposition process and related device structures
KR102596988B1 (en) 2018-05-28 2023-10-31 에이에스엠 아이피 홀딩 비.브이. Method of processing a substrate and a device manufactured by the same
US11718913B2 (en) 2018-06-04 2023-08-08 Asm Ip Holding B.V. Gas distribution system and reactor system including same
TW202013553A (en) 2018-06-04 2020-04-01 荷蘭商Asm 智慧財產控股公司 Wafer handling chamber with moisture reduction
US11286562B2 (en) 2018-06-08 2022-03-29 Asm Ip Holding B.V. Gas-phase chemical reactor and method of using same
KR102568797B1 (en) 2018-06-21 2023-08-21 에이에스엠 아이피 홀딩 비.브이. Substrate processing system
US10797133B2 (en) 2018-06-21 2020-10-06 Asm Ip Holding B.V. Method for depositing a phosphorus doped silicon arsenide film and related semiconductor device structures
CN112292477A (en) 2018-06-27 2021-01-29 Asm Ip私人控股有限公司 Cyclic deposition methods for forming metal-containing materials and films and structures containing metal-containing materials
JP2021529254A (en) 2018-06-27 2021-10-28 エーエスエム・アイピー・ホールディング・ベー・フェー Periodic deposition methods for forming metal-containing materials and films and structures containing metal-containing materials
US10612136B2 (en) 2018-06-29 2020-04-07 ASM IP Holding, B.V. Temperature-controlled flange and reactor system including same
US10755922B2 (en) 2018-07-03 2020-08-25 Asm Ip Holding B.V. Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition
US10388513B1 (en) 2018-07-03 2019-08-20 Asm Ip Holding B.V. Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition
US11053591B2 (en) 2018-08-06 2021-07-06 Asm Ip Holding B.V. Multi-port gas injection system and reactor system including same
US11430674B2 (en) 2018-08-22 2022-08-30 Asm Ip Holding B.V. Sensor array, apparatus for dispensing a vapor phase reactant to a reaction chamber and related methods
US11024523B2 (en) 2018-09-11 2021-06-01 Asm Ip Holding B.V. Substrate processing apparatus and method
KR20200030162A (en) 2018-09-11 2020-03-20 에이에스엠 아이피 홀딩 비.브이. Method for deposition of a thin film
US11049751B2 (en) 2018-09-14 2021-06-29 Asm Ip Holding B.V. Cassette supply system to store and handle cassettes and processing apparatus equipped therewith
CN110970344A (en) 2018-10-01 2020-04-07 Asm Ip控股有限公司 Substrate holding apparatus, system including the same, and method of using the same
US11232963B2 (en) 2018-10-03 2022-01-25 Asm Ip Holding B.V. Substrate processing apparatus and method
KR102592699B1 (en) 2018-10-08 2023-10-23 에이에스엠 아이피 홀딩 비.브이. Substrate support unit and apparatuses for depositing thin film and processing the substrate including the same
KR102546322B1 (en) 2018-10-19 2023-06-21 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus and substrate processing method
KR102605121B1 (en) 2018-10-19 2023-11-23 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus and substrate processing method
USD948463S1 (en) 2018-10-24 2022-04-12 Asm Ip Holding B.V. Susceptor for semiconductor substrate supporting apparatus
US11087997B2 (en) 2018-10-31 2021-08-10 Asm Ip Holding B.V. Substrate processing apparatus for processing substrates
KR20200051105A (en) 2018-11-02 2020-05-13 에이에스엠 아이피 홀딩 비.브이. Substrate support unit and substrate processing apparatus including the same
US11572620B2 (en) 2018-11-06 2023-02-07 Asm Ip Holding B.V. Methods for selectively depositing an amorphous silicon film on a substrate
US11031242B2 (en) 2018-11-07 2021-06-08 Asm Ip Holding B.V. Methods for depositing a boron doped silicon germanium film
US10818758B2 (en) 2018-11-16 2020-10-27 Asm Ip Holding B.V. Methods for forming a metal silicate film on a substrate in a reaction chamber and related semiconductor device structures
US10847366B2 (en) 2018-11-16 2020-11-24 Asm Ip Holding B.V. Methods for depositing a transition metal chalcogenide film on a substrate by a cyclical deposition process
US11217444B2 (en) 2018-11-30 2022-01-04 Asm Ip Holding B.V. Method for forming an ultraviolet radiation responsive metal oxide-containing film
KR102636428B1 (en) 2018-12-04 2024-02-13 에이에스엠 아이피 홀딩 비.브이. A method for cleaning a substrate processing apparatus
US11158513B2 (en) 2018-12-13 2021-10-26 Asm Ip Holding B.V. Methods for forming a rhenium-containing film on a substrate by a cyclical deposition process and related semiconductor device structures
TW202037745A (en) 2018-12-14 2020-10-16 荷蘭商Asm Ip私人控股有限公司 Method of forming device structure, structure formed by the method and system for performing the method
TWI819180B (en) 2019-01-17 2023-10-21 荷蘭商Asm 智慧財產控股公司 Methods of forming a transition metal containing film on a substrate by a cyclical deposition process
KR20200091543A (en) 2019-01-22 2020-07-31 에이에스엠 아이피 홀딩 비.브이. Semiconductor processing device
CN111524788B (en) 2019-02-01 2023-11-24 Asm Ip私人控股有限公司 Method for topologically selective film formation of silicon oxide
US11482533B2 (en) 2019-02-20 2022-10-25 Asm Ip Holding B.V. Apparatus and methods for plug fill deposition in 3-D NAND applications
KR102626263B1 (en) 2019-02-20 2024-01-16 에이에스엠 아이피 홀딩 비.브이. Cyclical deposition method including treatment step and apparatus for same
TW202044325A (en) 2019-02-20 2020-12-01 荷蘭商Asm Ip私人控股有限公司 Method of filling a recess formed within a surface of a substrate, semiconductor structure formed according to the method, and semiconductor processing apparatus
TW202104632A (en) 2019-02-20 2021-02-01 荷蘭商Asm Ip私人控股有限公司 Cyclical deposition method and apparatus for filling a recess formed within a substrate surface
TW202100794A (en) 2019-02-22 2021-01-01 荷蘭商Asm Ip私人控股有限公司 Substrate processing apparatus and method for processing substrate
KR20200108248A (en) 2019-03-08 2020-09-17 에이에스엠 아이피 홀딩 비.브이. STRUCTURE INCLUDING SiOCN LAYER AND METHOD OF FORMING SAME
KR20200108243A (en) 2019-03-08 2020-09-17 에이에스엠 아이피 홀딩 비.브이. Structure Including SiOC Layer and Method of Forming Same
KR20200108242A (en) 2019-03-08 2020-09-17 에이에스엠 아이피 홀딩 비.브이. Method for Selective Deposition of Silicon Nitride Layer and Structure Including Selectively-Deposited Silicon Nitride Layer
KR20200116033A (en) 2019-03-28 2020-10-08 에이에스엠 아이피 홀딩 비.브이. Door opener and substrate processing apparatus provided therewith
KR20200116855A (en) 2019-04-01 2020-10-13 에이에스엠 아이피 홀딩 비.브이. Method of manufacturing semiconductor device
KR20200123380A (en) 2019-04-19 2020-10-29 에이에스엠 아이피 홀딩 비.브이. Layer forming method and apparatus
KR20200125453A (en) 2019-04-24 2020-11-04 에이에스엠 아이피 홀딩 비.브이. Gas-phase reactor system and method of using same
KR20200130121A (en) 2019-05-07 2020-11-18 에이에스엠 아이피 홀딩 비.브이. Chemical source vessel with dip tube
KR20200130118A (en) 2019-05-07 2020-11-18 에이에스엠 아이피 홀딩 비.브이. Method for Reforming Amorphous Carbon Polymer Film
KR20200130652A (en) 2019-05-10 2020-11-19 에이에스엠 아이피 홀딩 비.브이. Method of depositing material onto a surface and structure formed according to the method
JP2020188255A (en) 2019-05-16 2020-11-19 エーエスエム アイピー ホールディング ビー.ブイ. Wafer boat handling device, vertical batch furnace, and method
USD947913S1 (en) 2019-05-17 2022-04-05 Asm Ip Holding B.V. Susceptor shaft
USD975665S1 (en) 2019-05-17 2023-01-17 Asm Ip Holding B.V. Susceptor shaft
USD935572S1 (en) 2019-05-24 2021-11-09 Asm Ip Holding B.V. Gas channel plate
USD922229S1 (en) 2019-06-05 2021-06-15 Asm Ip Holding B.V. Device for controlling a temperature of a gas supply unit
KR20200141002A (en) 2019-06-06 2020-12-17 에이에스엠 아이피 홀딩 비.브이. Method of using a gas-phase reactor system including analyzing exhausted gas
KR20200143254A (en) 2019-06-11 2020-12-23 에이에스엠 아이피 홀딩 비.브이. Method of forming an electronic structure using an reforming gas, system for performing the method, and structure formed using the method
USD944946S1 (en) 2019-06-14 2022-03-01 Asm Ip Holding B.V. Shower plate
USD931978S1 (en) 2019-06-27 2021-09-28 Asm Ip Holding B.V. Showerhead vacuum transport
KR20210005515A (en) 2019-07-03 2021-01-14 에이에스엠 아이피 홀딩 비.브이. Temperature control assembly for substrate processing apparatus and method of using same
JP2021015791A (en) 2019-07-09 2021-02-12 エーエスエム アイピー ホールディング ビー.ブイ. Plasma device and substrate processing method using coaxial waveguide
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US11562901B2 (en) 2019-09-25 2023-01-24 Asm Ip Holding B.V. Substrate processing method
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US11501968B2 (en) 2019-11-15 2022-11-15 Asm Ip Holding B.V. Method for providing a semiconductor device with silicon filled gaps
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US11450529B2 (en) 2019-11-26 2022-09-20 Asm Ip Holding B.V. Methods for selectively forming a target film on a substrate comprising a first dielectric surface and a second metallic surface
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CN112885693A (en) 2019-11-29 2021-06-01 Asm Ip私人控股有限公司 Substrate processing apparatus
JP2021090042A (en) 2019-12-02 2021-06-10 エーエスエム アイピー ホールディング ビー.ブイ. Substrate processing apparatus and substrate processing method
KR20210070898A (en) 2019-12-04 2021-06-15 에이에스엠 아이피 홀딩 비.브이. Substrate processing apparatus
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Citations (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5374578A (en) * 1992-02-25 1994-12-20 Ramtron International Corporation Ozone gas processing for ferroelectric memory circuits
US5933727A (en) * 1994-03-11 1999-08-03 Micron Technology, Inc. Method for increasing capacitance of an HSG rugged capacitor using a phosphine rich oxidation and subsequent wet etch
US6020243A (en) * 1997-07-24 2000-02-01 Texas Instruments Incorporated Zirconium and/or hafnium silicon-oxynitride gate dielectric
US6077774A (en) * 1996-03-29 2000-06-20 Texas Instruments Incorporated Method of forming ultra-thin and conformal diffusion barriers encapsulating copper
US6084765A (en) * 1997-12-06 2000-07-04 Samsung Electronics Co., Ltd. Integrated circuit capacitors having recessed oxidation barrier spacers
US6124158A (en) * 1999-06-08 2000-09-26 Lucent Technologies Inc. Method of reducing carbon contamination of a thin dielectric film by using gaseous organic precursors, inert gas, and ozone to react with carbon contaminants
US6144060A (en) * 1997-07-31 2000-11-07 Samsung Electronics Co., Ltd. Integrated circuit devices having buffer layers therein which contain metal oxide stabilized by heat treatment under low temperature
US6180451B1 (en) * 1998-06-29 2001-01-30 United Microelectronics Corp. Method of forming capacitor with a HSG layer
US6200893B1 (en) * 1999-03-11 2001-03-13 Genus, Inc Radical-assisted sequential CVD
US6203613B1 (en) * 1999-10-19 2001-03-20 International Business Machines Corporation Atomic layer deposition with nitrate containing precursors
US20010006835A1 (en) * 1999-12-22 2001-07-05 Min-Soo Kim Method for manufacturing aluminum oxide film for use in a semiconductor device
US20010024387A1 (en) * 1999-12-03 2001-09-27 Ivo Raaijmakers Conformal thin films over textured capacitor electrodes
US20010041250A1 (en) * 2000-03-07 2001-11-15 Werkhoven Christian J. Graded thin films
US6326277B1 (en) * 1999-08-30 2001-12-04 Micron Technology, Inc. Methods of forming recessed hemispherical grain silicon capacitor structures
US6335240B1 (en) * 1998-01-06 2002-01-01 Samsung Electronics Co., Ltd. Capacitor for a semiconductor device and method for forming the same
US6350642B1 (en) * 2000-11-21 2002-02-26 Samsung Electronics Co., Ltd. Method of manufacturing semiconductor memory device including various contact studs
US6368909B2 (en) * 1998-03-30 2002-04-09 Samsung Electronics Co., Ltd. Methods of fabricating integrated circuit ferroelectric capacitors including tensile stress applying layers on the upper electrode thereof
US6376325B1 (en) * 1999-09-21 2002-04-23 Samsung Electronics Co., Ltd. Method for fabricating a ferroelectric device
US6391785B1 (en) * 1999-08-24 2002-05-21 Interuniversitair Microelektronica Centrum (Imec) Method for bottomless deposition of barrier layers in integrated circuit metallization schemes
US6440869B1 (en) * 2000-06-26 2002-08-27 Vanguard International Semiconductor Corporation Method of forming the capacitor with HSG in DRAM
US20020127867A1 (en) * 2001-03-12 2002-09-12 Samsung Electronics Co., Ltd. Semiconductor devices having a hydrogen diffusion barrier layer and methods of fabricating the same
US6509601B1 (en) * 1998-07-31 2003-01-21 Samsung Electronics Co., Ltd. Semiconductor memory device having capacitor protection layer and method for manufacturing the same

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR920010201B1 (en) * 1988-03-04 1992-11-21 가부시끼가이샤 도시바 Semidonductor device and method for manufacturing of the same
JPH07273216A (en) * 1994-03-30 1995-10-20 Toshiba Corp Forming method of metal oxide film
JP3292795B2 (en) * 1995-08-30 2002-06-17 シャープ株式会社 Method for manufacturing semiconductor memory device
US6054331A (en) * 1997-01-15 2000-04-25 Tong Yang Cement Corporation Apparatus and methods of depositing a platinum film with anti-oxidizing function over a substrate
KR100269309B1 (en) * 1997-09-29 2000-10-16 윤종용 Ferroelectric memory devices and fabrication methods therefor
JPH11297959A (en) * 1998-04-15 1999-10-29 Ebara Corp Structure of high-ferroelectric memory cell and manufacture therefor
KR100282459B1 (en) * 1998-10-13 2001-02-15 황철성 Manufacturing method of ferroelectric ram capacitor

Patent Citations (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5374578A (en) * 1992-02-25 1994-12-20 Ramtron International Corporation Ozone gas processing for ferroelectric memory circuits
US5933727A (en) * 1994-03-11 1999-08-03 Micron Technology, Inc. Method for increasing capacitance of an HSG rugged capacitor using a phosphine rich oxidation and subsequent wet etch
US6077774A (en) * 1996-03-29 2000-06-20 Texas Instruments Incorporated Method of forming ultra-thin and conformal diffusion barriers encapsulating copper
US6020243A (en) * 1997-07-24 2000-02-01 Texas Instruments Incorporated Zirconium and/or hafnium silicon-oxynitride gate dielectric
US6144060A (en) * 1997-07-31 2000-11-07 Samsung Electronics Co., Ltd. Integrated circuit devices having buffer layers therein which contain metal oxide stabilized by heat treatment under low temperature
US6084765A (en) * 1997-12-06 2000-07-04 Samsung Electronics Co., Ltd. Integrated circuit capacitors having recessed oxidation barrier spacers
US6261849B1 (en) * 1997-12-06 2001-07-17 Samsung Electronics Co., Ltd. Method of forming integrated circuit capacitors having recessed oxidation barrier spacers and method of forming same
US6335240B1 (en) * 1998-01-06 2002-01-01 Samsung Electronics Co., Ltd. Capacitor for a semiconductor device and method for forming the same
US6368909B2 (en) * 1998-03-30 2002-04-09 Samsung Electronics Co., Ltd. Methods of fabricating integrated circuit ferroelectric capacitors including tensile stress applying layers on the upper electrode thereof
US6180451B1 (en) * 1998-06-29 2001-01-30 United Microelectronics Corp. Method of forming capacitor with a HSG layer
US6509601B1 (en) * 1998-07-31 2003-01-21 Samsung Electronics Co., Ltd. Semiconductor memory device having capacitor protection layer and method for manufacturing the same
US6200893B1 (en) * 1999-03-11 2001-03-13 Genus, Inc Radical-assisted sequential CVD
US6124158A (en) * 1999-06-08 2000-09-26 Lucent Technologies Inc. Method of reducing carbon contamination of a thin dielectric film by using gaseous organic precursors, inert gas, and ozone to react with carbon contaminants
US6391785B1 (en) * 1999-08-24 2002-05-21 Interuniversitair Microelektronica Centrum (Imec) Method for bottomless deposition of barrier layers in integrated circuit metallization schemes
US6326277B1 (en) * 1999-08-30 2001-12-04 Micron Technology, Inc. Methods of forming recessed hemispherical grain silicon capacitor structures
US6376325B1 (en) * 1999-09-21 2002-04-23 Samsung Electronics Co., Ltd. Method for fabricating a ferroelectric device
US6203613B1 (en) * 1999-10-19 2001-03-20 International Business Machines Corporation Atomic layer deposition with nitrate containing precursors
US20010024387A1 (en) * 1999-12-03 2001-09-27 Ivo Raaijmakers Conformal thin films over textured capacitor electrodes
US20010006835A1 (en) * 1999-12-22 2001-07-05 Min-Soo Kim Method for manufacturing aluminum oxide film for use in a semiconductor device
US20010041250A1 (en) * 2000-03-07 2001-11-15 Werkhoven Christian J. Graded thin films
US6440869B1 (en) * 2000-06-26 2002-08-27 Vanguard International Semiconductor Corporation Method of forming the capacitor with HSG in DRAM
US6350642B1 (en) * 2000-11-21 2002-02-26 Samsung Electronics Co., Ltd. Method of manufacturing semiconductor memory device including various contact studs
US20020127867A1 (en) * 2001-03-12 2002-09-12 Samsung Electronics Co., Ltd. Semiconductor devices having a hydrogen diffusion barrier layer and methods of fabricating the same

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7535695B2 (en) * 2003-05-20 2009-05-19 Micron Technology, Inc. DRAM cells and electronic systems
US20060274477A1 (en) * 2003-05-20 2006-12-07 Cem Basceri DRAM cells and electronic systems
US9012299B2 (en) 2007-10-30 2015-04-21 Spansion Llc Metal-insualtor-metal (MIM) device and method of formation thereof
US20090109598A1 (en) * 2007-10-30 2009-04-30 Spansion Llc Metal-insulator-metal (MIM) device and method of formation thereof
US8445913B2 (en) * 2007-10-30 2013-05-21 Spansion Llc Metal-insulator-metal (MIM) device and method of formation thereof
US20130237030A1 (en) * 2007-10-30 2013-09-12 Spansion Llc Metal-insulator-metal (mim) device and method of formation thereof
US8828837B2 (en) * 2007-10-30 2014-09-09 Spansion Llc Metal-insulator-metal (MIM) device and method of formation thereof
US20090200533A1 (en) * 2008-02-08 2009-08-13 Klaus-Dieter Ufert Resistive Memory Element and Method of Fabrication
US7741630B2 (en) * 2008-02-08 2010-06-22 Qimonda Ag Resistive memory element and method of fabrication
US20090297696A1 (en) * 2008-05-29 2009-12-03 Viljami Pore Methods for forming conductive titanium oxide thin films
US9646820B2 (en) 2008-05-29 2017-05-09 Asm International N.V. Methods for forming conductive titanium oxide thin films
US8945675B2 (en) * 2008-05-29 2015-02-03 Asm International N.V. Methods for forming conductive titanium oxide thin films
US8907449B2 (en) 2008-10-28 2014-12-09 Taiyo Yuden Co., Ltd. Thin film MIM capacitors and manufacturing method therefor
US20110193194A1 (en) * 2008-10-28 2011-08-11 Taiyo Yuden Co., Ltd. Thin film mim capacitors and manufacturing method therefor
US20150264815A1 (en) * 2014-03-11 2015-09-17 Ibiden Co., Ltd. Substrate with built-in capacitor and method for manufacturing substrate with built-in capacitor
US9655249B2 (en) * 2014-03-11 2017-05-16 Ibiden Co., Ltd. Substrate with built-in capacitor and method for manufacturing substrate with built-in capacitor
US9523148B1 (en) 2015-08-25 2016-12-20 Asm Ip Holdings B.V. Process for deposition of titanium oxynitride for use in integrated circuit fabrication
US9540729B1 (en) 2015-08-25 2017-01-10 Asm Ip Holding B.V. Deposition of titanium nanolaminates for use in integrated circuit fabrication
US10002755B2 (en) 2015-08-25 2018-06-19 Asm Ip Holding B.V. Process for deposition of titanium oxynitride for use in integrated circuit fabrication
US10460928B2 (en) 2015-08-25 2019-10-29 Asm Ip Holding B.V. Process for deposition of titanium oxynitride for use in integrated circuit fabrication
US10546744B2 (en) 2015-08-25 2020-01-28 Asm Ip Holding B.V. Process for deposition of titanium oxynitride for use in integrated circuit fabrication
US11195712B2 (en) 2015-08-25 2021-12-07 Asm Ip Holding B.V. Process for deposition of titanium oxynitride for use in integrated circuit fabrication

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