US20050042859A1 - Etching process for high-k gate dielectrics - Google Patents
Etching process for high-k gate dielectrics Download PDFInfo
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- US20050042859A1 US20050042859A1 US10/961,707 US96170704A US2005042859A1 US 20050042859 A1 US20050042859 A1 US 20050042859A1 US 96170704 A US96170704 A US 96170704A US 2005042859 A1 US2005042859 A1 US 2005042859A1
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- 238000000034 method Methods 0.000 title claims abstract description 68
- 238000005530 etching Methods 0.000 title claims description 9
- 239000003989 dielectric material Substances 0.000 title description 4
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 37
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 21
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 235000011149 sulphuric acid Nutrition 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 claims description 7
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 6
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 claims description 5
- 239000011261 inert gas Substances 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 229910004541 SiN Inorganic materials 0.000 claims description 3
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 claims 3
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims 3
- 229910006504 ZrSO4 Inorganic materials 0.000 claims 1
- 239000006117 anti-reflective coating Substances 0.000 description 21
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 8
- 229910021332 silicide Inorganic materials 0.000 description 7
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 5
- 229910052786 argon Inorganic materials 0.000 description 4
- 239000007943 implant Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 3
- 229910052731 fluorine Inorganic materials 0.000 description 3
- 239000011737 fluorine Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 229910000167 hafnon Inorganic materials 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 235000011007 phosphoric acid Nutrition 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 229910052845 zircon Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000012864 cross contamination Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
- H01L21/31122—Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
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Abstract
A method of forming a gate electrode comprising the following steps. A substrate having a high-k gate dielectric layer formed thereover is provided. A gate layer is formed over the high-k gate dielectric layer. A gate ARC layer is formed over the gate layer. The gate ARC layer and the gate layer are patterned to form a patterned gate ARC layer and a patterned gate layer. The high-k gate dielectric layer not under the patterned gate layer is partially etched and a smooth exposed upper surface of the patterned gate layer is formed. The partially etched high-k gate dielectric layer portions not under the patterned gate layer are removed to form the gate electrode comprised of the patterned gate layer and the etched high-k gate dielectric layer.
Description
- This application is a divisional of U.S. patent application Ser. No. 10/146,315, filed May 15, 2002, and entitled, “Etching Process for High-K gate Dielectrics,” assigned to a common assignee and hereby incorporated by reference in its entirety.
- The present invention relates generally to semiconductor fabrication and more specifically to processes of etching high-k gate dielectric layers.
- High dielectric constant (high-k) dielectrics were thought to replace silicon oxide (SiO2) in the near future due to their low leakage current as compared to SiO2 of the same equivalent oxide thickness (EOT). But there have been many problems in attempting to incorporate high-k dielectrics into the current complimentary metal-oxide semiconductor (CMOS) process flow such as thermal instability (the high-k material degrades under high temperature), transconductance, cross-contamination (metal out-diffusion from high-k dielectric metal oxides during thermal processes) and Gm/Idsat degradation (due to the presence of fixed charges and unstable high-k dielectric/poly-Si interface, mobility degradation of the MOS).
- The high-k material has a slow etch rate compared to SiO2 and further, the high-k gate dielectric reacts with the poly-Si gate to form an interfacial layer therebetween which is difficult to etch. In the high-k gate dielectric etching process, H3PO4 and HF based chemical etches are not considered because of the concerns on poly-Si gate damage and shallow trench isolation (STI) over-loss (i.e. the STI will be over-etched as compared to the high-k gate dielectric layer). The present embodiments focus upon these etching issues.
- U.S. Pat. No. 6,271,094 B1 to Boyd et al. describes a high-k layer and gate patterning process.
- U.S. Pat. No. 6,210,999 B1 to Gardner et al. describes a high-k gate dielectric and gate etch process.
- U.S. Pat. No. 6,069,381 to Black et al. and U.S. Pat. No. 6,100,173 to Gardner et al. describe other high-k gate dielectric and gate patterning processes.
- The present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which like reference numerals designate similar or corresponding elements, regions and portions and in which:
- FIGS. 1 to 5 schematically illustrate a first embodiment of the present invention.
- FIGS. 6 to 9 schematically illustrate a second embodiment of the present invention.
- Unless otherwise specified, all structures, layers, steps, methods, etc. may be formed or accomplished by conventional steps or methods known in the prior art.
- First Embodiment
- Initial Structure
- As shown in
FIG. 1 ,structure 10 may include (shallow trench isolation)structures 12.Structure 10 is preferably a silicon substrate and is understood to possibly include a semiconductor wafer or substrate.STIs 12 are preferably comprised of plasma oxide formed by an high-density plasma (HDP) process or a sub-atmospheric chemical vapor deposition (SACVD) process. - High-k gate
dielectric layer 14 is formed oversilicon substrate 10 to a thickness of preferably from about 20 to 100 Å and more preferably from about 30 to 50 Å. High-k gatedielectric layer 14 is preferably comprised of ZrSiO4, HfSiO4, LaSiO4, YSiO4, ZrSixOy or HfSixOy and is more preferably comprised of ZrSixOy or HfSixOy. - In a step of the first embodiment,
gate layer 16 is formed over high-k gatedielectric layer 14 to a thickness of preferably from about 400 to 3000 Å and more preferably from about 1200 to 1800 Å which is slightly thicker than in conventional processes so as to compensate for the subsequent etch loss from the Ar sputter or the F-based-chemistry plasma etch 24 as described below. -
Gate layer 16 is preferably comprised of polysilicon (poly-Si), polycide or a poly-Si/poly-Ge stack structure and is more preferably comprised of poly-Si. - High-k gate
dielectric layer 14 reacts with the poly-Si gate layer 16 to forminterfacial layer 18 which is very hard to etch.Interfacial layer 18 is preferably from about 3 to 10 Å thick and is more preferably from about 3 to 5 Å thick. - Gate anti-reflective coating (ARC) 20 is formed over poly-
Si gate layer 16 to a thickness of preferably from about 100 to 500 Å and more preferably from about 200 to 400 Å. Gate ARC 20 is preferably comprised of SiN, SiON, silicon oxide, organic ARC or an organic ARC/SiON stack structure and is more preferably comprised of an organic ARC/SiON stack structure. - Gate Patterning
- As shown in
FIG. 2 ,gate ARC 20 and poly-Si gate layer 16 are patterned to form patternedgate ARC 20′ and patterned poly-Si gate 16′. ARC 20 and poly-Si gate 16 may be patterned using, for example, an overlying patterned photoresist layer (not shown). - Removal of Patterned Gate ARC 20
- As shown in
FIG. 3 , patternedgate ARC 20′ is stripped from patterned poly-Si gate layer 16′. This leaves theupper surface 22 of patterned poly-Si gate layer 16′ rough. - Argon (Ar) Sputter or Fluorine (F)-Based-Chemistry Plasma Etch 24—
- In another step of the present embodiment, and as shown in
FIG. 4 , the structure ofFIG. 3 is subjected to an argon (Ar) sputter or a fluorine (F)-based-chemistry plasma etch 24 which thins patternedgate layer 16′ to form thinner patternedgate layer 16″ having a smoothupper surface 22′. Ar sputter/F-based-chemistry plasma etch 24 also removes: (1) the exposed portions ofinterfacial layer 18 not under patternedgate layer 16′ to form patternedinterfacial layer 18′; and (2) a portion of the exposed portions of high-k gatedielectric layer 14 not under patternedgate layer 16′ to form partially etched high-k gatedielectric layer 14′. - Thinner patterned
gate layer 16″ has a thickness of preferably from about 300 to 2000 Å and more preferably from about 1000 to 1500 Å. - The F-based-chemistry of the F-based-chemistry plasma etch 24 is preferably: (1) CxFy such as CF4, C2F6, C4F6 or C4F8; (2) CxHyFz such as CHF3, CH2F2 or CH3F; or SxFy such as SF6; and is more preferably: CF4, C4F6, CH2F2 or CH3F. The F-based-chemistry may also include an inert gas such as helium (He) or Ar, for example: CF4/Ar/O2 or CF4/Ar and is more preferably CF4/Ar/O2.
- The smooth
upper surface 22′ of patternedgate layer 16′ is better for any subsequent silicide process to form a silicide portion over patternedgate layer 16′. - If an Ar sputter 24 is selected, it is conducted at the following parameters:
-
- Ar: preferably from about 20 to 500 sccm; and more preferably from about 100 to 200 sccm;
- power: preferably from about 200 to 2000 Watts; and more preferably from about 300 to 500 Watts;
- temperature: preferably from about 0 to 100° C.; and more preferably from about 80 to 90° C.;
- pressure: preferably from about 5 to 50 mTorr; and more preferably from about 20 to 50 mTorr; and
- time: preferably from about 5 to 30 seconds; and more preferably from about 5 to 10 seconds.
If an F-based-chemistry plasma etch 24 is selected, it is conducted at the following parameters: - CF4: preferably from about 1 to 100 sccm; and more preferably from about 5 to 30 sccm;
- Ar: preferably from about 10 to 1000 sccm; and more preferably from about 50 to 300 sccm;
- top power: preferably from about 100 to 1000 Watts; and more preferably from about 300 to 700 Watts;
- bottom power: preferably from about 0 to 500 Watts; and more preferably from about 50 to 200 Watts; and
- pressure: preferably from about 1 to 200 mTorr; and more preferably from about 2 to 50 mTorr.
Wet Etch 26 to Remove Remaining Exposed Portions of High-K GateDielectric Layer 14′
- As shown in
FIG. 5 , awet etch 26 is used to remove the remaining exposed portions of partially etched high-kgate dielectric layer 14′ from oversilicon substrate 10 not under patternedgate layer 16′ to form etched high-kgate dielectric layer 14″. Patternedgate layer 16′, patternedinterfacial layer 18′ and etched high-kgate dielectric layer 14″comprise gate electrode 28. -
Wet etch 26 is preferably a sulfuric acid (H2SO4) wet etch conducted at the following parameters: -
- H2SO4: preferably from about 2 to 20% by volume; and more preferably from about 2 to 5% by volume;
- temperature: preferably from about 25 to 130° C. and more preferably from about 25 to 50° C.; and
- time: preferably from about 10 to 30 seconds and more preferably from about 10 to 20 seconds.
- Further processing may then continue such as, for example, silicide formation, LDD implants, gate sidewall spacer formation, HDD implants, etc.
- By using an H2SO4
wet etch 26 instead of an H3PO4 wet etch chemistry, the poly-Si sidewalls the source/drain (S/D) areas of the silicon substrate adjacent the patternedgate layer 16″/high-kgate dielectric layer 14″. Alsoless STI 12 over-loss will be achieved than if an HF wet etch chemistry were used. - An acceptable etching rate is achieved by using the two step etch process of the first embodiment of the present invention, i.e. (1) Ar sputter 24 followed by (2) an H2SO4
wet etch 26. Another point of the present embodiment is that neither the Ar sputter 24 nor the H2SO4wet etch 26 require masking due the selectivity of each. - Second Embodiment
- Initial Structure
- As shown in
FIG. 6 ,structure 110 may include (shallow trench isolation)structures 112.Structure 110 is preferably a silicon substrate and is understood to possibly include a semiconductor wafer or substrate.STIs 112 are preferably comprised of HDP oxide or SACVD oxide. - High-k
gate dielectric layer 114 is formed oversilicon substrate 110 to a thickness of preferably from about 10 to 50 Å and more preferably from about 20 to 50 Å. High-kgate dielectric layer 114 is preferably comprised of ZrSiO4, HfSiO4, LaSiO4, YSiO4, ZrSixOy or HfSixOy and is more preferably comprised of ZrSixOy or HfSixOy. -
Gate layer 116 is formed over high-kgate dielectric layer 114 to a thickness of preferably from about 400 to 3000 Å and more preferably from about 1200 to 1800 Å which is comparable to the thickness in conventional processes. -
Gate layer 116 is preferably comprised of polysilicon (poly-Si), polycide or a poly-Si/poly-Ge stack structure and is more preferably comprised of poly-Si. - High-k
gate dielectric layer 114 reacts with the poly-Si gate layer 116 to forminterfacial layer 118 which is very hard to etch.Interfacial layer 118 is preferably from about 3 to 10 Å thick and is more preferably from about 3 to 5 Å thick. - Gate anti-reflective coating (ARC) 120 is formed over poly-
Si gate layer 116 to a thickness of preferably from about 100 to 500A and more preferably from about 200 to 400 Å.Gate ARC 120 is preferably comprised of SiN, SiON, silicon oxide, organic ARC or an organic ARC/SiON stack structure and is more preferably comprised of an organic ARC/SiON stack structure. - Gate Patterning
- As shown in
FIG. 7 ,gate ARC 120 and poly-Si gate layer 116 are patterned to form patternedgate ARC 120′ and patterned poly-Si gate 116′.ARC 120 and poly-Si gate 116 may be patterned using, for example, an overlying patterned photoresist layer (not shown). - Argon (Ar) Sputter or Plasma Etch with a Fluorine (F)-Based-
Chemistry 124 - It is noted that the patterned
gate ARC 120′ is not removed from over patterned poly-Si gate layer 116′ before the Ar sputter/F-based-chemistry plasma etch 124. - In one step of the embodiment, and as shown in
FIG. 8 , the structure ofFIG. 7 is subjected to an argon (Ar) sputter/F-based-chemistry plasma etch 124 which removesgate ARC 120 from over patterned poly-Si gate layer 116′, leaving theupper surface 122 of exposed patterned poly-Si gate layer 116′ smooth.Gate ARC 120 minimizes poly-Si loss from the patterned poly-Si gate layer 116′. Ar sputter/F-based-chemistry plasma etch 124 also removes: (1) the exposed portions ofinterfacial layer 118 not under patternedgate layer 116′ to form patternedinterfacial layer 118′; and (2) a portion of the exposed portions of high-kgate dielectric layer 114 not under patternedgate layer 116′ to form partially etched high-kgate dielectric layer 114′. - The F-based-chemistry of the F-based-
chemistry plasma etch 124 is preferably: (1) CxFy such as CF4, C2F6, C4F6 or C4F8; (2) CxHyFz such as CHF3, CH2F2 or CH3F; or SxFy such as SF6; and is more preferably: CF4, C4F6, CH2F2 or CH3F. The F-based-chemistry may also include an inert gas such as helium (He) or Ar, for example: CF4/Ar/O2 or CF4/Ar and is more preferably CF4/Ar/O2. - The smooth
upper surface 122′ of patternedgate layer 16′ is better for any subsequent silicide process to form a silicide portion over patternedgate layer 116′. - If an
Ar sputter 124 is selected, it is conducted at the following parameters: -
- Ar: preferably from about 20 to 500 sccm; and more preferably from about 100 to 200 sccm;
- power: preferably from about 200 to 2000 Watts; and more preferably from about 300 to 500 Watts;
- temperature: preferably from about 0 to 100° C.; and more preferably from about 80 to 90° C.;
- pressure: preferably from about 5 to 50 mTorr; and more preferably from about 20 to 50 mTorr; and
- time: preferably from about 5 to 30 seconds; and more preferably from about 5 to 10 seconds.
- If an F-based-
chemistry plasma etch 124 is selected, it is conducted at the following parameters: -
- CF4: preferably from about 1 to 100 sccm; and more preferably from about 5 to 30 sccm;
- Ar: preferably from about 10 to 1000 sccm; and more preferably from about 50 to 300 sccm;
- top power: preferably from about 100 to 1000 Watts; and more preferably from about 300 to 700 Watts;
- bottom power: preferably from about 0 to 500 Watts; and more preferably from about 50 to 200 Watts; and
- pressure: preferably from about 1 to 200 mTorr; and more preferably from about 2 to 50 mTorr.
Wet Etch 126 to Remove Remaining Exposed Portions of High-KGate Dielectric Layer 114′
- As shown in
FIG. 9 , awet etch 126 is used to remove the remaining exposed portions of partially etched high-kgate dielectric layer 114′ from oversilicon substrate 110 not under patternedgate layer 116′ to form etched high-kgate dielectric layer 114″. Patternedgate layer 116′, patternedinterfacial layer 118′ and etched high-kgate dielectric layer 114″comprise gate electrode 128. -
Wet etch 126 is preferably a sulfuric acid (H2SO4) wet etch conducted at the following parameters: -
- H2SO4: preferably from about 2 to 20% by volume; and more preferably from about 2 to 5% by volume;
- temperature: preferably from about 25 to 130° C. and more preferably from about 25 to 50° C.; and
- time: preferably from about 10 to 30 seconds and more preferably from about 10 to 20 seconds.
- Further processing may then continue such as, for example, silicide formation, LDD implants, gate sidewall spacer formation, HDD implants, etc.
- By using an H2SO4
wet etch 126 instead of an H3PO4 wet etch chemistry, the poly-Si sidewalls the source/drain (S/D) areas of the silicon substrate adjacent the patternedgate layer 116′/high-kgate dielectric layer 114″. Alsoless STI 112 over-loss will be achieved than if an HF wet etch chemistry were used. Further, poly-Si gate layer 116 is deposited to a thickness substantially equal to those thicknesses used in conventional processes. - Advantages
- The advantages of one or more embodiments of the present invention include: a smooth upper surface of the patterned poly-Si gate layer is achieved which provides for better subsequent silicide process formation; the sidewalls of the patterned poly-Si gate layer are not deleteriously affected by the wet etch process; the S/D areas of the silicon substrate are not deleteriously affected by the wet etch process; less STI over-loss is achieved; acceptable etching rates are achieved by using the two step etching process, i.e. the Ar sputter and the H2SO4 wet etch; and the poly-Si gate layer is deposited to a thickness substantially equal to those thicknesses used in conventional processes.
- While particular embodiments of the present invention have been illustrated and described, it is not intended to limit the invention, except as defined by the following claims.
Claims (37)
1. A method of forming a gate electrode, comprising the steps of:
providing a substrate having a high-k gate dielectric layer formed thereover;
forming a gate layer over the high-k gate dielectric layer;
forming a gate ARC layer over the gate layer;
patterning the gate ARC layer and the gate layer to form a patterned gate ARC layer and a patterned gate layer;
partially etching the high-k gate dielectric layer not under the patterned gate layer using an F-based-chemistry plasma etch including an F-based-chemistry, and forming a smooth exposed upper surface of the patterned gate layer; and
then removing the partially etched high-k gate dielectric layer portions not under the patterned gate layer to form the gate electrode comprised of the patterned gate layer and the etched high-k gate dielectric layer.
2. The method of claim 1 , wherein the high-k gate dielectric layer not under the patterned gate layer is etched using an F-based-chemistry plasma etch including an F-based-chemistry selected from the group consisting of CxFy, CxHyFz and SxFy.
3. The method of claim 1 , wherein the high-k gate dielectric layer not under the patterned gate layer is etched using an F-based-chemistry plasma etch including an F-based-chemistry selected from the group consisting of CF4, C2F6, C4F6, C4F8, CHF3, CH2F2, CH3F, SF6, CF4/Ar/O2 and CF4/Ar.
4. The method of claim 1 , wherein the high-k gate dielectric layer not under the patterned gate layer is etched using an F-based-chemistry plasma etch including an F-based-chemistry selected from the group consisting of CF4/Ar/O2 and CF4/Ar.
5. The method of claim 1 , wherein the high-k gate dielectric layer not under the patterned gate layer is etched using an F-based-chemistry plasma etch including an F-based-chemistry including an inert gas.
6. The method of claim 1 , wherein the high-k gate dielectric layer not under the patterned gate layer is etched using an F-based-chemistry plasma etch conducted at the following parameters:
CF4: from about 1 to 100 sccm;
Ar: from about 10 to 1000 sccm;
top power: from about 100 to 1000 Watts;
bottom power: from about 0 to 500 Watts; and
pressure: from about 1 to 200 mTorr.
7. The method of claim 1 , wherein the high-k gate dielectric layer not under the patterned gate layer is etched using an F-based-chemistry plasma etch conducted at the following parameters:
CF4: from about 5 to 30 sccm;
Ar: from about 50 to 300 sccm;
top power: from about 300 to 700 Watts;
bottom power: from about 50 to 200 Watts; and
pressure: from about 2 to 50 mTorr.
8. The method of claim 1 , wherein the patterned gate ARC layer is removed from over the patterned gate layer by the Ar sputter or the F-based-chemistry plasma etch.
9. The method of claim 1 , wherein the patterned gate ARC layer is removed from over the patterned gate layer by the Ar sputter or the F-based-chemistry plasma etch and whereby the patterned gate ARC layer minimizes loss of the patterned gate layer during the Ar sputter or the F-based-chemistry plasma etch.
10. The method of claim 1 , wherein the high-k gate dielectric layer not under the patterned gate layer is etched using an Ar sputter or an F based chemistry plasma and the partially etched high-k gate dielectric layer portions not under the patterned gate layer is etched using an H2SO4 wet etch chemistry process.
11. A method of forming a gate electrode, comprising the steps of:
providing a substrate having a high-k gate dielectric layer formed thereover;
forming a gate layer over the high-k gate dielectric layer;
forming a gate ARC layer over the gate layer;
patterning the gate ARC layer and the gate layer to form a patterned gate ARC layer and a patterned gate layer;
removing the patterned ARC layer from over the patterned gate layer;
subjecting the structure to an Ar sputter or an F-based-chemistry plasma etch to partially etch the high-k gate dielectric layer not under the patterned gate layer using an F-based-chemistry plasma etch, and to form a smooth exposed upper surface of the patterned gate layer; and
removing the partially etched high-k gate dielectric layer portions not under the patterned gate layer using an H2SO4 wet etch chemistry process to form the gate electrode comprised of the patterned gate layer and the etched high-k gate dielectric layer.
12. The method of claim 11 , wherein the partially etched the high-k gate dielectric layer not under the patterned gate layer is etched using an F-based-chemistry plasma etch including an F-based-chemistry selected from the group consisting of CxFy, CxHyFz and SxFy.
13. The method of claim 11 , wherein the partially etched the high-k gate dielectric layer not under the patterned gate layer is etched using an F-based-chemistry plasma etch including an F-based-chemistry selected from the group consisting of CF4, C2F6, C4F6, C4F8, CHF3, CH2F2, CH3F, SF6, CF4/Ar/O2 and CF4/Ar.
14. The method of claim 11 , wherein the partially etched the high-k gate dielectric layer not under the patterned gate layer is etched using an F-based-chemistry plasma etch including an F-based-chemistry selected from the group consisting of CF4/Ar/O2 and CF4/Ar.
15. The method of claim 11 , wherein the partially etched the high-k gate dielectric layer not under the patterned gate layer is etched using an F-based-chemistry plasma etch including an F-based-chemistry including an inert gas.
16. The method of claim 11 , wherein the partially etched the high-k gate dielectric layer not under the patterned gate layer is etched using an F-based-chemistry plasma etch conducted at the following parameters:
CF4: from about 1 to 100 sccm;
Ar: from about 10 to 1000 sccm;
top power: from about 100 to 1000 Watts;
bottom power: from about 0 to 500 Watts; and
pressure: from about 1 to 200 mTorr.
17. The method of claim 11 , wherein the partially etched the high-k gate dielectric layer not under the patterned gate layer is etched using an F-based-chemistry plasma etch conducted at the following parameters:
CF4: from about 5 to 30 sccm;
Ar: from about 50 to 300 sccm;
top power: from about 300 to 700 Watts;
bottom power: from about 50 to 200 Watts; and
pressure: from about 2 to 50 mTorr.
18. A method of forming a gate electrode, comprising the steps of:
providing a substrate having a high-k gate dielectric layer formed thereover;
forming a gate layer over the high-k gate dielectric layer;
forming a gate ARC layer over the gate layer;
patterning the gate ARC layer and the gate layer to form a patterned gate ARC layer and a patterned gate layer;
subjecting the structure to an Ar sputter or an F-based-chemistry plasma etch to partially etch the high-k gate dielectric layer not under the patterned gate layer and to remove the patterned ARC layer leaving a smooth exposed upper surface of the patterned gate layer; and
removing the partially etched high-k gate dielectric layer portions not under the patterned gate layer using an H2SO4 wet etch chemistry process to form the gate electrode comprised of the patterned gate layer and the etched high-k gate dielectric layer.
19. The method of claim 18 , wherein the substrate is a silicon substrate; the high-k gate dielectric layer is comprised of a material selected from the group consisting of ZrSO4, HfSO4, LaSO4, YSO4, ZrSixOy and HfSixOy; the gate layer is comprised of a material selected from the group consisting of polysilicon, polycide and a poly-Si/poly-Ge stack structure; and the gate ARC layer is comprised of a material selected from the group consisting of SiN, SiON, silicon oxide, organic ARC and an organic ARC/SiON stack structure.
20. The method of claim 18 , wherein the substrate is a silicon substrate; the high-k gate dielectric layer is comprised of a material selected from the group consisting of ZrSixOy and HfSixOy; the gate layer is comprised of polysilicon; and the gate ARC layer is comprised of an organic ARC/SiON stack structure.
21. The method of claim 18 , wherein the partially etched the high-k gate dielectric layer not under the patterned gate layer is etched using an Ar sputter conducted at the following parameters:
Ar: from about 20 to 500 sccm;
power: from about 200 to 2000 Watts;
temperature: from about 0 to 100° C.;
pressure: from about 5 to 50 mTorr; and
time: from about 5 to 30 seconds.
22. The method of claim 18 , wherein the partially etched the high-k gate dielectric layer not under the patterned gate layer is etched using an Ar sputter conducted at the following parameters:
Ar: from about 100 to 200 sccm;
power: from about 300 to 500 Watts;
temperature: from about 80 to 90° C.;
pressure: from about 20 to 50 mTorr; and
time: from about 5 to 10 seconds.
23. The method of claim 18 , wherein the partially etched the high-k gate dielectric layer not under the patterned gate layer is etched using an F-based-chemistry plasma etch including an F-based-chemistry selected from the group consisting of CxFy, CxHyFz and SxFy.
24. The method of claim 18 , wherein the partially etched the high-k gate dielectric layer not under the patterned gate layer is etched using an F-based-chemistry plasma etch including an F-based-chemistry selected from the group consisting of CF4, C2F6, C4F6, C4F8, CHF3, CH2F2, CH3F, SF6, CF4/Ar/O2 and CF4/Ar.
25. The method of claim 18 , wherein the partially etched the high-k gate dielectric layer not under the patterned gate layer is etched using an F-based-chemistry plasma etch including an F-based-chemistry selected from the group consisting of CF4/Ar/O2 and CF4/Ar.
26. The method of claim 18 , wherein the partially etched the high-k gate dielectric layer not under the patterned gate layer is etched using an F-based-chemistry plasma etch including an F-based-chemistry including an inert gas.
27. The method of claim 18 , wherein the partially etched the high-k gate dielectric layer not under the patterned gate layer is etched using an F-based-chemistry plasma etch conducted at the following parameters:
CF4: from about 1 to 100 sccm;
Ar: from about 10 to 1000 sccm;
top power: from about 100 to 1000 Watts;
bottom power: from about 0 to 500 Watts; and
pressure: from about 1 to 200 mTorr.
28. The method of claim 18 , wherein the partially etched the high-k gate dielectric layer not under the patterned gate layer is etched using an F-based-chemistry plasma etch conducted at the following parameters:
CF4: from about 5 to 30 sccm;
Ar: from about 50 to 300 sccm;
top power: from about 300 to 700 Watts;
bottom power: from about 50 to 200 Watts; and
pressure: from about 2 to 50 mTorr.
29. The method of claim 18 , wherein the H2SO4 wet etch chemistry process is conducted at the following parameters:
H2SO4: from about 2 to 20% by volume;
temperature: from about 25 to 130° C.; and
time: from about 10 to 30 seconds.
30. The method of claim 18 , wherein the H2SO4 wet etch chemistry process is conducted at the following parameters:
H2SO4: from about 2 to 5% by volume;
temperature: from about 25 to 50° C.; and
time: from about 10 to 20 seconds.
31. The method of claim 18 , wherein the high-k gate dielectric layer interacts with the gate layer to form an interfacial layer therebetween.
32. The method of claim 18 , wherein the high-k gate dielectric layer interacts with the gate layer to form an interfacial layer therebetween; and wherein the Ar sputter or the F-based-chemistry plasma etch also etches and removes the interfacial layer not under the patterned gate layer.
33. The method of claim 18 , wherein the substrate further includes STIs formed therein adjacent to the high-k gate dielectric layer.
34. The method of claim 18 , wherein the substrate further includes STIs formed therein adjacent to the high-k gate dielectric layer; and wherein the STIs are not substantially affected by the H2SO4 wet etch chemistry process.
35. The method of claim 18 , wherein high-k gate dielectric layer has a thickness of from about 10 to 50 Å; the gate layer has a thickness of from about 400 to 3000 Å; and the gate ARC layer has a thickness of from about 100 to 500 Å.
36. The method of claim 18 wherein high-k gate dielectric layer has a thickness of from about 20 to 50 Å; the gate layer has a thickness of from about 1200 to 1800 Å; and the gate ARC layer has a thickness of from about 200 to 400 Å.
37. The method of claim 18 , wherein the patterned gate ARC layer minimizes loss of the patterned gate layer during the Ar sputter or the F-based-chemistry plasma etch.
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