|Publication number||US20040108217 A1|
|Application number||US 10/313,760|
|Publication date||10 Jun 2004|
|Filing date||5 Dec 2002|
|Priority date||5 Dec 2002|
|Also published as||CN1720354A, EP1567695A1, US20050230263, WO2004053202A1|
|Publication number||10313760, 313760, US 2004/0108217 A1, US 2004/108217 A1, US 20040108217 A1, US 20040108217A1, US 2004108217 A1, US 2004108217A1, US-A1-20040108217, US-A1-2004108217, US2004/0108217A1, US2004/108217A1, US20040108217 A1, US20040108217A1, US2004108217 A1, US2004108217A1|
|Original Assignee||Dubin Valery M.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (17), Referenced by (29), Classifications (11), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
 The present invention relates to the field of microelectronic device processing, and more particularly to a method of forming a copper interconnect structure utilizing electroplating and/or electroless techniques and structures formed thereby.
 Transistors, as is well known in the art, are the building blocks of all integrated circuits. Modern integrated circuits interconnect literally millions of densely configured transistors that perform a wide variety of functions. To achieve such a dramatic increase in the density of circuit components has required microelectronic manufacturers to scale down the physical dimensions of the circuit elements, as well as to utilize multiple levels of interconnection structures used to connect the circuit elements into functional circuitry.
 One such interconnection process is known as the damascene process (FIG. 5), in which dielectric layers 202 and 202′ are deposited over a substrate 200. Vias 204, 204′ and trenches 206, 206′ are etched into the dielectric layers 202, 202′. Metal layers 208, 208′, such as copper or aluminum, is then formed over the vias 204, 204′ and trenches 206, 206′. This process can be repeated to achieve interconnection, through the trenches and vias, of multiple layers of metallization.
 The utilization of copper metal in a damascene structure has many advantages, for example its lower electrical resistance as compared with previously used metals, such as aluminum. One technique for depositing copper in a damascene structure is by electroless deposition, which is attractive because of its lower cost and high quality of deposition. In electroless plating, metal deposition occurs by a chemical reduction reaction in an aqueous solution which contains a reducing agent, wherein no external power supply is needed. However, electroless deposition requires the activation of a nonconductive surface, for example by providing a seed layer, in order to electrolessly deposit the metal.
 However, there are problems associated with the use of copper as an interconnect metal in a damascene structure. One such problem is that copper diffuses or drifts easily into the dielectric layers 202, 202′ (referring again to FIG. 5), thus forming shorts between adjacent circuit elements. Copper interconnect structures must therefore be encapsulated by diffusion barrier layers, such as tantalum, tantalum nitride, titanium nitride (TiN) or titanium tungsten (TiW). Unfortunately, the addition of the diffusion barrier layer can increase the effective dielectric constant of the copper interconnect structure, which results in an increase in the resistance-capacitance (RC) delay which degrades the electrical performance of the device.
 Another problem associated with copper metallization is that copper is readily oxidized, especially during subsequent processing steps. The oxidized copper degrades the electrical and mechanical properties of the copper interconnect. Accordingly, an hermetic encapsulating layer is generally employed in order to provide corrosion resistance for the copper layer, such encapsulating materials may include silicon carbide (SiC) and silicon nitride (SiN). This encapsulating layer may also serve as an etch stop, which prevents over-etching of the copper layer during subsequent processing steps. However, this encapsulating layer can also increase the effective dielectric constant of the copper interconnect structure.
 Yet another problem encountered with copper metallization is the electromigration of copper atoms at high current densities, which can result in voids in the metal interconnect structure. One method of reducing the amount of electromigration is to alloy the copper metal with aluminum, tin, indium or silicon; however, this may increase the copper resistance significantly.
 Accordingly, there is a need for an improved copper interconnect fabrication process and structure that increases copper corrosion resistance and/or oxidation resistance, increases electromigration resistance, and/or decreases the effective dielectric constant of the copper interconnect structure.
 While the specification concludes with claims particularly pointing out and distinctly claiming that which is regarded as the present invention, the advantages of this invention can be more readily ascertained from the following description of the invention when read in conjunction with the accompanying drawings in which:
FIGS. 1a-1 f represent cross-sections of structures that may be formed when carrying out an embodiment of the method of the present invention.
FIG. 2 represents a cross-section of a structure that may be formed when carrying out an embodiment of the method of the present invention.
FIG. 3 represents a cross-section of a structure that may be formed when carrying out yet another embodiment of the method of the present invention.
FIG. 4 is a process flow diagram according to an embodiment of the present invention.
FIG. 5 is a cross-sectional illustration of a damascene interconnect structure, as is known in the art.
 In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It is to be understood that the various embodiments of the invention, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the spirit and scope of the invention. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the claims are entitled. In the drawings, like numerals refer to the same or similar functionality throughout the several views.
 A method for making a copper interconnect structure is described. That method comprises forming an opening in a dielectric layer disposed on a substrate, forming a barrier layer over the opening, forming a seed layer over the metal layer, and forming a copper-noble metal alloy layer by electroplating and/or electroless deposition on the seed layer, wherein the copper-noble metal alloy layer improves the electrical characteristics and reliability of the copper interconnect structure. Either an etch stop layer or a cladding layer may then be formed on the copper alloy layer.
 In an embodiment of the method of the present invention, as illustrated by FIGS. 1a-1 f, a dielectric layer 104 is formed on a substrate 102 (FIG. 1a). The substrate 102 may comprise materials such as silicon, silicon-on insulator, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Although several examples of materials from which the substrate 102 may be formed are described here, any material that may serve as a foundation upon which a microelectronic device may be built falls within the spirit and scope of the present invention.
 The dielectric layer 104 is formed on the substrate 102. Those skilled in the art will appreciate that the dielectric layer 104 may also be formed from a variety of materials, thicknesses or multiple layers of material. By way of illustration and not limitation, the dielectric layer 104 may include silicon dioxide (preferred), organic materials or inorganic materials. Although a few examples of materials that may be used to form the dielectric layer 104 are described here, that layer may be made from other materials that serve to separate and insulate the different metal layers.
 The dielectric layer 104 may be formed on the substrate 102 using a conventional deposition method, e.g., a chemical vapor deposition (“CVD”), a low pressure CVD (“LPCVD”), a physical vapor deposition (“PVD”), or an atomic layer deposition (“ALD”). Preferably, a CVD process is used. In such a process, a metal oxide precursor (e.g., a metal chloride) and steam may be fed at selected flow rates into a CVD reactor, which is then operated at a selected temperature and pressure to generate an atomically smooth interface between the substrate 102 and the dielectric layer 104. The CVD reactor should be operated long enough to form the dielectric layer 104 with the desired thickness. In most applications, the dielectric layer 104 is about one micron thick, and more preferably between about 6,000 angstroms and about 8,000 angstroms thick.
 The dielectric layer 104 may have at least one opening 105 formed in it (FIG. 1b), which comprises at least one via 106, and at least one trench 107, which may be used to connect to other metal layers in the microelectronic device (not shown), according to the conventional damascene technique as is known by those skilled in the art. As such steps are well known in to those skilled in the art, they will not be described in more detail here.
 Following the formation of the opening 105, a barrier layer 108 is deposited onto the opening 105 (FIG. 1c). Those skilled in the art will appreciate that barrier layer 108 may be formed from a variety of materials, thicknesses or multiple layers of material. By way of illustration and not limitation, the barrier layer 108 may be deposited using conventional techniques such as PVD, ALD, conventional CVD, low pressure CVD or other such methods known to those skilled in the art. In a currently preferred embodiment, the barrier layer can include any one of the following materials: tantalum, tungsten, titanium, ruthenium, molybdenum, and their alloys with nitrogen, silicon and carbon. Although a few examples of materials that may be used to form the barrier layer 108 are described here, that layer may be made from other materials that serve to prevent the diffusion of a metal across the barrier layer 108. The barrier layer 108 can range from about 10 angstroms to about 500 angstroms. A thinner barrier layer 108 is preferred (between about 10 angstroms and 50 angstoms), as a thin barrier layer makes less of a contribution to the overall resistance of the copper interconnect structure.
 A seed layer 110 may then be optionally formed on the barrier layer 108 (FIG. 1d), and may comprise copper exclusively, or its alloys with tin, indium, cadmium, aluminum, magnesium, or its alloys with noble metals such as silver, palladium, platinum, rhodium, ruthenium, gold, iridium and osmium, or the seed layer 110 may comprise noble metals exclusively. Those skilled in the art will appreciate that the seed layer 110 may be formed from a variety of materials, thicknesses or multiple layers of material. In a currently preferred embodiment, the seed layer 110 is between about 10 angstroms and 2,000 angstroms thick, and comprises a copper-noble metal alloy. The atomic percentage of noble metal in the seed layer 110 is preferably about ten percent or less, and is most preferably between about 0.1 and 4 atomic percent. The seed layer 110 may be formed on the barrier layer 108 using a conventional deposition method, e.g., a conventional CVD, low pressure CVD, PVD, ALD, or other such methods known to those skilled in the art. Although a few examples of materials that may be used to form the seed layer 110 are described here, the seed layer 110 may be made from other materials that serve to activate the surface of the diffusion barrier layer in order to prepare it for the electroless deposition or the electroplating of copper.
 In a preferred embodiment, the copper deposition process may be performed using a conventional copper electroplating process, which is well known in the art, in which a single or dual damascene structure is filled with copper by using a direct current (DC) electroplating process (see FIG. 4). First, a surface (either the barrier layer 108 or the seed layer 110) is provided for the electroplating of copper 118. Next, the surface is exposed to an electroplating solution 119. Then, a copper alloy layer 112 is formed on the surface 120. In addition, it is well known in the art that if the surface is the seed layer 110, the seed layer 110, may be consumed by the electroplating process, so that the seed layer 110 may become continuous with the copper alloy layer 112, as depicted in FIG. If. In addition, it is to be understood that the electroplating of copper may be formed directly on the barrier layer, since the seed layer is optional, and thus the seed layer may not be present in an embodiment of the invention (see FIG. 1f).
 In a currently preferred embodiment, the electroplating solution may comprise copper ions, sulfuric acid, chloride ions, additives (such as suppressors i.e. polyethylene glycol, and anti-supressors i.e. di-sulfide), noble metal ions, noble metals and complexing agents (such as thiosulfate and peroxodisulfate). Although a few examples of materials that may comprise the electroplating solution are described here, that solution may comprise other materials that serve to deposit noble metal alloys of copper onto a surface, such as the barrier layer 108 or the seed layer 110 (FIG. 1e and 1 f).
 Alternatively, the deposition of copper may be performed using an electroless deposition process, which includes any autocatalytic (i.e. no external power supply is applied) deposition of a film through the interaction of a metal salt and a chemical reducing agent. First, as is known in the art, preparing or treating a surface, such as the barrier layer 108, is necessary in order to produce an activated surface, i.e. a surface that is susceptible to the electroless deposition process. Methods for providing the activation of a surface for electroless deposition may include contact displacement, in which the surface is dipped or sprayed with a copper containing contact displacement solution, or the utilization of a seed layer, such as the seed layer 110. During the electroless deposition, the seed layer 110 (see FIG. 1c) may serve as the activated surface upon which the electroless deposition forms. The seed layer 110 acts as a region which controls the placement of the deposited metal from the electroless deposition process, because the metal from the electroless deposition solution only deposits on the seed layer 110. The inherent selectivity of the electroless deposition method results in a higher quality metallization film because it improves the uniformity and continuity of the electrolessly deposited metal layer.
 Next, after the activated surface (the seed layer 110 in the current embodiment of the present invention) for electroless deposition has been provided, the activated surface is exposed to the electroless deposition solution, by methods including immersing the activated surface in an electroless deposition solution or spraying the electroless deposition solution onto the activated surface. Finally, a metal, such as the copper alloy layer 112 of the present invention (see FIG. 1e), is electrolessly deposited on the activated surface.
 The copper alloy layer 112 may comprise the following alloys: copper silver, copper palladium, copper platinum, copper rhodium, copper ruthenium, copper gold, copper iridium and copper osmium. The percentage of noble metal in the alloy is about four percent atomic weight, most preferably between about 0.1 and 4 percent atomic weight. The incorporation of the noble metals in the copper alloy layer 112 increases copper corrosion resistance since the copper alloy layer 112 is less prone to oxidize than pure copper due to the un-reactive nature of the noble metal. The copper alloy layer 112 is also more electromigration resistant than pure copper because the low solubility of the noble metals facilitates the stuffing of the grain boundaries of the copper alloy layer 112 by the noble metals, as well as stuffing the interfaces the copper layer 112 makes with the barrier layer 108 and an etch stop layer 114 (which may be deposited in a later step, see FIG. 2). This prevents the occurrence of a major failure path (shorts, etc.) for electromigration, which would otherwise occur along the grain boundaries and interfaces. In addition, the noble metal resistance to oxidation prevents failure paths through the cracked or porous copper oxide that may form on the top surface of copper alloy layer 112, as well as at the barrier layer 108 dielectric layer 104 interface. Thus, a method of forming a copper interconnect structure 113 has been disclosed (FIGS. 1e and 1 f).
 It is to be appreciated that multiple layers of metallization may be deposited on top of the copper interconnect structure 113, according to the method of the present invention, as shown in FIGS. 2 and 3. After the copper alloy layers 112, 112′ are formed as previously described herein, etch stop layers 114, 114′ may be formed above the copper alloy layers 112, 112′ (FIG. 2). The etch stop layers 114, 114′ may comprise silicon carbide, silicon nitride, silicon carbon nitride, and other such materials as are known in the art. Those skilled in the art will appreciate that the etch stop layers 114, 114′ may be formed from a variety of materials, thicknesses or multiple layers of material. Although a few examples of materials that may be used to form the etch stop layers 114, 114′ are described here, that layer may be made from other materials that serve to stop the etching of copper alloy layer 112 during subsequent process steps, such as during subsequent lithographic, etching and cleaning processing steps. Since such processing steps are well known in the art, they will not be described in detail here. By way of illustration and not limitation, the etch stop layers 114, 114′ may be deposited using conventional techniques such as PVD, ALD, conventional CVD, low pressure CVD or other such methods known to those skilled in the art. The etch stop layer 114, 114′ can range from about 100 angstroms to about 1000 angstroms. A thinner etch stop layer 114, 114′ is preferred, as a thinner layer makes less of a contribution to the overall dielectric constant of the copper interconnect structure.
 In another embodiment, cladding layers 116, 116′ can be electrolessly deposited over the copper alloy layers 112, 112′ instead of the etch stop layers 114, 114′ (FIG. 3). The cladding layers 116, 116′ may comprise noble metals or their alloys with refractory metals, for example silver tungsten, palladium tungsten. In addition, cladding layers 116, 116′ may comprise electrolessly deposited cobalt nickel alloys with refractory metals and/or their metalloids (i.e. boron or phosphorous). The use of the cladding layers allows for the elimination of the etch stop layer altogether, since no etch stop function is needed due to the high corrosion resistance of the copper alloy layer 112, 112′ and the cladding layers 116, 116′. The elimination of the etch stop layer reduces the effective dielectric constant of the copper alloy layer, which improves the electrical performance and speed of the transistor device.
 As described above, the use of an electrolessly deposited noble metal-copper alloy metallization structure increases copper corrosion resistance and oxidation resistance, increases electromigration resistance, and decreases the effective dielectric constant of the copper interconnect structure. Thus the reliability and speed of the microelectronic device are greatly enhanced. It is understood that the present invention includes both single and dual damascene structures, as well as multilevel metallization structures.
 Although the foregoing description has specified certain steps and materials that may be used in the method of the present invention, those skilled in the art will appreciate that many modifications and substitutions may be made. Accordingly, it is intended that all such modifications, alterations, substitutions and additions be considered to fall within the spirit and scope of the invention as defined by the appended claims. In addition, it is appreciated that the fabrication of a multiple metal layer structure atop a substrate, such as a silicon substrate, to manufacture a silicon device is well known in the art. Therefore, it is appreciated that the Figures provided herein illustrate only portions of an exemplary microelectronic device that pertains to the practice of the present invention. Thus the present invention is not limited to the structures described herein.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5549808 *||12 May 1995||27 Aug 1996||International Business Machines Corporation||Method for forming capped copper electrical interconnects|
|US5616422 *||9 May 1995||1 Apr 1997||International Business Machines Corporation||Metallized substrate|
|US5969422 *||15 May 1997||19 Oct 1999||Advanced Micro Devices, Inc.||Plated copper interconnect structure|
|US5989623 *||19 Aug 1997||23 Nov 1999||Applied Materials, Inc.||Dual damascene metallization|
|US6100184 *||20 Aug 1997||8 Aug 2000||Sematech, Inc.||Method of making a dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer|
|US6136707 *||2 Oct 1999||24 Oct 2000||Cohen; Uri||Seed layers for interconnects and methods for fabricating such seed layers|
|US6174812 *||8 Jun 1999||16 Jan 2001||United Microelectronics Corp.||Copper damascene technology for ultra large scale integration circuits|
|US6326305 *||5 Dec 2000||4 Dec 2001||Advanced Micro Devices, Inc.||Ceria removal in chemical-mechanical polishing of integrated circuits|
|US6344125 *||6 Apr 2000||5 Feb 2002||International Business Machines Corporation||Pattern-sensitive electrolytic metal plating|
|US6503828 *||14 Jun 2001||7 Jan 2003||Lsi Logic Corporation||Process for selective polishing of metal-filled trenches of integrated circuit structures|
|US6525425 *||14 Jun 2000||25 Feb 2003||Advanced Micro Devices, Inc.||Copper interconnects with improved electromigration resistance and low resistivity|
|US6605874 *||19 Dec 2001||12 Aug 2003||Intel Corporation||Method of making semiconductor device using an interconnect|
|US6977224 *||28 Dec 2000||20 Dec 2005||Intel Corporation||Method of electroless introduction of interconnect structures|
|US20020050459 *||1 Nov 2001||2 May 2002||Kabushiki Kaisha Toshiba||Electronic device manufacturing method|
|US20020084529 *||28 Dec 2000||4 Jul 2002||Dubin Valery M.||Interconnect structures and a method of electroless introduction of interconnect structures|
|US20030075808 *||13 Aug 2002||24 Apr 2003||Hiroaki Inoue||Semiconductor device, method for manufacturing the same, and plating solution|
|US20030116439 *||21 Dec 2001||26 Jun 2003||International Business Machines Corporation||Method for forming encapsulated metal interconnect structures in semiconductor integrated circuit devices|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US6958540 *||23 Jun 2003||25 Oct 2005||International Business Machines Corporation||Dual damascene interconnect structures having different materials for line and via conductors|
|US7300860||30 Mar 2004||27 Nov 2007||Intel Corporation||Integrated circuit with metal layer having carbon nanotubes and methods of making same|
|US7300867||5 Jul 2005||27 Nov 2007||International Business Machines Corporation||Dual damascene interconnect structures having different materials for line and via conductors|
|US7300869 *||20 Sep 2004||27 Nov 2007||Lsi Corporation||Integrated barrier and seed layer for copper interconnect technology|
|US7495338 *||16 Mar 2006||24 Feb 2009||International Business Machines Corporation||Metal capped copper interconnect|
|US7658970||10 Jul 2008||9 Feb 2010||Mei Chang||Noble metal layer formation for copper film deposition|
|US7695981 *||15 May 2006||13 Apr 2010||Siluria Technologies, Inc.||Seed layers, cap layers, and thin films and methods of making thereof|
|US7704876||30 Aug 2007||27 Apr 2010||International Business Machines Corporation||Dual damascene interconnect structures having different materials for line and via conductors|
|US7713876 *||28 Sep 2005||11 May 2010||Tokyo Electron Limited||Method for integrating a ruthenium layer with bulk copper in copper metallization|
|US7910165||26 Mar 2004||22 Mar 2011||Applied Materials, Inc.||Ruthenium layer formation for copper film deposition|
|US7928569 *||14 Aug 2008||19 Apr 2011||International Business Machines Corporation||Redundant barrier structure for interconnect and wiring applications, design structure and method of manufacture|
|US8264046||16 Nov 2009||11 Sep 2012||Taiwan Semiconductor Manufacturing Company, Ltd.||Synergy effect of alloying materials in interconnect structures|
|US20040241321 *||26 Mar 2004||2 Dec 2004||Applied Materials, Inc.||Ruthenium layer formation for copper film deposition|
|US20040262764 *||23 Jun 2003||30 Dec 2004||International Business Machines Corporation||Dual damascene interconnect structures having different materials for line and via conductors|
|US20050006245 *||8 Jul 2003||13 Jan 2005||Applied Materials, Inc.||Multiple-step electrodeposition process for direct copper plating on barrier metals|
|US20050085031 *||15 Oct 2004||21 Apr 2005||Applied Materials, Inc.||Heterogeneous activation layers formed by ionic and electroless reactions used for IC interconnect capping layers|
|US20050245068 *||5 Jul 2005||3 Nov 2005||International Business Machines Corporation||Dual damascene interconnect structures having different materials for line and via conductors|
|US20060063375 *||20 Sep 2004||23 Mar 2006||Lsi Logic Corporation||Integrated barrier and seed layer for copper interconnect technology|
|US20060153973 *||20 Jan 2006||13 Jul 2006||Applied Materials, Inc.||Ruthenium layer formation for copper film deposition|
|US20060157857 *||16 Mar 2006||20 Jul 2006||International Business Machines Corporation||Metal capped copper interconnect|
|US20060251872 *||5 May 2005||9 Nov 2006||Wang Jenn Y||Conductive barrier layer, especially an alloy of ruthenium and tantalum and sputter deposition thereof|
|US20060254503 *||15 May 2006||16 Nov 2006||Cambrios Technologies Corporation||Seed layers, cap layers, and thin films and methods of making thereof|
|US20070059502 *||29 Aug 2006||15 Mar 2007||Applied Materials, Inc.||Integrated process for sputter deposition of a conductive barrier layer, especially an alloy of ruthenium and tantalum, underlying copper or copper alloy seed layer|
|US20070072415 *||28 Sep 2005||29 Mar 2007||Tokyo Electron Limited||Method for integrating a ruthenium layer with bulk copper in copper metallization|
|US20100164108 *||11 Mar 2010||1 Jul 2010||Johnston Steven W||Integrating a bottomless via to promote adsorption of antisuppressor on exposed copper surface and enhance electroplating superfill on noble metals|
|US20130207267 *||16 Aug 2012||15 Aug 2013||SK Hynix Inc.||Interconnection structures in a semiconductor device and methods of manufacturing the same|
|WO2006121604A2 *||25 Apr 2006||16 Nov 2006||Applied Materials Inc||Conductive barrier layer, especially an alloy of ruthenium and tantalum and sputter deposition thereof|
|WO2007081434A1 *||13 Nov 2006||19 Jul 2007||Aviza Tech Inc||Apparatus and method for the deposition of ruthenium containing films|
|WO2008027186A2 *||14 Aug 2007||6 Mar 2008||Applied Materials Inc||Integrated process for sputter deposition of a conductive barrier layer, especially an alloy of ruthenium and tantalum, underlying copper or copper alloy seed layer|
|U.S. Classification||205/291, 205/118|
|International Classification||C23C18/48, C25D7/12, C25D3/58|
|Cooperative Classification||C25D7/123, C23C18/48, C25D3/58|
|European Classification||C25D3/58, C25D7/12, C23C18/48|
|22 Jan 2003||AS||Assignment|
Owner name: INTEL CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:DUBIN, VALERY M.;REEL/FRAME:013670/0241
Effective date: 20030108