US20030162377A1 - Method for making a semiconductor device having a high-k gate dielectric - Google Patents
Method for making a semiconductor device having a high-k gate dielectric Download PDFInfo
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- US20030162377A1 US20030162377A1 US10/082,530 US8253002A US2003162377A1 US 20030162377 A1 US20030162377 A1 US 20030162377A1 US 8253002 A US8253002 A US 8253002A US 2003162377 A1 US2003162377 A1 US 2003162377A1
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- layer
- dielectric layer
- gate dielectric
- oxide
- titanium nitride
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- 238000000034 method Methods 0.000 title claims abstract description 46
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 8
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 8
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 32
- 239000012535 impurity Substances 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 13
- 238000000137 annealing Methods 0.000 claims description 8
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 5
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 5
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 5
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 5
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 5
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 5
- 238000000277 atomic layer chemical vapour deposition Methods 0.000 claims description 4
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 claims description 4
- XWCMFHPRATWWFO-UHFFFAOYSA-N [O-2].[Ta+5].[Sc+3].[O-2].[O-2].[O-2] Chemical compound [O-2].[Ta+5].[Sc+3].[O-2].[O-2].[O-2] XWCMFHPRATWWFO-UHFFFAOYSA-N 0.000 claims description 2
- VKJLWXGJGDEGSO-UHFFFAOYSA-N barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[Ti+4].[Ba+2] VKJLWXGJGDEGSO-UHFFFAOYSA-N 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims description 2
- JQJCSZOEVBFDKO-UHFFFAOYSA-N lead zinc Chemical compound [Zn].[Pb] JQJCSZOEVBFDKO-UHFFFAOYSA-N 0.000 claims description 2
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 claims description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 claims description 2
- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 claims description 2
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 2
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 claims description 2
- 239000003989 dielectric material Substances 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- -1 e.g. Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- VTGARNNDLOTBET-UHFFFAOYSA-N gallium antimonide Chemical compound [Sb]#[Ga] VTGARNNDLOTBET-UHFFFAOYSA-N 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910001510 metal chloride Inorganic materials 0.000 description 1
- 239000012702 metal oxide precursor Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- OCGWQDWYSQAFTO-UHFFFAOYSA-N tellanylidenelead Chemical compound [Pb]=[Te] OCGWQDWYSQAFTO-UHFFFAOYSA-N 0.000 description 1
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
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Definitions
- the present invention relates to methods for making semiconductor devices, in particular, semiconductor devices that include high-k gate dielectric layers.
- MOS field-effect transistors with very thin gate dielectrics made from silicon dioxide may experience unacceptable gate leakage currents. Forming the gate dielectric from certain high-k dielectric materials, in place of silicon dioxide, can reduce gate leakage. Such a dielectric may not, however, be compatible with polysilicon—the preferred material for making the device's gate electrode. Placing a thin layer of titanium nitride, which is compatible with many high-k gate dielectrics, between a high-k gate dielectric and a polysilicon-based gate electrode may enable such a dielectric to be used with such a gate electrode. Unfortunately, the presence of such a layer may increase the transistor's threshold voltage, which is undesirable.
- FIGS. 1 a - 1 d represent cross-sections of structures that may be formed when carrying out an embodiment of the method of the present invention.
- a method for making a semiconductor device comprises forming on a substrate a dielectric layer that has a dielectric constant that is greater than the dielectric constant of silicon dioxide. That dielectric layer is modified so that it will be compatible with a gate electrode to be formed on it. A gate electrode is then formed on the dielectric layer.
- dielectric layer 101 is formed on substrate 100 .
- Substrate 100 may include isolation regions, p-type wells and n-type wells that have been formed in a bulk silicon or silicon-on-insulator substructure.
- Substrate 100 may comprise other materials—which may or may not be combined with silicon—such as: germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.
- germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide such as: germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.
- Dielectric layer 101 comprises a material that has a dielectric constant that is greater than the dielectric constant of silicon dioxide.
- Dielectric layer 101 preferably has a dielectric constant that is at least about twice that of silicon dioxide, i.e., a dielectric constant that is greater than about 8.
- dielectric layer 101 When serving as the gate dielectric for the semiconductor device, dielectric layer 101 is a “high-k gate dielectric.”
- Some of the materials that may be used to make high-k gate dielectrics include: hafnium oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. Particularly preferred are hafnium oxide, zirconium oxide, titanium oxide, and aluminum oxide.
- that layer may be made from other materials that serve to reduce gate leakage from the level present in devices that include silicon dioxide gate dielectrics.
- Dielectric layer 101 may be formed on substrate 100 using a conventional deposition method, e.g., a conventional chemical vapor deposition (“CVD”), low pressure CVD, or physical vapor deposition (“PVD”) process.
- a conventional atomic layer CVD process is used.
- a metal oxide precursor e.g., a metal chloride
- steam may be fed at selected flow rates into a CVD reactor, which is then operated at a selected temperature and pressure to generate an atomically smooth interface between substrate 100 and dielectric layer 101 .
- the CVD reactor should be operated long enough to form a layer with the desired thickness. In most applications, dielectric layer 101 should be less than about 100 angstroms thick, and more preferably between about 20 angstroms and about 60 angstroms thick.
- dielectric layer 101 will include undesirable impurities, e.g., hydrogen and/or unreacted metal (represented by dots in FIG. 1 a ), which render that layer incompatible with polysilicon.
- dielectric layer 101 is modified so that it will be compatible with a gate electrode to be formed on it.
- FIGS. 1 a - 1 c illustrate steps that may be applied to modify dielectric layer 101 .
- sacrificial layer 102 is formed on dielectric layer 101 to generate the structure represented by FIG. 1 a .
- Sacrificial layer 102 preferably is made from a material that may getter impurities from dielectric layer 101 .
- An example of a suitable material is titanium nitride.
- Such a titanium nitride layer may be formed on dielectric layer 101 using a conventional CVD or PVD process. In a preferred embodiment, such a process is used to form a titanium nitride layer that is between about 10 angstroms and about 50 angstroms thick.
- sacrificial layer 102 is formed on dielectric layer 101 , undesirable impurities are transported from dielectric layer 101 to sacrificial layer 102 .
- impurities may be transported from high-k gate dielectric layer 101 to titanium nitride layer 102 by annealing titanium nitride layer 102 .
- Titanium nitride layer 102 may be annealed using a rapid thermal anneal process or by heating that layer in a furnace at between about 500° C. and about 1,000° C. for between about 5 minutes and about 20 minutes.
- FIG. 1 b represents a structure in which undesirable impurities, e.g., hydrogen and unreacted metal (represented by dots in FIG. 1 b ), have been transferred from high-k dielectric layer 101 into titanium nitride layer 102 .
- FIG. 1 b is not meant to suggest that annealing titanium nitride layer 102 will cause all undesirable impurities, initially present in high-k dielectric layer 101 , to be moved into layer 102 . Rather, the annealing step is performed to cause a sufficient number of those impurities to move from high-k dielectric layer 101 into titanium nitride layer 102 to modify high-k dielectric layer 101 such that it will be compatible with a gate electrode to be formed on that layer.
- a method that applies an annealing step which does not remove all—or even substantially all—of the undesirable impurities from high-k dielectric layer 101 , may still fall within the spirit and scope of the present invention.
- sacrificial layer 102 is removed.
- sacrificial layer 102 is made from titanium nitride and dielectric layer 101 comprises a high-k gate dielectric layer
- titanium nitride layer 102 may be removed from high-k gate dielectric layer 101 using a conventional wet etch process, which uses a chemistry that is selective for titanium nitride over the material used to form the high-k gate dielectric layer.
- a gate electrode may be formed on dielectric layer 101 .
- the gate electrode may be formed by initially depositing polysilicon layer 103 on high-k gate dielectric layer 101 —generating the FIG. 1 c structure.
- Polysilicon layer 103 may be deposited using conventional methods and preferably is between about 2,000 angstroms and about 4,000 angstroms thick.
- additional steps that are generally used to complete the gate electrode e.g., forming a silicide (not shown) on the upper part of etched polysilicon structure 104 ) may be applied. As such steps are well known to those skilled in the art, they will not be described in more detail here.
- a sacrificial titanium nitride layer may enable a high-k gate dielectric to be used with a polysilicon-based gate electrode.
- a titanium nitride layer may be formed on a high-k gate dielectric layer, annealing and then removing that layer to remove undesirable impurities from the high-k gate dielectric, the embodiment described above enables the resulting device to benefit from the temporary presence of the titanium nitride layer without experiencing the work function shifts that permanent placement of that layer between the high-k gate dielectric and the gate electrode may cause.
- the present invention is not limited to this particular embodiment, but instead contemplates other processes for modifying dielectric layers to ensure compatibility with gate electrodes.
Abstract
Description
- The present invention relates to methods for making semiconductor devices, in particular, semiconductor devices that include high-k gate dielectric layers.
- MOS field-effect transistors with very thin gate dielectrics made from silicon dioxide may experience unacceptable gate leakage currents. Forming the gate dielectric from certain high-k dielectric materials, in place of silicon dioxide, can reduce gate leakage. Such a dielectric may not, however, be compatible with polysilicon—the preferred material for making the device's gate electrode. Placing a thin layer of titanium nitride, which is compatible with many high-k gate dielectrics, between a high-k gate dielectric and a polysilicon-based gate electrode may enable such a dielectric to be used with such a gate electrode. Unfortunately, the presence of such a layer may increase the transistor's threshold voltage, which is undesirable.
- Accordingly, there is a need for an improved process for making a semiconductor device that includes a high-k gate dielectric. There is a need for such a process in which a polysilicon-based gate electrode is formed on such a gate dielectric to create a functional device—without causing undesirable work function shifts. The method of the present invention provides such a process.
- FIGS. 1a-1 d represent cross-sections of structures that may be formed when carrying out an embodiment of the method of the present invention.
- A method for making a semiconductor device is described. That method comprises forming on a substrate a dielectric layer that has a dielectric constant that is greater than the dielectric constant of silicon dioxide. That dielectric layer is modified so that it will be compatible with a gate electrode to be formed on it. A gate electrode is then formed on the dielectric layer. In the following description, a number of details are set forth to provide a thorough understanding of the present invention. It will be apparent to those skilled in the art, however, that the invention may be practiced in many ways other than those expressly described here. The invention is thus not limited by the specific details disclosed below.
- In an embodiment of the method of the present invention, as illustrated by FIGS. 1a-1 d,
dielectric layer 101 is formed onsubstrate 100.Substrate 100 may include isolation regions, p-type wells and n-type wells that have been formed in a bulk silicon or silicon-on-insulator substructure.Substrate 100 may comprise other materials—which may or may not be combined with silicon—such as: germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Although several examples of materials from whichsubstrate 100 may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the present invention. -
Dielectric layer 101 comprises a material that has a dielectric constant that is greater than the dielectric constant of silicon dioxide.Dielectric layer 101 preferably has a dielectric constant that is at least about twice that of silicon dioxide, i.e., a dielectric constant that is greater than about 8. When serving as the gate dielectric for the semiconductor device,dielectric layer 101 is a “high-k gate dielectric.” Some of the materials that may be used to make high-k gate dielectrics include: hafnium oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. Particularly preferred are hafnium oxide, zirconium oxide, titanium oxide, and aluminum oxide. Although a few examples of materials that may be used to formdielectric layer 101 are described here, that layer may be made from other materials that serve to reduce gate leakage from the level present in devices that include silicon dioxide gate dielectrics. -
Dielectric layer 101 may be formed onsubstrate 100 using a conventional deposition method, e.g., a conventional chemical vapor deposition (“CVD”), low pressure CVD, or physical vapor deposition (“PVD”) process. Preferably, a conventional atomic layer CVD process is used. In such a process, a metal oxide precursor (e.g., a metal chloride) and steam may be fed at selected flow rates into a CVD reactor, which is then operated at a selected temperature and pressure to generate an atomically smooth interface betweensubstrate 100 anddielectric layer 101. The CVD reactor should be operated long enough to form a layer with the desired thickness. In most applications,dielectric layer 101 should be less than about 100 angstroms thick, and more preferably between about 20 angstroms and about 60 angstroms thick. - As deposited,
dielectric layer 101 will include undesirable impurities, e.g., hydrogen and/or unreacted metal (represented by dots in FIG. 1a), which render that layer incompatible with polysilicon. In the method of the present invention,dielectric layer 101 is modified so that it will be compatible with a gate electrode to be formed on it. FIGS. 1a-1 c illustrate steps that may be applied to modifydielectric layer 101. First,sacrificial layer 102 is formed ondielectric layer 101 to generate the structure represented by FIG. 1a.Sacrificial layer 102 preferably is made from a material that may getter impurities fromdielectric layer 101. An example of a suitable material is titanium nitride. Such a titanium nitride layer may be formed ondielectric layer 101 using a conventional CVD or PVD process. In a preferred embodiment, such a process is used to form a titanium nitride layer that is between about 10 angstroms and about 50 angstroms thick. - After
sacrificial layer 102 is formed ondielectric layer 101, undesirable impurities are transported fromdielectric layer 101 tosacrificial layer 102. Whensacrificial layer 102 is made from titanium nitride anddielectric layer 101 comprises a high-k gate dielectric layer, impurities may be transported from high-k gatedielectric layer 101 totitanium nitride layer 102 by annealingtitanium nitride layer 102.Titanium nitride layer 102 may be annealed using a rapid thermal anneal process or by heating that layer in a furnace at between about 500° C. and about 1,000° C. for between about 5 minutes and about 20 minutes. - FIG. 1b represents a structure in which undesirable impurities, e.g., hydrogen and unreacted metal (represented by dots in FIG. 1b), have been transferred from high-k
dielectric layer 101 intotitanium nitride layer 102. FIG. 1b is not meant to suggest that annealingtitanium nitride layer 102 will cause all undesirable impurities, initially present in high-kdielectric layer 101, to be moved intolayer 102. Rather, the annealing step is performed to cause a sufficient number of those impurities to move from high-kdielectric layer 101 intotitanium nitride layer 102 to modify high-kdielectric layer 101 such that it will be compatible with a gate electrode to be formed on that layer. Thus, a method that applies an annealing step, which does not remove all—or even substantially all—of the undesirable impurities from high-kdielectric layer 101, may still fall within the spirit and scope of the present invention. - After the undesirable impurities have been transported from
dielectric layer 101 tosacrificial layer 102, e.g., by annealing the sacrificial layer,sacrificial layer 102 is removed. Whensacrificial layer 102 is made from titanium nitride anddielectric layer 101 comprises a high-k gate dielectric layer,titanium nitride layer 102 may be removed from high-k gatedielectric layer 101 using a conventional wet etch process, which uses a chemistry that is selective for titanium nitride over the material used to form the high-k gate dielectric layer. - Following the removal of
sacrificial layer 102, a gate electrode may be formed ondielectric layer 101. In a preferred embodiment, the gate electrode may be formed by initially depositingpolysilicon layer 103 on high-k gatedielectric layer 101—generating the FIG. 1c structure.Polysilicon layer 103 may be deposited using conventional methods and preferably is between about 2,000 angstroms and about 4,000 angstroms thick. After etching bothlayers - As described above, a sacrificial titanium nitride layer may enable a high-k gate dielectric to be used with a polysilicon-based gate electrode. By forming a titanium nitride layer on a high-k gate dielectric layer, annealing and then removing that layer to remove undesirable impurities from the high-k gate dielectric, the embodiment described above enables the resulting device to benefit from the temporary presence of the titanium nitride layer without experiencing the work function shifts that permanent placement of that layer between the high-k gate dielectric and the gate electrode may cause. Although the embodiment described above is an example of a process for modifying a dielectric layer to enable it to be compatible with a gate electrode, the present invention is not limited to this particular embodiment, but instead contemplates other processes for modifying dielectric layers to ensure compatibility with gate electrodes.
- Although the foregoing description has specified certain steps and materials that may be used in the method of the present invention, those skilled in the art will appreciate that many modifications and substitutions may be made. Accordingly, it is intended that all such modifications, alterations, substitutions and additions be considered to fall within the spirit and scope of the invention as defined by the appended claims.
Claims (20)
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US10/943,661 US7166505B2 (en) | 2002-02-22 | 2004-09-16 | Method for making a semiconductor device having a high-k gate dielectric |
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- 2003-07-11 US US10/618,226 patent/US20040106287A1/en not_active Abandoned
-
2004
- 2004-09-16 US US10/943,661 patent/US7166505B2/en not_active Expired - Fee Related
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030178674A1 (en) * | 2002-03-22 | 2003-09-25 | Shigeru Fujita | Semiconductor device and its manufacturing method |
US8581352B2 (en) | 2006-08-25 | 2013-11-12 | Micron Technology, Inc. | Electronic devices including barium strontium titanium oxide films |
US9202686B2 (en) | 2006-08-25 | 2015-12-01 | Micron Technology, Inc. | Electronic devices including barium strontium titanium oxide films |
Also Published As
Publication number | Publication date |
---|---|
US7166505B2 (en) | 2007-01-23 |
US20040106287A1 (en) | 2004-06-03 |
US20050032318A1 (en) | 2005-02-10 |
US6617209B1 (en) | 2003-09-09 |
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