US 20030137359 A1 Abstract A fractional-N frequency synthesizer is disclosed wherein the multi-modulus frequency divider in the feedback path of the phase locked loop is controlled by a delta-sigma modulator to achieve the desired division ratio. The fractional input control signal to the delta sigma modulator is dithered to break any periodicity in the modulator output signal to avoid the generation of fractional spurious frequencies.
Claims(20) 1. A delta-sigma fractional-N frequency synthesizer comprising:
a phase locked loop including a phase frequency detector, a loop filter, a voltage-controlled oscillator and a multi-modulus frequency divider in a feedback loop between the voltage-controlled oscillator output and an input of the phase frequency detector; a delta-sigma modulator having an input for receiving a fractional control word and an output coupled to the multi-modulus frequency divider for controlling the division ratio of the multi-modulus frequency divider in response to the input fractional control word; a generator for producing a signal in accordance with and related to a frequency compensation loop error signal from the multi-modulus frequency divider; and means for adding said generator signal output to a fractional input control word to produce a zero average dither fractional control word as the input to the delta-sigma modulator to generate a multi-modulus input control signal whereby the division ratio is changed without generation of fractional spurious frequencies. 2. The delta-sigma fractional-N frequency synthesizer as defined in 3. The delta-sigma fractional-N frequency synthesizer as defined in _{comp}/Z to F_{comp}/Y, where Z is an integer value of at least 2 and the maximum value of Y is related to the loop filter and the frequency compensation loop error signal. 4. The delta-sigma fractional-N frequency synthesizer as defined in 5. The delta-sigma fractional-N frequency synthesizer as defined in 6. The delta-sigma fractional-N frequency synthesizer as defined in 7. The delta-sigma fractional-N frequency synthesizer as defined in 8. The delta-sigma fractional-N frequency synthesizer as defined in _{comp}/Z is equal to 4. 9. The delta-sigma fractional-N frequency synthesizer as defined in _{comp}/Z is equal to 8. 10. The delta-sigma fractional-N frequency synthesizer as defined in _{comp}/Z is equal to 16. 11. The delta-sigma fractional-N frequency synthesizer as defined in _{comp}/Z has an arbitrary integer value equal to or greater than 1. 12. The delta-sigma fractional-N frequency synthesizer as defined in 13. The delta-sigma fractional-N frequency synthesizer as defined in 14. The delta-sigma fractional-N frequency synthesizer as defined in said fractional input control word further comprises a separate F _{input }control signal and an M_{input }control signal; means for combining said F _{input }control signal and said generator signal output to produce a delta-sigma modulator input control word, said delta-sigma modulator generating an output control word in response to said input control word; and means for combining said M _{input }control signal and said delta-sigma modulator output control word to generate said multi-modulus frequency divider division ratio control. 15. The delta-sigma fractional-N frequency synthesizer as defined in 16. The delta-sigma fractional-N frequency synthesizer as defined in said fractional input control word further comprises a separate F _{input }control signal and an A_{input }control signal and an N_{input }control signal; means for combining said F _{input }control signal and said generator signal output to produce a delta-sigma modulator input control word, said delta-sigma modulator generating an output control word in response to said input control word; means for combining said A _{input }control signal and said delta-sigma modulator output control word to generate a multi-modulus “A” control input signal; and means for combining said N _{input }control signal and the result of the combined A_{input }control signal and delta-sigma modulator output control word to generate a multi-modulus “N” control input signal. 17. A method for providing a desired synthesized fractional frequency without generating fractional spurious frequencies comprising the steps of:
providing a fractional-N frequency synthesizer comprising a phase locked loop including a phase frequency detector, a loop filter, a voltage-controlled oscillator and a multi-modulus frequency divider in a feedback loop between the voltage-controlled oscillator output and an input of the phase frequency detector; providing a delta-sigma modulator having an input for receiving a fractional control word and an output coupled to the multi-modulus frequency divider for controlling the division ratio of the multi-modulus frequency divider in response to the input fractional control word; producing a signal in accordance with and related to a frequency compensation loop error signal from the multi-modulus frequency divider; and adding said signal to a fractional input control word to produce a zero average dither fractional control word as the input to the delta-sigma modulator to generate a multi-modulus input control signal whereby the division ratio is changed without generation of fractional spurious frequencies. 18. The method as defined in 19. The method as defined in 20. A method of producing a synthesized fractional frequency without fractional spurious frequency generation comprising the steps of:
providing a reference frequency; providing a phase locked loop voltage controlled oscillator; generating a desired output frequency by controlling the division ratio of a multi-modulus frequency divider in a feedback path in the phase locked loop; dithering the fractional input control signal to a delta sigma modulator using a sine wave generator; and controlling the multi-modulus division ratio with the output signal produced by the delta-sigma modulator. Description [0001] The present invention relates generally to delta-sigma modulator based fractional-N phase locked loop frequency synthesizers and deals more particularly with a delta-sigma modulator based fractional-N phase locked loop frequency synthesizer with a sine wave generator to break the periodicity of the delta-sigma modulator output to eliminate the generation of fractional spurious frequencies. [0002] Digital frequency synthesizers have long been used in communication systems, particularly RF communication systems, to generate RF signals carried over RF channels. In frequency synthesis, it is desirable to achieve the selected frequency output in as little time as possible with any spurious outputs minimized. It is known to create a frequency synthesizer by placing a frequency divider function between the voltage-controlled oscillator (VCO) output and the phase frequency detector (PFD) in a phase-locked loop (PLL), wherein the output is an integer-N multiple of the input reference frequency to the PFD. The spurious outputs in question are usually associated with phase detectors and occur at the phase detector operating frequency, which is generally the same as the channel spacing. Incorporating a fractional-N division function in the PLL helps overcome problems of spurious frequency outputs in an integer PLL by allowing the phase detector to operate at a much higher frequency for the same channel spacing. [0003] A number of methods that are based upon the concept of integer-N frequency synthesis are known to realize the fractional-N division function and include pulse swallowing, phase interpolation, Wheatly random jittering and delta-sigma modulation to control the multi-modulus, including dual-modulus, frequency dividers to provide the division function. Of the known methods, a delta-sigma modulator realization of a fractional-N frequency synthesizer is desirable and preferable to achieve low phase noise, fast settling time, fine channel resolution and wide tuning bandwidth. The delta-sigma modulator fractional-N phase locked loop frequency synthesizer is based on the concept of division ratio averaging, wherein an integer frequency divider rather than a fractional frequency divider is used, and the division ratio is dynamically switched between two or more values, effectively providing a non-integer number division function. One of the more important advantages of using the delta-sigma modulator to control a multi-modulus is the ability to shape phase noise introduced by the delta-sigma modulator controlled fractional-N division function. A problem generally associated with such a delta-sigma modulator fractional-N frequency synthesizer is the appearance or presence of fractional spurious levels at a fractional offset frequency. The fractional spurious levels may also appear at the fractional offset frequency harmonics. The fractional spurious levels in delta-sigma modulator based fractional-N frequency synthesizers may originate from several sources including the operation of the delta-sigma modulator itself, coupling between the multi-modulus prescaler or charge pump driving the loop filter and the outside world through power supply feeds or substrates, and the nonlinearity of the charge pump. The fractional spurious frequencies may also originate from the spacing error or timing error of the multi-modulus prescaler. [0004] It is a general object therefore of the present invention to provide a method and related apparatus to prevent the generation of spurious frequency errors in a delta-sigma based fractional-N frequency synthesizer. [0005] It is another object of the present invention to break the periodicity of the multi-modulus control output signal of the delta-sigma modulator to eliminate fractional spurious frequencies in the fractional-N frequency synthesizer originating from the operation of the delta-sigma modulator. [0006] It is a further object of the present invention to provide a delta-sigma based fractional-N phase locked loop frequency synthesizer with a sine wave generator to break the periodicity of the output signal of the delta-sigma modulator to eliminate the production of fractional spurious frequencies. [0007] Other objects and features of the present invention will become readily apparent from the following written detailed description taken together with the drawings forming a part thereof. [0008] The invention resides in a fractional-N frequency synthesizer having a delta-sigma modulator control of the division ratio of a multi-modulus frequency divider in the feedback path of the phase locked loop. The output control signal of the delta-sigma modulator is dithered to break the periodicity of the division ratio control signal which occurs when the fractional control input words to the delta-sigma modulation has too few “zeros” or “ones” which cause the generation of fractional spurious frequencies. The invention avoids the generation of the fractional spurious frequencies. [0009] In a one aspect of the invention, a delta-sigma fractional-N frequency synthesizer comprises a phase locked loop including a phase frequency detector, a loop filter, a voltage-controlled oscillator and a multi-modulus frequency divider in a feedback loop between the voltage-controlled oscillator output and an input of the phase frequency detector. The delta-sigma modulator has an input for receiving a fractional control word and an output coupled to the multi-modulus frequency divider for controlling the division ratio of the multi-modulus frequency divider in response to the input fractional control word. A generator produces a signal in accordance with and related to a frequency compensation loop error signal from the multi-modulus frequency divider. Means are provided for adding the generator signal output to the fractional input control word to produce a zero average dither fractional control word as the input to the delta-sigma modulator. The delta sigma modulator generates a multi-modulus input control signal whereby the division ratio is changed without generation of fractional spurious frequencies. [0010] Preferably, the order of the delta-sigma modulator has an integer value in the range of Z to X, where Z is an integer value of at least 2 and X has an arbitrary integer value greater than Z. [0011] Preferably, the generator output signal frequency has a value in the range of F [0012] Preferably, the generator signal output is an asymmetrical signal. [0013] Preferably, the generator signal output is a symmetrical signal. [0014] Preferably, the generator is a symmetrical sine wave generator. [0015] Preferably, the generator is an asymmetrical sine wave generator. [0016] Preferably, F [0017] Preferably, F [0018] Preferably, F [0019] Preferably, F [0020] Preferably, the multi-modulus frequency divider is a dual-modulus frequency divider. [0021] In a further aspect of the invention, the dual-modulus frequency divider includes a prescaler coupled to the output of the voltage-controlled oscillator and includes an N-divider and A-divider coupled to the output of the prescaler. The prescaler has a division ratio control input coupled to the A-divider to switch the division ratio in response to the A-divider completing a predetermined count. [0022] In another aspect of the invention, the fractional input control word further comprises a separate F [0023] Preferably, the multi-modulus frequency divider further comprises a dual multi-modulus frequency divider. [0024] In a further aspect of the invention, the fractional input control word further comprises a separate F [0033] Turning now to the drawings and first considering FIG. 1, a schematic functional block diagram of a representative delta-sigma modulator based fractional-N phase locked loop frequency synthesizer is illustrated therein and generally designated [0034] The frequency F [0035] Turning now to FIG. 2, a schematic functional block diagram of a first embodiment of a delta-sigma modulator fractional-N phase locked loop frequency synthesizer of the invention is illustrated therein and generally designated [0036] The output [0037] The output [0038] Turning now to FIG. 3, a delta-sigma fractional-N phase locked loop frequency synthesizer embodying the invention is illustrated therein and designated generally [0039] The output [0040] The sine wave generator [0041] Turning now to FIG. 4, a delta-sigma fractional-N phase locked loop frequency synthesizer embodying the invention is illustrated therein and designated generally [0042] The output [0043] The DMD [0044] Turning now to FIG. 5, a delta-sigma fractional-N phase locked loop frequency synthesizer embodying the invention is illustrated therein and designated generally [0045] A reference frequency F [0046] The output [0047] An A [0048] As in FIG. 4, the DMD [0049] The sine wave signal used to “dither” the input to the delta-sigma modulator may be generated using any of a number of different techniques and methods now known or future developed, some of which methods are illustrated, for example, in FIGS. 6, 7 and [0050] In FIG. 7, the sine wave generator comprises a counter [0051] In FIG. 8, the sine wave generator comprises a counter [0025]FIG. 1 is a schematic functional block diagram of a delta-sigma modulator based fractional-N synthesizer. [0026]FIG. 2 is a schematic functional block diagram of a first embodiment of a delta-sigma fractional-N synthesizer of the present invention. [0027]FIG. 3 is a schematic functional block diagram of an alternate embodiment of the delta-sigma fractional-N synthesizer of the present invention. [0028]FIG. 4 is a schematic functional block diagram of a further alternate embodiment of the delta-sigma fractional-N synthesizer of the present invention. [0029]FIG. 5 is a schematic functional block diagram of a further alternate embodiment of the delta-sigma fractional-N synthesizer of the present invention. [0030]FIG. 6 is a functional block diagram of a sine wave signal generator using logic. [0031]FIG. 7 is a functional block diagram of a sine wave signal generator using ROM. [0032]FIG. 8 is a functional block diagram of a sine wave signal generator using RAM. Referenced by
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