US20030119254A1 - Reducing secondary injection effects - Google Patents

Reducing secondary injection effects Download PDF

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US20030119254A1
US20030119254A1 US10/023,278 US2327801A US2003119254A1 US 20030119254 A1 US20030119254 A1 US 20030119254A1 US 2327801 A US2327801 A US 2327801A US 2003119254 A1 US2003119254 A1 US 2003119254A1
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substrate
electron acceptor
channel
acceptor dopant
dopant
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US6583007B1 (en
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Boaz Eitan
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Spansion Israel Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7923—Programmable transistors with more than two possible different levels of programmation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data

Definitions

  • the present invention relates to electrically erasable, programmable read only memory (EEPROM) and nitride, programmable read only memory (NROM) cells in general, and particularly to reducing effects of secondary injection in NROM cells.
  • EEPROM electrically erasable, programmable read only memory
  • NROM nitride, programmable read only memory
  • FIG. 1 illustrates a typical prior art floating gate memory cell.
  • the floating gate memory cell comprises source and drain portions S and D embedded in a substrate 5 , between which is a channel 7 .
  • a floating gate 8 is located above but insulated from channel 7
  • a gate 9 is located above but insulated from floating gate 8 .
  • the standard electron injection mechanism for programming is channel hot electron injection, in which the source to drain potential drop creates a lateral field that accelerates channel electron e 1 from source S to drain D, as indicated by arrow 6 .
  • the high energy electrons e 1 may be injected (arrow 4 ) into floating gate 8 , provided that the gate voltage creates a sufficiently great vertical field.
  • drain D Due to the positive potential of drain D, generated electrons e 2 may be collected (arrow 11 ) by drain D. However, as indicated by arrow 13 , holes h 2 may accelerate towards the low substrate potential of substrate 5 . On the way, another impact ionization may occur, creating another electron-hole pair e 3 -h 3 with probability M 2 . Holes h 3 are pulled (arrow 15 ) further into substrate 5 and are no concern. However, electrons e 3 , called secondary electrons, may be accelerated (arrow 17 ) towards positive gate 9 where, if they have gained sufficient energy, are injected into floating gate 8 , this event having a probability of T.
  • the current for secondary injection is defined as:
  • I ds is the channel current from source to drain.
  • NROM nitride read only memory
  • the present invention seeks to provide methods and apparatus for reducing effects of secondary injection in non-volatile memory (NVM) devices that have a non-conducting charge trapping layer, such as NROM devices.
  • NVM non-volatile memory
  • the reduction of the secondary injection improves endurance and reliability.
  • the present invention also provides methods and apparatus for preventing punch-through voltages from detrimentally affecting erase operations in the NVM device that has a non-conducting charge trapping layer.
  • the probability T of secondary injection may be reduced by reducing the surface concentration of an electron acceptor dopant, such as, but not limited to, boron.
  • Punch-through voltages in erase operations may be controlled by one or several methods. For example, using relatively high negative gate voltages (e.g., in the range of ⁇ 5 to ⁇ 7V) and relatively low bit line (e.g., drain) voltages to erase the memory cell may reduce and suppress surface punch-through.
  • undesirable punch-through currents may be reduced in the substrate by electron acceptor doping far from the gate-substrate interface (i.e., the substrate surface). The electron acceptor doping far from the gate-substrate interface reduces the probability T of secondary injection.
  • the negative gate voltage in erase helps suppress the surface punch-through problem in erase, due to the reduced surface concentration of the electron acceptor dopant.
  • the surface concentration of the electron acceptor dopant may be reduced and the concentration increased far from the surface by one or several methods.
  • the substrate may be constructed with a double or triple-well process.
  • Doping of the electron acceptor dopant may be constrained to be deep in the NROM cell well or at a medium depth. This may be accomplished, for example, by a deep pocket implant of the dopant.
  • the surface concentration of the electron acceptor dopant may be reduced by doping the surface with an electron donor dopant, such as, but not limited to, phosphor or arsenic.
  • the presence of the electron acceptor dopant deep in the substrate may not reduce the probability M 2 of creating electron-hole pairs e 3 -h 3 , nevertheless the distance of the dopant from the surface and far from the n+ junction may reduce the probability T of secondary injection, and reduce punch-through.
  • NVM non-volatile memory
  • the method including forming two diffusion areas in a substrate, said diffusion areas forming a channel therebetween, the channel being adapted to permit movement of primary electrons to at least one of the diffusion areas, forming a non-conducting charge trapping layer at least over the channel, and managing at least one of movement of secondary electrons from the substrate towards the charge trapping layer and a punch-through voltage in the substrate by controlling a position of a concentration of an electron acceptor dopant in the substrate.
  • NVM non-volatile memory
  • the managing includes concentrating less of the electron acceptor dopant generally near an upper surface of the substrate, the upper surface including an interface between the substrate and the charge trapping layer, and more of the electron acceptor dopant further from the upper surface of the substrate.
  • the managing includes concentrating most of the electron acceptor dopant generally between a position halfway from the upper surface and a lower surface of the substrate.
  • the method includes constructing the substrate with at least one of a double-well and triple-well process.
  • less of the electron acceptor dopant may be concentrated generally near the upper surface of the substrate by concentrating more of an electron donor dopant near the upper surface of the substrate.
  • the electron acceptor dopant may comprise boron.
  • the electron donor dopant may comprise at least one of phosphor and arsenic.
  • the non-conducting charge trapping layer may include an oxide-nitride-oxide (ONO) layer.
  • ONO oxide-nitride-oxide
  • NVM non-volatile memory
  • a non-volatile memory (NVM) device including a channel formed in a substrate, two diffusion areas, one on either side of the channel in the substrate, each diffusion area having a junction with the channel, the channel being adapted to permit movement of electrons to at least one of the diffusion areas, a non-conducting charge trapping layer formed at least over the channel, and an electron acceptor dopant concentrated less near an upper surface of the substrate, the upper surface including an interface between the substrate and the charge trapping layer, and concentrated more further from the upper surface of the substrate.
  • NVM non-volatile memory
  • the electron acceptor dopant is concentrated at at least 1 ⁇ 10 17 cm ⁇ 2 at a depth of 0.1 ⁇ m from the upper surface of the substrate.
  • the electron acceptor dopant is concentrated at at least 1 ⁇ 10 17 cm ⁇ 2 at a depth of between 0.1-0.8 ⁇ m and deeper from the upper surface of the substrate.
  • the electron acceptor dopant is concentrated less than 1 ⁇ 10 17 cm ⁇ 2 at a depth of less than 0.1 ⁇ m.
  • FIG. 1 is a simplified illustration of secondary injection in a prior art floating gate memory cell
  • FIG. 2 is a simplified illustration of a non-volatile memory (NVM) device having a surface concentration adapted for reduced secondary injection, constructed and operative in accordance with an embodiment of the invention
  • FIG. 3 is a simplified graphical illustration of a concentration of an electron acceptor dopant in terms of depth in the substrate of the NVM device of FIG. 2, in accordance with an embodiment of the invention
  • FIG. 4 is a simplified graphical illustration of an effect of reducing an electron acceptor dopant generally near the upper surface of the substrate of the NVM device of FIG. 2, as opposed to the presence of pocket or planar implants, on secondary injection of electrons, in accordance with an embodiment of the invention.
  • FIGS. 5 and 6 are simplified graphical illustrations of the effect of a concentration of the electron acceptor dopant deep in the substrate, such as deep in a double or triple well, respectively on programming and erasing, in accordance with an embodiment of the invention.
  • FIG. 2 illustrates a non-volatile memory (NVM) device 10 , constructed and operative in accordance with an embodiment of the invention.
  • the NVM device 10 has a non-conducting charge trapping layer, such as a nitride read only memory (NROM) device, as is now explained.
  • NROM nitride read only memory
  • NVM device 10 preferably includes a channel 12 formed in a substrate 14 .
  • Two diffusion areas 16 and 18 are preferably formed on either side of channel 12 in substrate 14 , each diffusion area having a junction with channel 12 .
  • a non-conducting charge trapping layer such as, but not limited to, an oxide-nitride-oxide (ONO) layer 20 (i.e., a sandwich of an oxide sub-layer 20 A, a nitride sub-layer 20 B and an oxide sub-layer 20 C) is preferably formed at least over channel 12
  • a polysilicon gate 22 is preferably formed at least over ONO layer 20 .
  • NROM device 10 may comprise two separated and separately chargeable areas 23 A and 23 B in the nitride sub-layer 20 B, each chargeable area defining and storing one bit.
  • movement of secondary electrons from substrate 14 towards ONO layer 20 may be managed and may be reduced by controlling a concentration of an electron acceptor dopant in substrate 14 .
  • concentration of an electron acceptor dopant in substrate 14 may significantly reduce secondary electron injection in the direction towards ONO layer 20 and polysilicon gate 22 .
  • the electron acceptor dopant may comprise, without limitation, boron.
  • the surface concentration of the electron acceptor dopant may be reduced and the concentration increased far from the upper surface of substrate 14 by one or several methods.
  • substrate 14 may be constructed with a double or triple implant process.
  • the electron acceptor dopant may be concentrated as a function of depth in the substrate of the NVM device 10 , as is further described hereinbelow with reference to FIG. 3.
  • the electron acceptor dopant may be doped by means of a deep or medium-depth pocket implant 24 , as indicated generally in FIG. 2.
  • the surface concentration of the electron acceptor dopant may be reduced by doping the surface with an electron donor dopant 25 (indicated generally in FIG. 2), such as, but not limited to, phosphor or arsenic.
  • the presence of the electron acceptor dopant deep in the substrate 14 may not reduce the probability M 2 of creating electron-hole pairs e 3 -h 3 (FIG. 1), nevertheless the distance of the dopant from the upper surface of substrate 14 and far from the n+ junctions 16 and 18 will reduce the probability T of secondary injection, and reduce punch-through.
  • FIG. 3 illustrates one example of a concentration of the electron acceptor dopant, e.g., boron, in terms of depth in the substrate of the NVM device 10 .
  • the boron is concentrated at at least 1 ⁇ 10 17 cm ⁇ 2 at a depth of 0.1 ⁇ m from the upper surface of the substrate 14 and deeper (for example, but not necessarily, to a depth of about 0.8 ⁇ m).
  • the boron concentration is less than 1 ⁇ 10 17 cm ⁇ 2 .
  • the concentration of the electron acceptor dopant deep in the substrate 14 may reduce punch-through (which is generally undesirable in erase operations on the memory device) deep in the substrate 14 .
  • surface punch-through may be reduced in erase operations by using relatively high negative gate voltages (e.g., in the range of ⁇ 5 to ⁇ 7V) and relatively low bit line (e.g., drain) voltages to erase the memory device.
  • FIGS. 4 - 6 illustrate the beneficial effects of the reduced surface concentration of the electron acceptor dopant on reducing secondary injection with no adverse effects on operation (programming and erasing) of the NVM device.
  • FIG. 4 illustrates the effect of eliminating the electron acceptor dopant generally near the upper surface of substrate 14 , as opposed to the presence of pocket or planar implants, on secondary injection of electrons, normalized to current in the substrate 14 (I sub ).
  • the curves illustrate the normalized write time, in terms of T*I sub (wherein T is time in seconds and I sub is the substrate current in pA), versus the change in threshold voltage DV tr in volts.
  • Vds is low ( ⁇ 2V) and Vsub is high ( ⁇ 4V).
  • Curve 26 is the normalized write time for a boron pocket implant whose dose is 0.75 ⁇ 10 13 cm ⁇ 2
  • curve 28 is the normalized write time for no boron pocket implant. It is seen that the presence of the pocket implant (curve 28 ) increases secondary injection by about two orders of magnitude (i.e., about 100 times more).
  • Curve 30 is the normalized write time for a boron planar implant (implant over the entire channel with maximum concentration next to the ONO surface) whose dose is 0.8 ⁇ 10 13 cm 2
  • curve 32 is the normalized write time for no boron planar implant. It is seen that the presence of the planar implant (curve 30 ) increases secondary injection by a factor of about 3,000,000 (three million).
  • the reduction of the electron acceptor dopant generally near the upper surface of substrate 14 may have insignificant or negligible effect on the operation of NVM device 10 .
  • the programming parameters may be, for example, without limitation, a gate voltage of 9 V applied for 2 ⁇ sec.
  • the change in threshold voltage DV tr is plotted for various drain voltages V d .
  • Curves 34 and 35 are plots of the threshold voltage versus drain voltage for a channel length (L d ) of 0.40 ⁇ m, respectively with and without a deep boron pocket implant.
  • Curves 36 and 37 are plots of the threshold voltage versus drain voltage for a channel length (L d ) of 0.50 ⁇ m, respectively with and without a deep boron pocket implant.
  • Curves 38 and 39 are plots of the threshold voltage versus drain voltage for a channel length (L d ) of 0.60 ⁇ m, respectively with and without a deep boron pocket implant. It is seen that the concentration of electron acceptor dopant deep in a double or triple well has negligible effect on the programmed threshold voltage.
  • FIG. 6 illustrates the effect of a deep pocket implant of the electron acceptor dopant on erasing.
  • the erasing parameters may be, for example, without limitation, a gate voltage of ⁇ 5 V applied for 250 ⁇ sec.
  • the change in threshold voltage DV tr is plotted for various drain voltages V d .
  • Curves 40 and 41 are plots of the threshold voltage versus drain voltage for a channel length (L d ) of 0.40 ⁇ m, respectively with and without a deep boron pocket implant. It is seen that the concentration of the electron acceptor dopant deep in a double or triple well has negligible effect on the erased threshold voltage.
  • NROM cells may store more than one bit, wherein two individual bits, a left-side bit and a right-side bit, are stored in physically different areas of the charge-trapping region.
  • One of the bits may be read with a read current I r
  • the other bit may be read with a reverse current (i.e., in the reverse direction, wherein the roles of drain and source are reversed) I rr . It is important to maintain separation between the two bits of a dual-bit NROM cell.

Abstract

A method for forming a non-volatile memory (NVM) device, the method including forming two diffusion areas in a substrate, said diffusion areas forming a channel therebetween, said channel being adapted to permit movement of primary electrons to at least one of the diffusion areas, forming a non-conducting charge trapping layer at least over the channel, and managing at least one of movement of secondary electrons from the substrate towards the charge trapping layer and a punch-through voltage in the substrate by controlling a position of a concentration of an electron acceptor dopant in the substrate.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is related to U.S. Ser. No. 09/519,745, filed Mar. 6, 2000.[0001]
    • FIELD OF THE INVENTION
  • The present invention relates to electrically erasable, programmable read only memory (EEPROM) and nitride, programmable read only memory (NROM) cells in general, and particularly to reducing effects of secondary injection in NROM cells. [0002]
    • BACKGROUND OF THE INVENTION
  • Floating gate memory cells are used for electrically erasable, programmable read only memory (EEPROM) and Flash EEPROM cells. Reference is now made to FIG. 1, which illustrates a typical prior art floating gate memory cell. The floating gate memory cell comprises source and drain portions S and D embedded in a [0003] substrate 5, between which is a channel 7. A floating gate 8 is located above but insulated from channel 7, and a gate 9 is located above but insulated from floating gate 8.
  • For most floating gate cells, the standard electron injection mechanism for programming is channel hot electron injection, in which the source to drain potential drop creates a lateral field that accelerates channel electron e[0004] 1 from source S to drain D, as indicated by arrow 6. Near drain D, the high energy electrons e1 may be injected (arrow 4) into floating gate 8, provided that the gate voltage creates a sufficiently great vertical field.
  • There is another injection mechanism, known as secondary electron injection. As indicated by [0005] arrow 3, some of the channel electrons e1 create hole and electron pairs through impact ionization of valence electrons in channel 7 or drain D. The probability of the ionization is denoted M1 and it indicates the ratio between the channel current and the hole substrate current.
  • Due to the positive potential of drain D, generated electrons e[0006] 2 may be collected (arrow 11) by drain D. However, as indicated by arrow 13, holes h2 may accelerate towards the low substrate potential of substrate 5. On the way, another impact ionization may occur, creating another electron-hole pair e3-h3 with probability M2. Holes h3 are pulled (arrow 15) further into substrate 5 and are no concern. However, electrons e3, called secondary electrons, may be accelerated (arrow 17) towards positive gate 9 where, if they have gained sufficient energy, are injected into floating gate 8, this event having a probability of T.
  • The current for secondary injection is defined as: [0007]
  • I g =I ds *M 1 *M 2 *T
  • wherein I[0008] ds is the channel current from source to drain.
  • Because this current is significant, some floating gate devices have been designed to enhance it, thereby reducing programming time and voltages. [0009]
  • The following articles discuss some possible methods to enhance secondary injection: [0010]
  • J. D. Bude et al., “Secondary Electron Flash—a High Performance, Low Power Flash Technology for 0.35 μm and Below”, IEDM 97, pp. 279-282; [0011]
  • J. D. Bude et al., “EEPROM/Flash Sub 3.0 V Drain-Source Bias Hot Carrier Writing”, IEDM 95, pp. 989-992; and [0012]
  • J. D. Bude and M. R. Pinto, “Modeling Nonequilibrium Hot Carrier Device Effects”, Conference of Insulator Specialists of Europe, Sweden, June 1997. [0013]
  • These references discuss enhancing the secondary generation and injection generally by means of pocket implants of boron, which is an electron acceptor dopant, in the [0014] substrate 5. The pocket implants tend to enhance creation of the electron-hole pairs e3-h3, and thus increase the probability M2.
  • However, secondary injection is not good for all types of memory cells. For nitride read only memory (NROM) cells, enhancing secondary injection may not enhance the operation of the cell and may be detrimental. [0015]
    • SUMMARY OF THE INVENTION
  • The present invention seeks to provide methods and apparatus for reducing effects of secondary injection in non-volatile memory (NVM) devices that have a non-conducting charge trapping layer, such as NROM devices. The reduction of the secondary injection improves endurance and reliability. The present invention also provides methods and apparatus for preventing punch-through voltages from detrimentally affecting erase operations in the NVM device that has a non-conducting charge trapping layer. [0016]
  • In the present invention, the probability T of secondary injection may be reduced by reducing the surface concentration of an electron acceptor dopant, such as, but not limited to, boron. Punch-through voltages in erase operations may be controlled by one or several methods. For example, using relatively high negative gate voltages (e.g., in the range of −5 to −7V) and relatively low bit line (e.g., drain) voltages to erase the memory cell may reduce and suppress surface punch-through. Furthermore, undesirable punch-through currents may be reduced in the substrate by electron acceptor doping far from the gate-substrate interface (i.e., the substrate surface). The electron acceptor doping far from the gate-substrate interface reduces the probability T of secondary injection. The negative gate voltage in erase helps suppress the surface punch-through problem in erase, due to the reduced surface concentration of the electron acceptor dopant. [0017]
  • The surface concentration of the electron acceptor dopant may be reduced and the concentration increased far from the surface by one or several methods. For example, the substrate may be constructed with a double or triple-well process. Doping of the electron acceptor dopant may be constrained to be deep in the NROM cell well or at a medium depth. This may be accomplished, for example, by a deep pocket implant of the dopant. The surface concentration of the electron acceptor dopant may be reduced by doping the surface with an electron donor dopant, such as, but not limited to, phosphor or arsenic. Although the presence of the electron acceptor dopant deep in the substrate may not reduce the probability M[0018] 2 of creating electron-hole pairs e3-h3, nevertheless the distance of the dopant from the surface and far from the n+ junction may reduce the probability T of secondary injection, and reduce punch-through.
  • There is thus provided in accordance with a preferred embodiment of the present invention a method for forming a non-volatile memory (NVM) device, the method including forming two diffusion areas in a substrate, said diffusion areas forming a channel therebetween, the channel being adapted to permit movement of primary electrons to at least one of the diffusion areas, forming a non-conducting charge trapping layer at least over the channel, and managing at least one of movement of secondary electrons from the substrate towards the charge trapping layer and a punch-through voltage in the substrate by controlling a position of a concentration of an electron acceptor dopant in the substrate. [0019]
  • In accordance with a preferred embodiment of the present invention the managing includes concentrating less of the electron acceptor dopant generally near an upper surface of the substrate, the upper surface including an interface between the substrate and the charge trapping layer, and more of the electron acceptor dopant further from the upper surface of the substrate. [0020]
  • Further in accordance with a preferred embodiment of the present invention the managing includes concentrating most of the electron acceptor dopant generally between a position halfway from the upper surface and a lower surface of the substrate. [0021]
  • Still further in accordance with a preferred embodiment of the present invention the method includes constructing the substrate with at least one of a double-well and triple-well process. [0022]
  • In accordance with a preferred embodiment of the present invention less of the electron acceptor dopant may be concentrated generally near the upper surface of the substrate by concentrating more of an electron donor dopant near the upper surface of the substrate. The electron acceptor dopant may comprise boron. The electron donor dopant may comprise at least one of phosphor and arsenic. [0023]
  • Further in accordance with a preferred embodiment of the present invention the non-conducting charge trapping layer may include an oxide-nitride-oxide (ONO) layer. [0024]
  • There is also provided in accordance with a preferred embodiment of the present invention a non-volatile memory (NVM) device including a channel formed in a substrate, two diffusion areas, one on either side of the channel in the substrate, each diffusion area having a junction with the channel, the channel being adapted to permit movement of electrons to at least one of the diffusion areas, a non-conducting charge trapping layer formed at least over the channel, and an electron acceptor dopant concentrated less near an upper surface of the substrate, the upper surface including an interface between the substrate and the charge trapping layer, and concentrated more further from the upper surface of the substrate. [0025]
  • In accordance with a preferred embodiment of the present invention the electron acceptor dopant is concentrated at at least 1×10[0026] 17 cm−2 at a depth of 0.1 μm from the upper surface of the substrate.
  • In accordance with another preferred embodiment of the present invention the electron acceptor dopant is concentrated at at least 1×10[0027] 17 cm−2 at a depth of between 0.1-0.8 μm and deeper from the upper surface of the substrate.
  • In accordance with yet another preferred embodiment of the present invention the electron acceptor dopant is concentrated less than 1×10[0028] 17 cm−2 at a depth of less than 0.1 μm.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present invention will be understood and appreciated more fully from the following detailed description taken in conjunction with the appended drawings in which: [0029]
  • FIG. 1 is a simplified illustration of secondary injection in a prior art floating gate memory cell; [0030]
  • FIG. 2 is a simplified illustration of a non-volatile memory (NVM) device having a surface concentration adapted for reduced secondary injection, constructed and operative in accordance with an embodiment of the invention; [0031]
  • FIG. 3 is a simplified graphical illustration of a concentration of an electron acceptor dopant in terms of depth in the substrate of the NVM device of FIG. 2, in accordance with an embodiment of the invention; [0032]
  • FIG. 4 is a simplified graphical illustration of an effect of reducing an electron acceptor dopant generally near the upper surface of the substrate of the NVM device of FIG. 2, as opposed to the presence of pocket or planar implants, on secondary injection of electrons, in accordance with an embodiment of the invention; and [0033]
  • FIGS. 5 and 6 are simplified graphical illustrations of the effect of a concentration of the electron acceptor dopant deep in the substrate, such as deep in a double or triple well, respectively on programming and erasing, in accordance with an embodiment of the invention. [0034]
    • DETAILED DESCRIPTION OF THE PRESENT INVENTION
  • Reference is now made to FIG. 2, which illustrates a non-volatile memory (NVM) [0035] device 10, constructed and operative in accordance with an embodiment of the invention. The NVM device 10 has a non-conducting charge trapping layer, such as a nitride read only memory (NROM) device, as is now explained.
  • [0036] NVM device 10 preferably includes a channel 12 formed in a substrate 14. Two diffusion areas 16 and 18 are preferably formed on either side of channel 12 in substrate 14, each diffusion area having a junction with channel 12. A non-conducting charge trapping layer, such as, but not limited to, an oxide-nitride-oxide (ONO) layer 20 (i.e., a sandwich of an oxide sub-layer 20A, a nitride sub-layer 20B and an oxide sub-layer 20C) is preferably formed at least over channel 12, and a polysilicon gate 22 is preferably formed at least over ONO layer 20. NROM device 10 may comprise two separated and separately chargeable areas 23A and 23B in the nitride sub-layer 20B, each chargeable area defining and storing one bit.
  • In accordance with an embodiment of the invention, movement of secondary electrons from [0037] substrate 14 towards ONO layer 20 may be managed and may be reduced by controlling a concentration of an electron acceptor dopant in substrate 14. For example, reducing the presence of the electron acceptor dopant generally near an upper surface of substrate 14 (that is, near the interface between substrate 14 and oxide sublayer 20A of ONO layer 20) may significantly reduce secondary electron injection in the direction towards ONO layer 20 and polysilicon gate 22. The electron acceptor dopant may comprise, without limitation, boron.
  • The surface concentration of the electron acceptor dopant may be reduced and the concentration increased far from the upper surface of [0038] substrate 14 by one or several methods. For example, substrate 14 may be constructed with a double or triple implant process. The electron acceptor dopant may be concentrated as a function of depth in the substrate of the NVM device 10, as is further described hereinbelow with reference to FIG. 3. Accordingly, the electron acceptor dopant may be doped by means of a deep or medium-depth pocket implant 24, as indicated generally in FIG. 2. The surface concentration of the electron acceptor dopant may be reduced by doping the surface with an electron donor dopant 25 (indicated generally in FIG. 2), such as, but not limited to, phosphor or arsenic. Although the presence of the electron acceptor dopant deep in the substrate 14 may not reduce the probability M2 of creating electron-hole pairs e3-h3 (FIG. 1), nevertheless the distance of the dopant from the upper surface of substrate 14 and far from the n+ junctions 16 and 18 will reduce the probability T of secondary injection, and reduce punch-through.
  • Reference is now made to FIG. 3, which illustrates one example of a concentration of the electron acceptor dopant, e.g., boron, in terms of depth in the substrate of the [0039] NVM device 10. It is, however, emphasized that the invention is not limited to the concentration shown in FIG. 3. In FIG. 3, the boron is concentrated at at least 1×1017 cm−2 at a depth of 0.1 μm from the upper surface of the substrate 14 and deeper (for example, but not necessarily, to a depth of about 0.8 μm). At a depth of less than 0.1 μm, the boron concentration is less than 1×1017 cm−2.
  • The concentration of the electron acceptor dopant deep in the [0040] substrate 14 may reduce punch-through (which is generally undesirable in erase operations on the memory device) deep in the substrate 14. In one embodiment of the present invention, surface punch-through may be reduced in erase operations by using relatively high negative gate voltages (e.g., in the range of −5 to −7V) and relatively low bit line (e.g., drain) voltages to erase the memory device.
  • FIGS. [0041] 4-6 illustrate the beneficial effects of the reduced surface concentration of the electron acceptor dopant on reducing secondary injection with no adverse effects on operation (programming and erasing) of the NVM device.
  • Reference is now made to FIG. 4, which illustrates the effect of eliminating the electron acceptor dopant generally near the upper surface of [0042] substrate 14, as opposed to the presence of pocket or planar implants, on secondary injection of electrons, normalized to current in the substrate 14 (Isub). The curves illustrate the normalized write time, in terms of T*Isub (wherein T is time in seconds and Isub is the substrate current in pA), versus the change in threshold voltage DVtr in volts. To verify that the programming is done by secondary injection, rather than channel hot electron injection, Vds is low (˜2V) and Vsub is high (˜4V). Curve 26 is the normalized write time for a boron pocket implant whose dose is 0.75×1013 cm−2, whereas curve 28 is the normalized write time for no boron pocket implant. It is seen that the presence of the pocket implant (curve 28) increases secondary injection by about two orders of magnitude (i.e., about 100 times more).
  • [0043] Curve 30 is the normalized write time for a boron planar implant (implant over the entire channel with maximum concentration next to the ONO surface) whose dose is 0.8×1013 cm2, whereas curve 32 is the normalized write time for no boron planar implant. It is seen that the presence of the planar implant (curve 30) increases secondary injection by a factor of about 3,000,000 (three million).
  • The reduction of the electron acceptor dopant generally near the upper surface of [0044] substrate 14 may have insignificant or negligible effect on the operation of NVM device 10. For example, reference is now made to FIG. 5, which illustrates the effect of a deep pocket implant of the electron acceptor dopant on programming. The programming parameters may be, for example, without limitation, a gate voltage of 9 V applied for 2 μsec. The change in threshold voltage DVtr is plotted for various drain voltages Vd. Curves 34 and 35 are plots of the threshold voltage versus drain voltage for a channel length (Ld) of 0.40 μm, respectively with and without a deep boron pocket implant. Curves 36 and 37 are plots of the threshold voltage versus drain voltage for a channel length (Ld) of 0.50 μm, respectively with and without a deep boron pocket implant. Curves 38 and 39 are plots of the threshold voltage versus drain voltage for a channel length (Ld) of 0.60 μm, respectively with and without a deep boron pocket implant. It is seen that the concentration of electron acceptor dopant deep in a double or triple well has negligible effect on the programmed threshold voltage.
  • Reference is now made to FIG. 6, which illustrates the effect of a deep pocket implant of the electron acceptor dopant on erasing. The erasing parameters may be, for example, without limitation, a gate voltage of −5 V applied for 250 μsec. The change in threshold voltage DV[0045] tr is plotted for various drain voltages Vd. Curves 40 and 41 are plots of the threshold voltage versus drain voltage for a channel length (Ld) of 0.40 μm, respectively with and without a deep boron pocket implant. It is seen that the concentration of the electron acceptor dopant deep in a double or triple well has negligible effect on the erased threshold voltage.
  • NROM cells may store more than one bit, wherein two individual bits, a left-side bit and a right-side bit, are stored in physically different areas of the charge-trapping region. One of the bits may be read with a read current I[0046] r, while the other bit may be read with a reverse current (i.e., in the reverse direction, wherein the roles of drain and source are reversed) Irr. It is important to maintain separation between the two bits of a dual-bit NROM cell.
  • It will be appreciated by persons skilled in the art that the present invention is not limited by what has been particularly shown and described herein above. Rather the scope of the invention is defined by the claims that follow: [0047]

Claims (18)

What is claimed is:
1. A method for forming a non-volatile memory (NVM) device, the method comprising:
forming two diffusion areas in a substrate, said diffusion areas forming a channel therebetween, said channel being adapted to permit movement of primary electrons to at least one of said diffusion areas;
forming a non-conducting charge trapping layer at least over said channel; and
managing at least one of movement of secondary electrons from said substrate towards said charge trapping layer and a punch-through voltage in said substrate by controlling a position of a concentration of an electron acceptor dopant in said substrate.
2. The method according to claim 1 wherein said managing comprises concentrating less of the electron acceptor dopant generally near an upper surface of said substrate, said upper surface comprising an interface between said substrate and said charge trapping layer, and more of the electron acceptor dopant further from said upper surface of said substrate.
3. The method according to claim 1 wherein said managing comprises concentrating most of the electron acceptor dopant generally between a position half-way from the upper surface and a lower surface of said substrate.
4. The method according to claim 1 and further comprising constructing said substrate with at least one of a double-well and triple-well process.
5. The method according to claim 2 wherein said managing comprises concentrating less of the electron acceptor dopant generally near said upper surface of said substrate by concentrating more of an electron donor dopant near said upper surface of said substrate.
6. The method according to claim 1 wherein said electron acceptor dopant comprises boron.
7. The method according to claim 5 wherein said electron donor dopant comprises at least one of phosphor and arsenic.
8. The method according to claim 1 wherein forming said non-conducting charge trapping layer comprises forming an oxide-nitride-oxide (ONO) layer.
9. A non-volatile memory (NVM) device comprising:
a channel formed in a substrate;
two diffusion areas, one on either side of said channel in said substrate, each diffusion area having a junction with said channel, said channel being adapted to permit movement of primary electrons to at least one of said diffusion areas;
a non-conducting charge trapping layer formed at least over said channel; and
an electron acceptor dopant concentrated less near an upper surface of said substrate, said upper surface comprising an interface between said substrate and said charge trapping layer, and concentrated more further from said upper surface of said substrate.
10. The device according to claim 9 wherein most of said electron acceptor dopant is concentrated generally between a position halfway from the upper surface and a lower surface of said substrate.
11. The device according to claim 9 wherein said substrate is constructed with at least one of a double-well and triple-well process.
12. The device according to claim 9 wherein an electron donor dopant is concentrated more near said upper surface of said substrate than further from said upper surface of said substrate.
13. The device according to claim 9 wherein said electron acceptor dopant comprises boron
14. The device according to claim 12 wherein said electron donor dopant comprises at least one of phosphor and arsenic.
15. The device according to claim 9 wherein said non-conducting charge trapping layer comprises an oxide-nitride-oxide (ONO) layer.
16. The device according to claim 9 wherein said electron acceptor dopant is concentrated at at least 1×1017 cm−2 at a depth of 0.1 μm from the upper surface of said substrate.
17. The device according to claim 9 wherein said electron acceptor dopant is concentrated at at least 1×1017 cm−2 at a depth of between 0.1-0.8 μm and deeper from the upper surface of said substrate.
18. The device according to claim 9 wherein said electron acceptor dopant is concentrated less than 1×1017 cm−2 at a depth of less than 0.1 μm.
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Publication number Priority date Publication date Assignee Title
WO2005060000A2 (en) * 2003-12-19 2005-06-30 Infineon Technologies Ag Bridge field-effect transistor storage cell, device comprising said cells and method for producing a bridge field-effect transistor storage cell
WO2005060000A3 (en) * 2003-12-19 2005-10-27 Infineon Technologies Ag Bridge field-effect transistor storage cell, device comprising said cells and method for producing a bridge field-effect transistor storage cell
DE102005045371B4 (en) * 2005-07-29 2010-04-15 Qimonda Ag Semiconductor memory, the production thereof, and method for operating the semiconductor memory

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US6583007B1 (en) 2003-06-24
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JP2003273256A (en) 2003-09-26

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