US20030030137A1 - Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument - Google Patents
Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument Download PDFInfo
- Publication number
- US20030030137A1 US20030030137A1 US10/267,641 US26764102A US2003030137A1 US 20030030137 A1 US20030030137 A1 US 20030030137A1 US 26764102 A US26764102 A US 26764102A US 2003030137 A1 US2003030137 A1 US 2003030137A1
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- substrate
- semiconductor device
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- semiconductor chips
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
A semiconductor device comprises a plurality of semiconductor chips (20, 30) having electrodes (22, 32) and aligned in the horizontal direction; a substrate (10) on which is formed an interconnect pattern (12) having bonding portions (14) connected to the electrodes (22, 32) of the semiconductor chips (20, 30) and lands (16) connected to the bonding portions (14), and external electrodes (40) provided on the lands (16) and connected to the electrodes (22,32) through an interconnect pattern (12).
Description
- The present invention relates to a semiconductor device and method of manufacturing the same, to a circuit board and to an electronic instrument.
- In recent years, with the increasing compactness of electronic instruments, the development of multichip modules incorporating a plurality of semiconductor chips at high density is proceeding. With a multichip module, since an existing plurality of semiconductor chips can be used, the cost can be reduced compared with the design of a new integrated circuit.
- However, conventional multichip modules have used wire bonding to connect interconnect pattern of a substrate to the electrodes of the semiconductor chip. As a result, the interconnect pattern requires bonding pads for the wires, and therefore the area of the substrate is increased, preventing the required compactness of the package from being fully achieved.
- The present invention solves this problems, and has as its object the provision of a compact semiconductor device incorporating a plurality of semiconductor chips at high density and a method of manufacturing the same, of a circuit board and of an electronic instrument.
- (1) A semiconductor device of the present invention comprises:
- a plurality of semiconductor chips having electrodes, and aligned in a horizontal direction for face-down bonding;
- a substrate on which an interconnect pattern is formed, the interconnect pattern having bonding portions to which the electrodes of the semiconductor chip are connected, and lands to which the bonding portions are electrically connected; and
- external electrodes provided on the lands.
- According to this aspect of the present invention, a plurality of semiconductor chips is aligned in a horizontal direction and mounted on a substrate. Each semiconductor chip is subjected to face-down bonding. Since the bonding is carried out within the region where the semiconductor chip is mounted, the area of the substrate can be kept to the minimum required. As a result, the semiconductor device can be made more compact.
- (2) In the semiconductor device:
- the external electrodes may be disposed within mounting regions of the semiconductor chips.
- By means of this, external electrodes can be provided corresponding to the electrodes of the semiconductor chip, within the region where each semiconductor chip is mounted.
- (3) In the semiconductor device:
- the external electrodes may be disposed outside regions where the semiconductor chips are mounted.
- By means of this, the external electrodes can be aligned on the periphery of the substrate.
- (4) In the semiconductor device:
- the substrate may be a flexible substrate and is formed to be larger than the regions where the semiconductor chips are mounted, and a flat support member may be provided on a periphery of the substrate.
- By means of this, even if a flexible substrate is used, the uniform height (coplanarity) of the external electrodes can be assured by means of the flat support member.
- (5) In the semiconductor device:
- the external electrodes may be disposed within a region where any one of the semiconductor chips is mounted.
- By means of this, all of the external electrodes can be provided within the region where any one of the semiconductor chips is mounted, and no external electrodes can be provided within the region where any other semiconductor chip is mounted.
- (6) In the semiconductor device:
- the substrate may be a flexible substrate and part of the substrate is bent; and
- a surface of the one semiconductor chip, which is disposed at a region where the external electrodes are provided, opposite to a surface on which the electrodes are formed may be adhered to a surface of at least one remaining semiconductor chip opposite to a surface on which the electrodes are formed.
- Since on the semiconductor chip another semiconductor chip is adhered, the size of the semiconductor device in the horizontal direction can be reduced.
- (7) In the semiconductor device:
- the substrate may have at least one hole formed along a region to be bent.
- By forming the hole in the substrate, the resilience of the substrate can be reduced, and the bent state can be more easily maintained.
- (8) In the semiconductor device:
- the hole may be a slot extending along a bending line;
- the interconnect pattern may be formed to pass over the hole; and
- an edge of the slot extending along the bending line may form a part of an outer edge.
- Since a part of the outer edge of the semiconductor device is formed by an edge of the slot, the edge of the semiconductor device can be positioned accurately.
- (9) In the semiconductor device:
- a plurality of the holes may be formed;
- the interconnect pattern may be formed to pass over the plurality of holes; and
- the plurality of holes may be slots extending along a bending line, and are aligned.
- By means of this, the substrate may be made easier to bend.
- (10) In the semiconductor device:
- the substrate may have a slit formed along a region to be bent; and
- the substrate may be divided by the slit, and a gap may be opened up between opposing divided edges.
- When the divided substrate is considered as a whole, it can be bent more easily.
- (11) In the semiconductor device:
- a joining member may be provided spanning the slit.
- By means of this, the bent portion of the substrate can be supported by the joining member.
- (12) In the semiconductor device:
- a flexible resin may be provided on the interconnect pattern in the hole; and
- the resin may be bent together with the substrate.
- By means of this, the bent portion of the substrate can be supported by the resin.
- (13) In the semiconductor device:
- the semiconductor chips may be adhered by an electrically conductive adhesive or a thermally conductive adhesive.
- When an electrically conductive adhesive is used, the electrical potential of the adhering surfaces of the semiconductor chips can be made the same. When a thermally conductive adhesive is used, cooling can be achieved by passing heat from the semiconductor chip which emits more heat to the semiconductor chip which emits less heat.
- (14) In the semiconductor device:
- a surface area of one of the semiconductor chips may be larger than a surface area of a remaining semiconductor chip; and
- the external electrodes may be formed only in a region where the semiconductor chip having a larger surface area is provided.
- By means of this, the largest possible region for providing the external electrodes can be assured, without going outside the surface area of the semiconductor chip.
- (15) In the semiconductor device:
- the electrodes of the semiconductor chips may be connected to the bonding portions by an anisotropically conductive material including conductive particles dispersed in an adhesive.
- Since the bonding portions and electrodes are electrically connected by the anisotropically conductive material, a semiconductor device can be manufactured by a method of outstanding reliability and productivity.
- (16) A method of manufacturing a semiconductor device of the present invention comprises:
- a step of providing a substrate on which an interconnect pattern is formed, the interconnect pattern having a plurality of bonding portions and a plurality of lands electrically connected to the bonding portions, and providing a plurality of semiconductor chips having electrodes;
- a step of providing anisotropically conductive materials including conductive particles dispersed in an adhesive at least on the bonding portions;
- a step of positioning the electrodes over the bonding portions on the anisotropically conductive materials, and mounting the semiconductor chips over the substrate;
- a step of applying pressure to at least one of the semiconductor chips and the substrate so that the bonding portions and the electrodes are electrically connected by the conductive particles; and
- a step of forming external electrodes on the lands.
- According to this aspect of the present invention, a plurality of semiconductor chips is mounted on the substrate, and the electrodes of the semiconductor chips and bonding portions are subjected to face-down bonding. Therefore, since the bonding is carried out within the region where the semiconductor chip is mounted, the area of the substrate can be kept to the minimum required. As a result, the semiconductor device can be made more compact.
- Since the bonding portions and electrodes are electrically connected by the anisotropically conductive material, a semiconductor device can be manufactured by a method of outstanding reliability and productivity.
- (17) In this method,
- the substrate may be a flexible substrate and formed to be larger than the regions where the semiconductor chips are mounted; and
- a flat support member may be provided on a periphery of the substrate.
- By means of this, even if a flexible substrate is used, the uniform height (coplanarity) of the external electrodes can be assured. In the case where all of the external electrodes are provided outside the region where all of the semiconductor chips are mounted, the external electrodes can be provided on the region to which the flat support member is attached.
- (18) The method may further comprise a step of bending a part of the substrate, after the step of mounting the semiconductor chips on the substrate, so that a surface of one of the semiconductor chips opposite to a surface where the electrodes are provided is adhered to a surface of another of the semiconductor chips opposite to a surface on which the electrodes are formed.
- Since on the semiconductor chip another semiconductor chip is adhered, the size of the semiconductor device in the horizontal direction can be reduced.
- (19) In this method,
- the substrate may have at least one hole formed along a region to be bent.
- In this way, by forming a hole in the substrate, the resilience of the substrate can be reduced, and the substrate can be made easier to bend.
- (20) The circuit board of the present invention has the above described semiconductor device mounted.
- (21) The electronic instrument of the present invention has the above described circuit board.
- FIGS. 1A to1C show a first embodiment of the semiconductor device to which the present invention is applied;
- FIGS. 2A to2C show a second embodiment of the semiconductor device to which the present invention is applied;
- FIGS. 3A to3C show a third embodiment of the semiconductor device to which the present invention is applied;
- FIG. 4 shows a modification of the third embodiment to which the present invention is applied;
- FIG. 5 shows a fourth embodiment of the semiconductor device to which the present invention is applied;
- FIGS. 6A to6C show a development of a fourth embodiment of the semiconductor device to which the present invention is applied;
- FIG. 7 shows a development of a fifth embodiment of the semiconductor device to which the present invention is applied;
- FIG. 8 shows a development of a sixth embodiment of the semiconductor device to which the present invention is applied;
- FIG. 9 shows a development of a seventh embodiment of the semiconductor device to which the present invention is applied;
- FIG. 10 shows an eighth embodiment of the semiconductor device to which the present invention is applied;
- FIG. 11 shows a ninth embodiment of the semiconductor device to which the present invention is applied;
- FIG. 12 shows a circuit board on which the semiconductor device of this embodiment is mounted;
- FIG. 13 shows an electronic instrument having a circuit board on which the semiconductor device of this embodiment is mounte.
- The present invention is now described in terms of a number of preferred embodiments, with reference to the drawings.
- First Embodiment
- FIGS. 1A to1C show a first embodiment of the semiconductor device to which the present invention is applied. It should be noted that FIG. 1A is a plan view of the semiconductor device, FIG. 1B is a cross-sectional view along the line IB-IB in FIG. 1A, and FIG. 1C is a bottom view of the semiconductor device. A
semiconductor device 1 comprises a substrate 10 a plurality (for example two) ofsemiconductor chips external electrodes 40. - The
substrate 10 may be formed of either of an organic or inorganic material, or may be a compound construction thereof. As asubstrate 10 formed of an organic material may be cited, for example, a flexible substrate formed of a polyimide resin. As asubstrate 10 formed of an inorganic material may be cited, for example, a ceramic substrate or glass substrate. As a compound construction of organic and inorganic materials may be cited, for example, a glass epoxy substrate. - On the
substrate 10, is formed aninterconnect pattern 12. Theinterconnect pattern 12 is formed on one surface of thesubstrate 10. It should be noted that in addition to theinterconnect pattern 12 formed on the one surface of thesubstrate 10, an interconnect pattern may also be formed on the other surface. - The
interconnect pattern 12 can be formed by covering thesubstrate 10 with copper or the like by sputtering or the like to form a conductive film, and etching the same. In this case, theinterconnect pattern 12 is formed directly on thesubstrate 10, and forms a two-layer substrate without an intervening adhesive. Alternatively, a three-layer substrate may be used with an adhesive interposed between thesubstrate 10 and theinterconnect pattern 12. Alternatively, a built-up substrate of multi-layer construction may be used, with an insulating resin and interconnect pattern laminated on the substrate, or a multi-layer substrate with a plurality of substrates laminated may be used. - The
interconnect pattern 12 includes a plurality ofbonding portions 14 and a plurality oflands 16. Each of thebonding portions 14 is electrically connected to at least one of thelands 16. Thebonding portions 14 and lands 16 are formed to be larger in area than the interconnect portions. It should be noted that bumps may be formed on thebonding portions 14. - The
bonding portions 14 and lands 16 are formed within the mounting region of each of the semiconductor chips 20 and 30 on thesubstrate 10, and are not formed outside these regions. Thebonding portions 14 positioned within the mounting regions of each of the semiconductor chips 20 and 30 are connected to thelands 16 positioned within the respective mounting region. Alternatively,bonding portions 14 positioned within the mounting region of either one of the semiconductor chips 20 and 30 may be connected tolands 16 positioned within the mounting region of the other of the semiconductor chips 20 and 30. To simplify trimming die, thesubstrate 10 may be formed to be oblong as shown in the drawing, and where even more extreme compactness is required, may be formed along the outline of the semiconductor chip. - In the
substrate 10 are formed throughholes 18. On the throughholes 18 are positioned thelands 16. That is to say, thelands 16 are able to be connected to the surface opposite to the surface of formation of theinterconnect pattern 12 through the through holes 18. In this way, on the surface of thesubstrate 10 opposite to the surface where theinterconnect pattern 12 is formed, a plurality of external electrodes 40 (see FIG. 1C) electrically connected to theinterconnect pattern 12 can be formed. - The plurality of
semiconductor chips electrodes electrodes bonding portions 14, and are electrically connected through an anisotropicallyconductive material 50. That is to say, the semiconductor chips 20 and 30 are subjected to face-down bonding to theinterconnect pattern 12 of thesubstrate 10 by facing down the surfaces on which theelectrodes electrodes - The anisotropically
conductive material 50 comprises an adhesive (binder) in which conductive particles (conductive filler) is dispersed, and may also include a dispersant. The anisotropicallyconductive material 50 may be preformed into a sheet, then adhered to thesubstrate 10, or may be disposed in liquid form on thesubstrate 10. A thermosetting adhesive is commonly used as the adhesive of the anisotropicallyconductive material 50. The anisotropicallyconductive material 50 is provided at least on thebonding portions 14. Alternatively, when the anisotropicallyconductive material 50 is provided to cover the whole of thesubstrate 10, this step can be carried out simply. When the anisotropicallyconductive material 50 is provided to exclude the periphery of thesubstrate 10, the anisotropicallyconductive material 50 will not be attached to the peripheral surface of thesubstrate 10, which is convenient for the later handling of thesubstrate 10. - The anisotropically
conductive material 50 is squeezed between theelectrodes bonding portions 14, and the conductive particles are arranged to provide electrical conduction therebetween. In this embodiment, the semiconductor chips 20 and 30 are subject to face-down bonding. When the face-down bonding is performed, instead of using the anisotropicallyconductive material 50, any of at least one of light, heat, pressure, and vibration may be used to bond theelectrodes bonding portions 14. In this case, the reliability is highest with metal-to-metal bonding. In this case, between the semiconductor chips 20 and 30 and thesubstrate 10 is commonly filled with an underfill resin. - The
external electrodes 40 are provided onlands 16 of theinterconnect pattern 12. In more detail, theexternal electrodes 40 are provided on the surface opposite to the surface where theinterconnect pattern 12 is formed on thesubstrate 10, and are electrically connected to thelands 16 through the through holes 18. The electrical connection of theexternal electrodes 40 to thelands 16 is commonly achieved by providing solder balls together with flux on the through holes on the surface of the substrate opposite to that on which the semiconductor chips are mounted, and formed by a reflow process, but may equally be achieved by providing a conductive material such as gold or copper plated on the inner surface of the through holes 18. Alternatively, when solder balls are used as theexternal electrodes 40, the throughholes 18 may be filled with the solder which is the material of the solder balls, and a conductive material formed integrally with the solder balls within the through holes 18. - Further, on the surface opposite to the semiconductor chip mounting surface, may be formed lands for external electrodes connected by via holes or through holes to the
interconnect pattern 12, and external electrodes may be formed thereon. The external electrodes may equally be formed of a metal other than the solder described above, or of a conductive resin, or the like. - As described above, when all of the
lands 16 are positioned within the mounting region of the semiconductor chips 20 and 30, theexternal electrodes 40 are also positioned within the mounting region of the semiconductor chips 20 and 30 (FAN-IN structure). When bondingportions 14 provided within the mounting region of some of the semiconductor chips 20 and 30 are connected tolands 16 provided within the mounting region, theexternal electrodes 40 are also electrically connected toelectrodes semiconductor chips external electrodes 40 are provided. - According to this embodiment, the plurality of
semiconductor chips substrate 10, and theelectrodes bonding portions 14. Therefore, since bonding is carried out within the region of the semiconductor chips 20 and 30, the area of thesubstrate 10 can be kept to the minimum required. As a result, thesemiconductor device 1 can be made compact. - This embodiment has the above described construction, and one example of a method of manufacturing the same is now described. First, the
substrate 10 having formed thereon theinterconnect pattern 12 which has a plurality ofbonding portions 14 and a plurality oflands 16 connected to thebonding portions 14 is provided in advance. Then on the surface of thesubstrate 10 on which theinterconnect pattern 12 is formed, the anisotropicallyconductive material 50 is provided. In more detail, the anisotropicallyconductive material 50 is provided on at least thebonding portions 14. - The plurality of the semiconductor chips20 and 30 having a plurality of
electrodes electrodes bonding portions 14 of the anisotropicallyconductive material 50, and the semiconductor chips 20 and 30 are mounted on thesubstrate 10. - Next, at least one of the semiconductor chips20 and 30 and the
substrate 10 is pressed, and thebonding portions 14 and theelectrodes conductive material 50. - Then from the surface of the
substrate 10 opposite to that on which theinterconnect pattern 12 is formed, with throughholes 18 interposed, theexternal electrodes 40 are formed on thelands 16. - By the above process, the
semiconductor device 1 is obtained. According to this embodiment, since thebonding portions 14 andelectrodes conductive material 50, asemiconductor device 1 can be manufactured by a method of outstanding reliability and manufacturing characteristics. - Second Embodiment
- FIGS. 2A to2C shows a second embodiment of the semiconductor device to which the present invention is applied. It should be noted that FIG. 2A is a plan view of the semiconductor device, FIG. 2B is a cross-sectional view along the line IIB-IIB in FIG. 2A, and FIG. 2C is a bottom view of the semiconductor device. A
semiconductor device 2 includes asubstrate 110,external electrodes 140, and the plurality (for example, two) ofsemiconductor chips - On the
substrate 110 is formed aninterconnect pattern 112. Theinterconnect pattern 112 includesbonding portions 114 and lands 116. Thebonding portions 114 are provided in positions corresponding to theelectrodes lands 116 are formed only within the mounting region of one of the semiconductor chips 20 and 30. Therefore, thelands 116 within this one of the mounting regions are electrically connected to thebonding portions 114 within the other of the mounting regions throughinterconnects 115. - Since the
lands 116 are formed in this way, theexternal electrodes 140 are also formed only within the mounting region of one of the semiconductor chips 20 and 30. It should be noted that in FIG. 2C, for simplification a reduced number of theexternal electrodes 140 are shown, and a larger number of theexternal electrodes 140 can actually be provided. - Other than this, the structure and method of manufacture is the same as in the first embodiment described above. Depending on the interconnect pattern of the mounting substrate or motherboard, it may be beneficial for all of the
external electrodes 140 to be concentrated in a single location as in the second embodiment of thesemiconductor device 2. - To prevent inclination of the semiconductor device due to a weight imbalance during mounting on the motherboard, a projection of the same size, height, and form as the
external electrodes 140 may be formed on the surface of thesubstrate 110 opposite to that on which thesemiconductor chip 20 is mounted. This projection may be formed of resin or tape or the like. - Third Embodiment
- FIGS. 3A to3C show a third embodiment of the semiconductor device to which the present invention is applied. It should be noted that FIG. 3A is a plan view of the semiconductor device, FIG. 3B is a cross-sectional view along the line IIIB-IIIB in FIG. 3A, and FIG. 3C is a bottom view of the semiconductor device. A
semiconductor device 3 includes asubstrate 210,external electrodes 240, and the plurality (for example, two) ofsemiconductor chips - On the
substrate 210 is formed aninterconnect pattern 212. Theinterconnect pattern 212 includesbonding portions 214 and lands 216. Thebonding portions 214 are provided in positions corresponding to theelectrodes lands 216 are formed on the outside of the mounting region of the semiconductor chips 20 and 30. Therefore, thebonding portions 214 within the mounting region of the semiconductor chips 20 and 30 and thelands 216 positioned outside this mounting region are electrically connected throughinterconnects 215. Thesubstrate 210 is formed to be larger than the mounting region of the semiconductor chips 20 and 30. - Since the
lands 216 are formed in this way, theexternal electrodes 240 are also formed outside the mounting region of the semiconductor chips 20 and 30 (FAN-OUT structure). It should be noted that in FIG. 3C, for simplification a reduced number of theexternal electrodes 240 are shown, and in practice a larger number of theexternal electrodes 240 can be provided. - On the
substrate 210 is provided aflat support member 200 which is rigid, for example of metal. Theflat support member 200 serves to reinforce thesubstrate 210 and maintain flatness, so that as long as it is rigid there are no restrictions on the material. For example, a metal such as stainless steel or a copper alloy is commonly used, but this may also be formed of plastic, ceramic, or another insulating material. In this embodiment, the anisotropicallyconductive material 50 is provided on theinterconnect pattern 212, and when there is no conduction from the conductive particles of the anisotropicallyconductive material 50, even if a metalflat support member 200 is used, electrical conduction between theinterconnect pattern 212 and theflat support member 200 can be prevented. Alternatively, when theflat support member 200 is formed of an insulating material, there may be an electrical connection from the conductive particles of the anisotropicallyconductive material 50. By forming an insulation layer at least on the contact surface with the anisotropicallyconductive material 50 on theflat support member 200, electrical conduction between theinterconnect pattern 212 and theflat support member 200 can be prevented even if theflat support member 200 is of metal. Theflat support member 200 may be adhered to thesubstrate 210 with a general insulating adhesive other than the anisotropically conductive material. - The
flat support member 200 is adhered outside the mounting region of the semiconductor chips 20 and 30 or the on the periphery of thesubstrate 210 by the anisotropicallyconductive material 50. Therefore, even if thesubstrate 210 is a flexible substrate, the flatness of the portion outside the semiconductor chips 20 and 30 and the periphery of thesubstrate 210 can be assured. In this embodiment, the flatness of the region of thesubstrate 210 in which theexternal electrodes 240 are provided is assured by theflat support member 200, as a result of which the uniform height (coplanarity) of theexternal electrodes 240 can be assured. Other than this, the structure and method of manufacture is the same as in the first embodiment described above, and description is omitted. - It should be noted that in this embodiment, in the mounting region of the semiconductor chips20 and 30 on the
substrate 210, noexternal electrodes 240 are provided, but in this region also, external electrodes may be provided (FAN-IN/OUT structure). In addition, or as an alternative, external electrodes may be provided in the region between thesemiconductor chip 20 and thesemiconductor chip 30. Thesemiconductor device 4 shown in FIG. 4 is an example showing theexternal electrodes 240 provided inside and outside of the mounting region of the semiconductor chips 20 and 30 and between the semiconductor chips 20 and 30 on thesubstrate 210. - It should be noted that in the third embodiment, when the
substrate 210 itself has flatness retaining properties (for example when thesubstrate 210 is of ceramic or glass epoxy), then theflat support member 200 is not necessarily required. - Fourth Embodiment
- FIG. 5 shows a fourth embodiment of the semiconductor device to which the present invention is applied, and FIGS. 6A to6C show a development of the substrate of the semiconductor device shown in FIG. 5. It should be noted that FIG. 6A is a plan view, FIG. 6B is a cross-sectional view along the line VB-VB in FIG. 6A, and FIG. 6C is a bottom view. A
semiconductor device 5 includes asubstrate 310,semiconductor chips external electrodes 340. - The
substrate 310, is as shown in FIG. 5 formed of a material which can be bent, and in particular in the case of a two-layer flexible substrate or in the case that the interconnect density is required to be further increased, a built-up type of flexible substrate is preferable. Thesubstrate 310 forms an oblong shape, longer in one direction. At both ends of thissubstrate 310, thesemiconductor chips semiconductor chips - An
interconnect pattern 312 is formed on thesubstrate 310. Theinterconnect pattern 312 includesbonding portions 314 and lands 316. Thebonding portions 314 are provided in positions corresponding toelectrodes semiconductor chips conductive material 350. On the other hand, thelands 316 are formed only within the mounting region of one of thesemiconductor chips lands 316 within this one mounting region and thebonding portions 314 within the other mounting region are electrically connected throughinterconnects 315. Theinterconnects 315 are formed between thesemiconductor chips protective layer 302 of resist or the like. - Since the
lands 316 are formed in this way, theexternal electrodes 340 are also formed only within the mounting region of one of thesemiconductor chips external electrodes 340 are shown, and in practice a larger number of theexternal electrodes 340 can be provided. With regard to the disposition of theexternal electrodes 340, as described in the third embodiment, they may equally be disposed using a flat support member on the outside of the semiconductor chip. - In this embodiment, the region of the
substrate 310 between thesemiconductor chips substrate 310 on which thesemiconductor chips substrate 310 is bent gradually without forming a crease, but equally thesubstrate 310 may forma crease. In thesubstrate 310, as shown in FIGS. 6A and 6C, in the bending region at least one, or a plurality ofholes 300 may be formed. By this means, the resilience of thesubstrate 310 is reduced, and it can be more easily bent, and becomes easier to hold the bent form. It should be noted that theinterconnects 315 are preferably formed so as to avoid theholes 300, but theinterconnects 315 may be formed over theholes 300. - The
substrate 310 is bent, and the surface of thesemiconductor chip 320 opposite to the surface on which theelectrodes 322 are formed, and the surface of thesemiconductor chip 330 opposite to the surface on which theelectrodes 332 are formed are adhered by an adhesive 304. The bent form of thesubstrate 310 is maintained by the adhesive force of the adhesive 304. Since the surfaces of thesemiconductor chips semiconductor chips semiconductor chips semiconductor chips semiconductor chips - Except for the above described points, the construction is the same as in the first embodiment described above, and description is omitted. It should be noted that semiconductor chips of different sizes may be used, but in this case when the larger semiconductor chip is disposed on the side of formation of the
external electrodes 340, this will give greater geometrical stability, and is preferable. - In this embodiment, two
semiconductor chips - Further, without bending and superimposing the substrate for each single semiconductor chip, a plurality of semiconductor chips may be mounted on plane, and then the substrate bent and superimposed.
- In this embodiment of the
semiconductor device 5, a plurality of thesemiconductor chips semiconductor device 5, the same method can be applied as that described in the first embodiment, except for the bending of thesubstrate 310. - Fifth Embodiment
- FIG. 7 is a development of a fifth embodiment of the substrate of the semiconductor device to which the present invention is applied. In this embodiment of the semiconductor device also, as with the
semiconductor device 5 shown in FIG. 5, asubstrate 410 is in a bent configuration. On thesubstrate 410, as in the fourth embodiment, thesemiconductor chips - In the
substrate 410 shown in FIG. 7, at least onehole 400 is formed. Thehole 400 is a slot extending along the bending line of thesubstrate 410. In other words, thesubstrate 410 is bent along thehole 400 which is a slot. In FIG. 7, a plurality ofholes 400 is aligned. Since theholes 400 are formed inside a side edge of thesubstrate 410, an edge portion of thesubstrate 410 remains. Therefore, thesubstrate 410 remains connected without being divided apart. - On the
substrate 410 aninterconnect pattern 412 is formed. Theinterconnect pattern 412 is formed to pass over theholes 400. Since thesubstrate 410 is connected even with theholes 400 formed, theinterconnect pattern 412 is not divided. - When the
substrate 410 of the above construction is bent as thesubstrate 310 in FIG. 5, the edge where theholes 400 are formed forms part of the outer edge of the semiconductor device. Therefore, since the semiconductor device forms a clear outline, positioning is easy. - To other aspects of the embodiment, the description under the fourth embodiment can be applied.
- Sixth Embodiment
- FIG. 8 is a development of a sixth embodiment of the substrate of the semiconductor device to which the present invention is applied. In this embodiment of the semiconductor device also, as with the
semiconductor device 5 shown in FIG. 5, asubstrate 510 is in a bent configuration. On thesubstrate 510, as in the fourth embodiment, thesemiconductor chips - The
substrate 510 shown in FIG. 8 has aslit 500 formed, whereby it is divided. In other words, the both dividing edges of thesubstrate 510 is spaced apart whereby theslit 500 is formed. Theslit 500 extends along the bending line of thesubstrate 510. In other words, thesubstrate 510 is bent along theslit 500. - On the
substrate 510, aninterconnect pattern 512 is formed. Theinterconnect pattern 512 is formed to pass over theslit 500. Since thesubstrate 510 is divided, it is preferable for the width of theinterconnect pattern 512 to be greater than the width of theinterconnect pattern 412 shown in FIG. 7. - When the
substrate 510 of the above construction is bent as thesubstrate 310 in FIG. 5, the edge where theslit 500 is formed forms part of the outer edge of the semiconductor device. Therefore, since the semiconductor device forms a clear outline, positioning is easy. - To other aspects of the embodiment, the description under the fourth embodiment can be applied.
- Seventh Embodiment
- FIG. 9 is a development of a sixth embodiment of the substrate of the semiconductor device to which the present invention is applied. This embodiment differs from the sixth embodiment in that a joining
member 620 is provided, spanning theslit 500 of thesubstrate 510 shown in FIG. 8. By the provision of the joiningmember 620, thesubstrate 510 which has been divided is joined and reinforced. Therefore, the width of aninterconnect pattern 612 may be less than the width of theinterconnect pattern 512 shown in FIG. 8. The joiningmember 620 may be formed of the same material as theinterconnect pattern 612. When theinterconnect pattern 612 is formed by etching of a metal foil such as copper foil, the joiningmember 620 may be formed at the same time, thus not requiring the number of processes to be increased. - To other aspects of the embodiment, the description under the sixth embodiment can be applied. In this embodiment, the joining member610 has been described spanning the
slit 500 separating thesubstrate 510, but the joining member 610 may equally span holes 400 (see FIG. 7) which do not separate thesubstrate 510.Such holes 400 may also be termed “slits.” - Eighth Embodiment
- FIG. 10 shows an eighth embodiment of the semiconductor device to which the present invention is applied. The semiconductor device shown in FIG. 10 has the same configuration as the
semiconductor device 5 shown in FIG. 5, except for asubstrate 710 andhole 700. - In the
substrate 710, in the region of bending, a plurality ofholes 700 is formed. The plurality ofholes 700 comprise slots extending along the bending line, in a in a parallel formation. Alternatively, theholes 700 may be termed “slits,” and in place of theholes 700, slits dividing thesubstrate 710 may be formed. By the formation of such holes (or slits) 700, thesubstrate 710 is made easier to bend. Theinterconnect pattern 312 passes over theholes 700. In this embodiment the description referring to FIG. 5 can also be applied. - Ninth Embodiment
- FIG. 11 shows a ninth embodiment of the semiconductor device to which the present invention is applied. In the semiconductor device shown in FIG. 11, with a
hole 800 formed in asubstrate 810 interposed, aflexible resin 820 is provided on theinterconnect pattern 312. As theresin 820 for example a soft polyimide resin may be used. - The
hole 800 is formed in the region where thesubstrate 810 is bent. Thehole 800 may be termed a “slit,” and in place of thehole 800, a slit dividing thesubstrate 810 may be formed. - In this embodiment, the
interconnect pattern 312 is formed on the inside of the bent portion of thesubstrate 810, and therefore without theresin 820, theinterconnect pattern 312 would be exposed to the exterior through thehole 800. But here the provision of theresin 820 within thehole 800 enables theinterconnect pattern 312 to be protected. Moreover, since theresin 820 is flexible, theresin 820 can be provided while thesubstrate 810 is still opened up in the flat state, and thesubstrate 810 bent thereafter, improving the working efficiency. It should be noted that the description of this embodiment can also be applied to the other embodiments. - The present invention can be applied to a face-down type of semiconductor device or to the module construction thereof. As a face-down type semiconductor device may be cited, for example, COF (Chip On Flex/Film) construction or COB (Chip On Board) construction.
- In these embodiments, a semiconductor device having external electrodes has been described, but a part of the substrate may be extended and used for external connection. A part of the substrate may be used as a connector lead, connectors may be mounted on the substrate, or the substrate interconnect pattern itself may be connected to another electronic instrument.
- Furthermore, the formation of external connectors may be eliminated, and using a solder cream applied on the motherboard at the time of mounting on the motherboard, external terminals may be formed as a result of surface tension during the fusion thereof. This semiconductor device is a so-called “land grid array” type of semiconductor device.
- In FIG. 12 shows a
circuit board 1000 on which the first embodiment of thesemiconductor device 1 is mounted. For thecircuit board 1000, an organic substrate such as a glass epoxy substrate or the like is generally used. On thecircuit board 1000, an interconnect pattern of for example copper is formed to constitute a desired circuit. Then by mechanical connection of corresponding parts of the interconnect pattern and external electrodes 40 (see FIG. 1B) of thesemiconductor device 1, electrical connection thereof is achieved. - It should be noted that the
semiconductor device 1 has a mounting area which can be made as small as the area for mounting a bare chip, and therefore by using thiscircuit board 1000 for an electronic instrument, the electronic instrument itself can be made more compact. Within the same area, a larger mounting space can be obtained, and therefore higher functionality is possible. - Then as an electronic instrument equipped with this
circuit board 1000, FIG. 13 shows a notebookpersonal computer 1100. - It should be noted that the above embodiments are examples of the present invention applied to a semiconductor device, but the present invention can be applied to any surface-mounted electronic component requiring a large number of external electrodes as in the case of a semiconductor device, whether an active component or passive component. As electronic components, for example, may be cited resistors, capacitors, coils, oscillators, filters, temperature sensors, thermistors, varistors, variable resistors, and fuses.
- In all of the above-described embodiments, as the method of mounting the semiconductor chip, face-down bonding is applied, but equally wire bonding, or TAB (Tape Automated Bonding), or similar mounting methods can be applied. A mounted module type of semiconductor device in which a combination of the above-described semiconductor chips and electronic components other than semiconductor chips is mounted may be configured.
Claims (21)
1. A semiconductor device comprising:
a plurality of semiconductor chips having electrodes, and aligned in a horizontal direction for face-down bonding;
a substrate on which an interconnect pattern is formed, the interconnect pattern having bonding portions to which the electrodes of the semiconductor chip are connected, and lands to which the bonding portions are electrically connected; and
external electrodes provided on the lands.
2. The semiconductor device as defined in claim 1 ,
wherein the external electrodes are disposed within mounting regions of the semiconductor chips.
3. The semiconductor device as defined in claim 1 ,
wherein the external electrodes are disposed outside regions where the semiconductor chips are mounted.
4. The semiconductor device as defined in claim 3 ,
wherein the substrate is a flexible substrate and is formed to be larger than the regions where the semiconductor chips are mounted, and a flat support member is provided on a periphery of the substrate.
5. The semiconductor device as defined in claim 1 ,
wherein the external electrodes are disposed within a region where any one of the semiconductor chips is mounted.
6. The semiconductor device as defined in claim 5 ,
wherein the substrate is a flexible substrate and part of the substrate is bent; and
wherein a surface of the one semiconductor chip, which is disposed at a region where the external electrodes are provided, opposite to a surface on which the electrodes are formed is adhered to a surface of at least one remaining semiconductor chip opposite to a surface on which the electrodes are formed.
7. The semiconductor device as defined in claim 6 ,
wherein the substrate has at least one hole formed along a region to be bent.
8. The semiconductor device as defined in claim 7 ,
wherein the hole is a slot extending along a bending line;
wherein the interconnect pattern is formed to pass over the hole; and
wherein an edge of the slot extending along the bending line forms a part of an outer edge.
9. The semiconductor device as defined in claim 7 ,
wherein a plurality of the holes are formed;
wherein the interconnect pattern is formed to pass over the plurality of holes; and
wherein the holes are slots extending along a bending line, and are aligned.
10. The semiconductor device as defined in claim 6 ,
wherein the substrate has a slit formed along a region to be bent; and
wherein the substrate is divided by the slit, and a gap is opened up between opposing divided edges.
11. The semiconductor device as defined in claim 10 ,
wherein a joining member is provided spanning the slit.
12. The semiconductor device as defined in claim 8 ,
wherein a flexible resin is provided on the interconnect pattern in the hole; and
wherein the resin is bent together with the substrate.
13. The semiconductor device as defined in claim 6 ,
wherein the semiconductor chips are adhered by an electrically conductive adhesive or a thermally conductive adhesive.
14. The semiconductor device as defined in claim 5 ,
wherein a surface area of one of the semiconductor chips is larger than a surface area of a remaining semiconductor chip; and
wherein the external electrodes are formed only in a region where the semiconductor chip having a larger surface area is provided.
15. The semiconductor device as defined in claim 1 ,
wherein the electrodes of the semiconductor chips are connected to the bonding portions by an anisotropically conductive material including conductive particles dispersed in an adhesive.
16. A method of manufacturing a semiconductor device, comprising:
a step of providing a substrate on which an interconnect pattern is formed, the interconnect pattern having a plurality of bonding portions and a plurality of lands electrically connected to the bonding portions, and providing a plurality of semiconductor chips having electrodes;
a step of providing anisotropically conductive materials including conductive particles dispersed in an adhesive at least on the bonding portions;
a step of positioning the electrodes over the bonding portions on the anisotropically conductive materials, and mounting the semiconductor chips over the substrate;
a step of applying pressure to at least one of the semiconductor chips and the substrate so that the bonding portions and the electrodes are electrically connected by the conductive particles; and
a step of forming external electrodes on the lands.
17. The method of manufacturing a semiconductor device as defined in claim 16 ,
wherein the substrate is a flexible substrate and is formed to be larger than the regions where the semiconductor chips are mounted; and
wherein a flat support member is provided on a periphery of the substrate.
18. The method of manufacturing a semiconductor device as defined in claim 16 , the method further comprising a step of bending a part of the substrate, after the step of mounting the semiconductor chips on the substrate, so that a surface of one of the semiconductor chips opposite to a surface where the electrodes are provided is adhered to a surface of another of the semiconductor chips opposite to a surface on which the electrodes are formed.
19. The method of manufacturing a semiconductor device as defined in claim 18 ,
wherein the substrate has at least one hole formed along a region to be bent.
20. A circuit board on which the semiconductor device as defined in any one of claims 1 to 15 is mounted.
21. An electronic instrument on which the circuit board as defined in claim 20 is mounted.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US10/267,641 US20030030137A1 (en) | 1998-09-09 | 2002-10-10 | Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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JP27261398 | 1998-09-09 | ||
JP10-272613 | 1998-09-09 | ||
US09/530,609 US6486544B1 (en) | 1998-09-09 | 1999-09-03 | Semiconductor device and method manufacturing the same, circuit board, and electronic instrument |
US10/267,641 US20030030137A1 (en) | 1998-09-09 | 2002-10-10 | Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument |
Related Parent Applications (1)
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US09/530,609 Continuation US6486544B1 (en) | 1998-09-09 | 1999-09-03 | Semiconductor device and method manufacturing the same, circuit board, and electronic instrument |
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US10/267,641 Abandoned US20030030137A1 (en) | 1998-09-09 | 2002-10-10 | Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument |
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US09/530,609 Expired - Fee Related US6486544B1 (en) | 1998-09-09 | 1999-09-03 | Semiconductor device and method manufacturing the same, circuit board, and electronic instrument |
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US (2) | US6486544B1 (en) |
EP (1) | EP1041633B1 (en) |
KR (1) | KR100514558B1 (en) |
CN (1) | CN1229863C (en) |
DE (1) | DE69938582T2 (en) |
TW (1) | TW563213B (en) |
WO (1) | WO2000014802A1 (en) |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010018225A1 (en) * | 2000-02-22 | 2001-08-30 | Hideki Tanaka | Tape carrier type semiconductor device, method for manufacturing the same, and flexible substrate |
US20030214034A1 (en) * | 2002-05-17 | 2003-11-20 | Hirofumi Abe | Semiconductor device having bump electrode |
US20060148231A1 (en) * | 2005-01-06 | 2006-07-06 | Kai-Kuang Ho | Integrated die bumping process |
US20090102062A1 (en) * | 2007-10-22 | 2009-04-23 | Shinko Electric Industries Co., Ltd. | Wiring substrate and method of manufacturing the same, and semiconductor device |
US20100289132A1 (en) * | 2009-05-13 | 2010-11-18 | Shih-Fu Huang | Substrate having embedded single patterned metal layer, and package applied with the same, and methods of manufacturing of the substrate and package |
US20100288541A1 (en) * | 2009-05-13 | 2010-11-18 | Advanced Semiconductor Engineering, Inc. | Substrate having single patterned metal layer, and package applied with the substrate , and methods of manufacturing of the substrate and package |
US20100314744A1 (en) * | 2009-05-13 | 2010-12-16 | Shih-Fu Huang | Substrate having single patterned metal layer exposing patterned dielectric layer, chip package structure including the substrate, and manufacturing methods thereof |
US20110057301A1 (en) * | 2009-09-08 | 2011-03-10 | Advanced Semiconductor Engineering, Inc. | Semiconductor package |
US20110084372A1 (en) * | 2009-10-14 | 2011-04-14 | Advanced Semiconductor Engineering, Inc. | Package carrier, semiconductor package, and process for fabricating same |
US20110084370A1 (en) * | 2009-10-14 | 2011-04-14 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and process for fabricating same |
US20110169150A1 (en) * | 2010-01-13 | 2011-07-14 | Advanced Semiconductor Engineering, Inc. | Semiconductor Package with Single Sided Substrate Design and Manufacturing Methods Thereof |
US20140291701A1 (en) * | 2012-03-05 | 2014-10-02 | Mitsubishi Electric Corporation | Semiconductor device |
US9349611B2 (en) | 2010-03-22 | 2016-05-24 | Advanced Semiconductor Engineering, Inc. | Stackable semiconductor package and manufacturing method thereof |
Families Citing this family (65)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
AU6349000A (en) * | 1999-07-16 | 2001-02-05 | Silicon Film Technologies, Inc. | High-density packaging of integrated circuits |
KR100530911B1 (en) | 1999-10-01 | 2005-11-23 | 세이코 엡슨 가부시키가이샤 | Wiring board, semiconductor device and method of producing, testing and packaging the same, and circuit board and electronic equipment |
JP3405456B2 (en) * | 2000-09-11 | 2003-05-12 | 沖電気工業株式会社 | Semiconductor device, method of manufacturing semiconductor device, stack type semiconductor device, and method of manufacturing stack type semiconductor device |
US20020121693A1 (en) | 2000-12-11 | 2002-09-05 | Milla Juan G. | Stacked die package |
JP2002237568A (en) * | 2000-12-28 | 2002-08-23 | Texas Instr Inc <Ti> | Chip-scale package stacked on interconnect body folded for vertical assembly on substrate |
US7115986B2 (en) * | 2001-05-02 | 2006-10-03 | Micron Technology, Inc. | Flexible ball grid array chip scale packages |
US6882046B2 (en) * | 2001-07-09 | 2005-04-19 | Koninklijke Phillips Electronics N.V. | Single package containing multiple integrated circuit devices |
JP3983120B2 (en) * | 2001-07-30 | 2007-09-26 | 富士通日立プラズマディスプレイ株式会社 | IC chip mounting structure and display device |
US7026708B2 (en) * | 2001-10-26 | 2006-04-11 | Staktek Group L.P. | Low profile chip scale stacking system and method |
US6576992B1 (en) * | 2001-10-26 | 2003-06-10 | Staktek Group L.P. | Chip scale stacking system and method |
US7485951B2 (en) * | 2001-10-26 | 2009-02-03 | Entorian Technologies, Lp | Modularized die stacking system and method |
US7656678B2 (en) | 2001-10-26 | 2010-02-02 | Entorian Technologies, Lp | Stacked module systems |
US6914324B2 (en) * | 2001-10-26 | 2005-07-05 | Staktek Group L.P. | Memory expansion and chip scale stacking system and method |
US20030234443A1 (en) * | 2001-10-26 | 2003-12-25 | Staktek Group, L.P. | Low profile stacking system and method |
US6956284B2 (en) * | 2001-10-26 | 2005-10-18 | Staktek Group L.P. | Integrated circuit stacking system and method |
US6940729B2 (en) * | 2001-10-26 | 2005-09-06 | Staktek Group L.P. | Integrated circuit stacking system and method |
US20060255446A1 (en) | 2001-10-26 | 2006-11-16 | Staktek Group, L.P. | Stacked modules and method |
US6867501B2 (en) * | 2001-11-01 | 2005-03-15 | Rohm Co., Ltd. | Semiconductor device and method for manufacturing same |
US7154171B1 (en) * | 2002-02-22 | 2006-12-26 | Amkor Technology, Inc. | Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor |
SG121707A1 (en) | 2002-03-04 | 2006-05-26 | Micron Technology Inc | Method and apparatus for flip-chip packaging providing testing capability |
SG111935A1 (en) | 2002-03-04 | 2005-06-29 | Micron Technology Inc | Interposer configured to reduce the profiles of semiconductor device assemblies and packages including the same and methods |
KR100460062B1 (en) * | 2002-04-23 | 2004-12-04 | 주식회사 하이닉스반도체 | Multi chip package and manufacturing method thereof |
US6900536B1 (en) * | 2002-04-26 | 2005-05-31 | Celis Semiconductor Corporation | Method for producing an electrical circuit |
US6600222B1 (en) * | 2002-07-17 | 2003-07-29 | Intel Corporation | Stacked microelectronic packages |
JP3867785B2 (en) * | 2002-10-15 | 2007-01-10 | セイコーエプソン株式会社 | Optical module |
US6731000B1 (en) * | 2002-11-12 | 2004-05-04 | Koninklijke Philips Electronics N.V. | Folded-flex bondwire-less multichip power package |
US7327022B2 (en) * | 2002-12-30 | 2008-02-05 | General Electric Company | Assembly, contact and coupling interconnection for optoelectronics |
DE10319509A1 (en) * | 2003-03-03 | 2004-09-23 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Circuit module and production process for semiconductor elements especially for solar cells and clothing has carrier which can bend flexibly between the cells |
US6924551B2 (en) * | 2003-05-28 | 2005-08-02 | Intel Corporation | Through silicon via, folded flex microelectronic package |
US7057116B2 (en) * | 2003-06-02 | 2006-06-06 | Intel Corporation | Selective reference plane bridge(s) on folded package |
US6991961B2 (en) | 2003-06-18 | 2006-01-31 | Medtronic, Inc. | Method of forming a high-voltage/high-power die package |
DE10332303A1 (en) * | 2003-07-16 | 2005-02-17 | Robert Bosch Gmbh | Components retainer/holder especially for micro-electronic circuits and micro-mechanical components e.g. revs sensor, has slightly deformable zone and badly deformable zone |
KR100699823B1 (en) * | 2003-08-05 | 2007-03-27 | 삼성전자주식회사 | Low cost type flexible film package module and method for fabricating thereof |
JP3867796B2 (en) * | 2003-10-09 | 2007-01-10 | セイコーエプソン株式会社 | Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus |
FR2861895B1 (en) * | 2003-11-03 | 2006-02-24 | Commissariat Energie Atomique | METHOD AND DEVICE FOR CONNECTING CHIPS |
JP2005150154A (en) * | 2003-11-11 | 2005-06-09 | Sharp Corp | Semiconductor module and its mounting method |
US20050230821A1 (en) * | 2004-04-15 | 2005-10-20 | Kheng Lee T | Semiconductor packages, and methods of forming semiconductor packages |
US7679591B2 (en) * | 2004-07-09 | 2010-03-16 | Au Optronics Corporation | Light emitting display device |
US7443023B2 (en) | 2004-09-03 | 2008-10-28 | Entorian Technologies, Lp | High capacity thin module system |
US7423885B2 (en) | 2004-09-03 | 2008-09-09 | Entorian Technologies, Lp | Die module system |
US7760513B2 (en) | 2004-09-03 | 2010-07-20 | Entorian Technologies Lp | Modified core for circuit module system and method |
US8072058B2 (en) * | 2004-10-25 | 2011-12-06 | Amkor Technology, Inc. | Semiconductor package having a plurality input/output members |
JP4251129B2 (en) * | 2004-10-25 | 2009-04-08 | セイコーエプソン株式会社 | Mounting structure, electro-optical device, and electronic apparatus |
US7709943B2 (en) | 2005-02-14 | 2010-05-04 | Daniel Michaels | Stacked ball grid array package module utilizing one or more interposer layers |
US20080203552A1 (en) * | 2005-02-15 | 2008-08-28 | Unisemicon Co., Ltd. | Stacked Package and Method of Fabricating the Same |
US20100020515A1 (en) * | 2005-03-08 | 2010-01-28 | Smart Modular Technologies, Inc. | Method and system for manufacturing micro solid state drive devices |
US7767543B2 (en) * | 2005-09-06 | 2010-08-03 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing a micro-electro-mechanical device with a folded substrate |
US20070096333A1 (en) * | 2005-10-31 | 2007-05-03 | Amir Motamedi | Optimal stacked die organization |
US7888185B2 (en) | 2006-08-17 | 2011-02-15 | Micron Technology, Inc. | Semiconductor device assemblies and systems including at least one conductive pathway extending around a side of at least one semiconductor device |
US7425758B2 (en) * | 2006-08-28 | 2008-09-16 | Micron Technology, Inc. | Metal core foldover package structures |
US7417310B2 (en) | 2006-11-02 | 2008-08-26 | Entorian Technologies, Lp | Circuit module having force resistant construction |
US8018042B2 (en) * | 2007-03-23 | 2011-09-13 | Microsemi Corporation | Integrated circuit with flexible planar leads |
US8058719B2 (en) * | 2007-03-23 | 2011-11-15 | Microsemi Corporation | Integrated circuit with flexible planer leads |
KR100885976B1 (en) * | 2007-06-25 | 2009-03-03 | 삼성전자주식회사 | Printed circuit board, memory module having the same and fabrication method thereof |
EP2353179A4 (en) * | 2008-10-17 | 2012-10-03 | Occam Portfolio Llc | Flexible circuit assemblies without solder and methods for their manufacture |
KR101047139B1 (en) * | 2009-11-11 | 2011-07-07 | 삼성전기주식회사 | Single Layer Board-on-Chip Package Substrate and Manufacturing Method Thereof |
JP6150375B2 (en) * | 2012-12-06 | 2017-06-21 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
US9543197B2 (en) | 2012-12-19 | 2017-01-10 | Intel Corporation | Package with dielectric or anisotropic conductive (ACF) buildup layer |
KR102066087B1 (en) | 2013-05-28 | 2020-01-15 | 엘지디스플레이 주식회사 | Flexible display device and manufacturing method of the same |
DE102015219190A1 (en) * | 2015-10-05 | 2017-04-06 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Method for producing an electronic component and electronic component |
US11164861B2 (en) | 2017-12-20 | 2021-11-02 | King Abdullah University Of Science And Technology | Monolithic electronic device and method of manufacture |
CN208077535U (en) * | 2018-04-28 | 2018-11-09 | 京东方科技集团股份有限公司 | A kind of flexible display panels and flexible display apparatus |
CN108766246A (en) * | 2018-07-18 | 2018-11-06 | 昆山国显光电有限公司 | Display panel and display device |
KR102196447B1 (en) * | 2020-01-08 | 2020-12-29 | 엘지디스플레이 주식회사 | Flexible display device and manufacturing method of the same |
KR102339385B1 (en) * | 2020-01-08 | 2021-12-15 | 엘지디스플레이 주식회사 | Flexible display device and manufacturing method of the same |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4922376A (en) * | 1989-04-10 | 1990-05-01 | Unistructure, Inc. | Spring grid array interconnection for active microelectronic elements |
US5220198A (en) * | 1990-08-27 | 1993-06-15 | Olympus Optical Co., Ltd. | Solid state imaging apparatus in which a solid state imaging device chip and substrate are face-bonded with each other |
US5463253A (en) * | 1990-03-15 | 1995-10-31 | Fujitsu Limited | Semiconductor device having a plurality of chips |
US5646446A (en) * | 1995-12-22 | 1997-07-08 | Fairchild Space And Defense Corporation | Three-dimensional flexible assembly of integrated circuits |
US6028365A (en) * | 1998-03-30 | 2000-02-22 | Micron Technology, Inc. | Integrated circuit package and method of fabrication |
US6108210A (en) * | 1998-04-24 | 2000-08-22 | Amerasia International Technology, Inc. | Flip chip devices with flexible conductive adhesive |
US6121676A (en) * | 1996-12-13 | 2000-09-19 | Tessera, Inc. | Stacked microelectronic assembly and method therefor |
US6208521B1 (en) * | 1997-05-19 | 2001-03-27 | Nitto Denko Corporation | Film carrier and laminate type mounting structure using same |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5159535A (en) | 1987-03-11 | 1992-10-27 | International Business Machines Corporation | Method and apparatus for mounting a flexible film semiconductor chip carrier on a circuitized substrate |
JP2751518B2 (en) * | 1990-01-25 | 1998-05-18 | 日本電気株式会社 | Semiconductor element mounting method |
US5065227A (en) * | 1990-06-04 | 1991-11-12 | International Business Machines Corporation | Integrated circuit packaging using flexible substrate |
JP2857492B2 (en) | 1990-11-28 | 1999-02-17 | シャープ株式会社 | TAB package |
KR100280762B1 (en) | 1992-11-03 | 2001-03-02 | 비센트 비.인그라시아 | Thermally Reinforced Semiconductor Devices Having Exposed Backsides and Methods of Manufacturing the Same |
JPH07169872A (en) | 1993-12-13 | 1995-07-04 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
JPH07302858A (en) | 1994-04-28 | 1995-11-14 | Toshiba Corp | Semiconductor package |
JP3400877B2 (en) * | 1994-12-14 | 2003-04-28 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
JPH08186336A (en) | 1994-12-28 | 1996-07-16 | Mitsubishi Electric Corp | Circuit board, drive circuit module and liquid crystal device using it as well as their manufacture |
US5783870A (en) * | 1995-03-16 | 1998-07-21 | National Semiconductor Corporation | Method for connecting packages of a stacked ball grid array structure |
JPH08321580A (en) * | 1995-05-25 | 1996-12-03 | Rohm Co Ltd | Structure and manufacture fo hybrid integrated circuit device |
JP3688755B2 (en) * | 1995-06-12 | 2005-08-31 | 株式会社日立製作所 | Electronic components and electronic component modules |
EP0774888B1 (en) * | 1995-11-16 | 2003-03-19 | Matsushita Electric Industrial Co., Ltd | Printed wiring board and assembly of the same |
JP3465809B2 (en) * | 1996-07-31 | 2003-11-10 | ソニー株式会社 | Semiconductor device and manufacturing method thereof |
JPH10242379A (en) | 1997-02-25 | 1998-09-11 | Hitachi Ltd | Semiconductor module |
JPH10270624A (en) * | 1997-03-27 | 1998-10-09 | Toshiba Corp | Chip-size package and manufacture thereof |
US6075287A (en) * | 1997-04-03 | 2000-06-13 | International Business Machines Corporation | Integrated, multi-chip, thermally conductive packaging device and methodology |
JP3490601B2 (en) | 1997-05-19 | 2004-01-26 | 日東電工株式会社 | Film carrier and laminated mounting body using the same |
-
1999
- 1999-09-03 EP EP99940645A patent/EP1041633B1/en not_active Expired - Lifetime
- 1999-09-03 CN CNB998015601A patent/CN1229863C/en not_active Expired - Fee Related
- 1999-09-03 DE DE69938582T patent/DE69938582T2/en not_active Expired - Lifetime
- 1999-09-03 KR KR10-2000-7004842A patent/KR100514558B1/en not_active IP Right Cessation
- 1999-09-03 WO PCT/JP1999/004785 patent/WO2000014802A1/en active IP Right Grant
- 1999-09-03 US US09/530,609 patent/US6486544B1/en not_active Expired - Fee Related
- 1999-09-07 TW TW088115417A patent/TW563213B/en not_active IP Right Cessation
-
2002
- 2002-10-10 US US10/267,641 patent/US20030030137A1/en not_active Abandoned
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4922376A (en) * | 1989-04-10 | 1990-05-01 | Unistructure, Inc. | Spring grid array interconnection for active microelectronic elements |
US5463253A (en) * | 1990-03-15 | 1995-10-31 | Fujitsu Limited | Semiconductor device having a plurality of chips |
US5220198A (en) * | 1990-08-27 | 1993-06-15 | Olympus Optical Co., Ltd. | Solid state imaging apparatus in which a solid state imaging device chip and substrate are face-bonded with each other |
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Also Published As
Publication number | Publication date |
---|---|
KR100514558B1 (en) | 2005-09-13 |
KR20010031776A (en) | 2001-04-16 |
WO2000014802A1 (en) | 2000-03-16 |
DE69938582T2 (en) | 2009-06-04 |
CN1229863C (en) | 2005-11-30 |
EP1041633B1 (en) | 2008-04-23 |
CN1277737A (en) | 2000-12-20 |
EP1041633A4 (en) | 2001-10-31 |
TW563213B (en) | 2003-11-21 |
US6486544B1 (en) | 2002-11-26 |
EP1041633A1 (en) | 2000-10-04 |
DE69938582D1 (en) | 2008-06-05 |
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