US20020072148A1 - Method for mounting a semiconductor chip on a substrate, and semiconductor device adapted for mounting on a substrate - Google Patents
Method for mounting a semiconductor chip on a substrate, and semiconductor device adapted for mounting on a substrate Download PDFInfo
- Publication number
- US20020072148A1 US20020072148A1 US09/792,003 US79200301A US2002072148A1 US 20020072148 A1 US20020072148 A1 US 20020072148A1 US 79200301 A US79200301 A US 79200301A US 2002072148 A1 US2002072148 A1 US 2002072148A1
- Authority
- US
- United States
- Prior art keywords
- bonding pads
- pad
- mounting
- substrate
- conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/5328—Conductive materials containing conductive organic materials or pastes, e.g. conductive adhesives, inks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05023—Disposition the whole internal layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05024—Disposition the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
- H01L2224/13008—Bump connector integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01027—Cobalt [Co]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01068—Erbium [Er]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Definitions
- This invention relates to a method for mounting a semiconductor chip on a substrate and to a semiconductor device that is adapted for mounting on a substrate.
- the applicant disclosed a method for mounting a semiconductor chip on a substrate to prepare a semiconductor device.
- the substrate has a chip-mounting region provided with a plurality of solder points.
- the semiconductor chip has a pad-mounting surface provided with a plurality of bonding pads, which are to be connected to corresponding ones of the solder points and which are disposed on the pad-mounting surface at locations that are offset from locations of the corresponding ones of the solder points on the chip-mounting region.
- the method involves the steps of forming a photoresist layer on the pad-mounting surface with a plurality of contact receiving cavities, each of which is registered with and exposes a portion of one of the bonding pads on the pad-mounting surface, and forming a plurality of conductive bodies, each of which is electrically connected to one of the bonding pads, and each of which has an anchor portion filling one of the contact receiving cavities and connected to the respective bonding pad, an extension portion extending from the anchor portion and formed on the surface of the photoresist layer, and a contact portion protruding from one end of the extension portion and formed on the surface of the photoresist layer opposite to the anchor portion.
- the contact portion is disposed at the position corresponding to a respective one of the solder points on the chip-mounting region of the substrate.
- the main object of the present invention is to provide a method of the type similar to that disclosed in the aforesaid co-pending U.S. patent application Ser. No. 09/688,855, for mounting a semiconductor chip on a substrate so as to overcome the aforesaid drawback.
- Another object of the present invention is to provide a semiconductor device of the type similar to that disclosed in the aforesaid co-pending U.S. patent application Ser. No. 09/688,855 that is capable of overcoming the aforesaid drawback.
- the semiconductor chip has a pad-mounting surface provided with a plurality of bonding pads, which are to be connected to corresponding ones of the solder points and which are disposed on the pad-mounting surface at locations that are offset from locations of the corresponding ones of the solder points on the chip-mounting region.
- the method comprises the steps of: attaching a printed circuit sheet to the pad-mounting surface, wherein the bonding pads are exposed from the printed circuit sheet, the printed circuit sheet including a non-conductive substrate with a printed surface that is opposite to the pad-mounting surface and that is printed with a plurality of conductive traces which are to be respectively and electrically connected with the bonding pads and which are respectively spaced apart from the bonding pads in lateral directions along the printed surface; forming a plurality of conductive bonding wires that respectively interconnect the bonding pads and the conductive traces; forming a photoresist layer on the printed surface and the pad-mounting surface such that the bonding pads and the bonding wires are embedded in the photoresist layer; forming access holes in the photoresist layer, each of which is registered with and exposes at least a portion of a respective one of the conductive traces; and forming a plurality of conductive bodies in the access holes, wherein each of the conductive bodies is electrically connected to a respective one of the
- a semiconductor device is adapted for mounting on a substrate having a chip-mounting region provided with a plurality of solder points.
- the semiconductor device comprises: a semiconductor chip having a pad-mounting surface provided with a plurality of bonding pads which are disposed on the pad-mounting surface at locations that are offset from locations of corresponding ones of the solder points on the chip-mounting region; a printed circuit sheet attached to the pad-mounting surface and including a non-conductive substrate with a printed surface that is opposite to the pad-mounting surface and that is printed with a plurality of conductive traces which are respectively spaced apart from the bonding pads in lateral directions along the printed surface; a plurality of conductive bonding wires that respectively interconnect the bonding pads and the conductive traces; a photoresist layer overlaid on the printed surface and the pad-mounting surface such that the bonding pads and the bonding wires are embedded in the photoresist layer, and formed with a plurality of access
- FIG. 1 is a fragmentary perspective view to illustrate a semiconductor chip connected to a printed circuit sheet via conductive bonding wires according to the method of this invention
- FIG. 2 is a cross-sectional view of an assembly of the printed circuit sheet, the bonding wire, and the semiconductor chip of FIG. 1;
- FIG. 3 illustrates a photoresist layer and a mask used in a photolithography process for the assembly of FIG. 2 according to the method of this invention
- FIG. 4 illustrates an access hole formed in the photoresist layer of FIG. 3 and a conductive body formed in the access hole according to the method of this invention
- FIG. 5 illustrates an assembly of the photoresist layer, the conductive body, the printed circuit sheet, the bonding wire, and the semiconductor chip of FIG. 4;
- FIGS. 6 and 7 illustrate different configurations of assemblies of the photoresist layer, the conductive bodies, the printed circuit sheet, the bonding wires, and the semiconductor chip that are modified from FIG. 5 according to different layouts of the bonding pads.
- FIG. 5 illustrates a semiconductor chip 1 to be mounted on a substrate 9 according to the method of this invention.
- the substrate 9 has a chip-mounting region provided with a plurality of solder points 90 .
- the semiconductor chip 1 has a pad-mounting surface 10 provided with a plurality of bonding pads 11 (see FIG. 1) , which are to be connected to corresponding ones of the solder points 90 and which are disposed on the pad-mounting surface 10 at locations that are offset from locations of the corresponding ones of the solder points 90 on the chip-mounting region of the substrate 9 .
- the bonding pads 11 are aligned along a center line of the pad-mounting surface 10 .
- FIGS. 1 to 5 illustrate consecutive steps for processing the semiconductor chip 1 to form a semiconductor device that is to be mounted on the substrate 9 according to the method of this invention.
- a printed circuit sheet 2 is attached to the pad-mounting surface 10 such that a portion of the pad-mounting surface 10 with the bonding pads 11 is exposed from the printed circuit sheet 2 .
- the printed circuit sheet 2 includes a non-conductive substrate 21 with a printed surface 20 that is opposite to the pad-mounting surface 10 and that is printed with a plurality of spaced apart conductive traces 21 which are to be respectively and electrically connected to the bonding pads 11 and which are respectively spaced apart from the bonding pads 11 in lateral directions along the printed surface 20 .
- a plurality of conductive bonding wires 22 are formed via known wire bonding techniques to respectively interconnect the bonding pads 11 and the conductive traces 21 .
- a light-curable layer such as a photoresist layer 3 is formed on the printed surface 20 and the pad-mounting surface 10 such that the bonding pads 11 and the bonding wires 22 are embedded in the photoresist layer 3 .
- a mask 4 is superimposed on the photoresist layer 3 , and the photoresist layer 3 is exposed at positions that are offset from contact portions 211 of the conductive traces 21 .
- the exposed portion of the photoresist layer 3 hardens, and forms an insulative isolating layer that covers the printed surface 20 and the pad-mounting surface 10 .
- a plurality of access holes 30 are formed in the photoresist layer 3 by removing the unexposed portion of the photoresist layer 3 from the isolating layer via solvent washing.
- Each of the access holes 30 exposes the contact portion 211 of a respective one of the conductive traces 21 .
- the contact portion 211 of each of the conductive traces 21 is registered with a respective one of the solder points 90 of the substrate 9 (see FIG. 5).
- a plurality of conductive bodies 5 are respectively formed in the access holes 30 (only one is shown in FIG. 5). Each of the conductive bodies 5 is electrically connected to a respective one of the bonding pads 11 , and protrudes from a respective one of the access holes 30 so as to permit electrical connection with the corresponding solder point 90 of the substrate 9 (see FIG. 5).
- FIGS. 6 and 7 illustrate different configurations of assemblies of the photoresist layer 3 , the conductive bodies 5 , the printed circuit sheet 2 , the bonding wires 22 , and the semiconductor chip 1 that are modified from FIG. 5 according to different layouts of the bonding pads 11 .
- the bonding pads 11 are formed on a peripheral portion of the pad-mounting surface 10 of the semiconductor chip 1 .
- the bonding pads 11 are formed into two parallel rows along a center portion of the pad-mounting surface 10 of the semiconductor chip 1 .
Abstract
A method for manufacturing a semiconductor device includes the steps of providing a semiconductor chip having a pad-mounting surface with bonding pads, attaching a printed circuit sheet to the pad-mounting surface, forming conductive bonding wires that respectively interconnect the bonding pads and conductive traces on the printed circuit sheet, forming a photoresist layer on the printed surface and the pad-mounting surface, forming access holes in the photoresist layer to expose portions of the conductive traces that are respectively offset from the bonding pads, and forming a plurality of conductive bodies in the access holes such that each of the conductive bodies is electrically connected to a respective one of the bonding pads.
Description
- This application is related to a co-pending U.S. patent application Ser. No. 09/688,855 filed by the applicant on Oct. 16, 2000, the entire disclosure of which is incorporated herein by reference.
- 1. Field of the invention
- This invention relates to a method for mounting a semiconductor chip on a substrate and to a semiconductor device that is adapted for mounting on a substrate.
- 2. Description of the Related Art
- With the rapid advancement in semiconductor fabrication technology, the bonding pads on the surface of a semiconductor chip are getting smaller in size, and the distances between adjacent bonding pads are getting shorter. These can create difficulty when connecting the semiconductor chip to an external circuit, and can affect adversely the production yield.
- In co-pending U.S. patent application Ser. No. 09/688,855, the applicant disclosed a method for mounting a semiconductor chip on a substrate to prepare a semiconductor device. The substrate has a chip-mounting region provided with a plurality of solder points. The semiconductor chip has a pad-mounting surface provided with a plurality of bonding pads, which are to be connected to corresponding ones of the solder points and which are disposed on the pad-mounting surface at locations that are offset from locations of the corresponding ones of the solder points on the chip-mounting region. The method involves the steps of forming a photoresist layer on the pad-mounting surface with a plurality of contact receiving cavities, each of which is registered with and exposes a portion of one of the bonding pads on the pad-mounting surface, and forming a plurality of conductive bodies, each of which is electrically connected to one of the bonding pads, and each of which has an anchor portion filling one of the contact receiving cavities and connected to the respective bonding pad, an extension portion extending from the anchor portion and formed on the surface of the photoresist layer, and a contact portion protruding from one end of the extension portion and formed on the surface of the photoresist layer opposite to the anchor portion. The contact portion is disposed at the position corresponding to a respective one of the solder points on the chip-mounting region of the substrate.
- The main object of the present invention is to provide a method of the type similar to that disclosed in the aforesaid co-pending U.S. patent application Ser. No. 09/688,855, for mounting a semiconductor chip on a substrate so as to overcome the aforesaid drawback.
- Another object of the present invention is to provide a semiconductor device of the type similar to that disclosed in the aforesaid co-pending U.S. patent application Ser. No. 09/688,855 that is capable of overcoming the aforesaid drawback.
- According to one aspect of the present invention, there is provided a method for mounting a semiconductor chip on a substrate having a chip-mounting region provided with a plurality of solder points. The semiconductor chip has a pad-mounting surface provided with a plurality of bonding pads, which are to be connected to corresponding ones of the solder points and which are disposed on the pad-mounting surface at locations that are offset from locations of the corresponding ones of the solder points on the chip-mounting region. The method comprises the steps of: attaching a printed circuit sheet to the pad-mounting surface, wherein the bonding pads are exposed from the printed circuit sheet, the printed circuit sheet including a non-conductive substrate with a printed surface that is opposite to the pad-mounting surface and that is printed with a plurality of conductive traces which are to be respectively and electrically connected with the bonding pads and which are respectively spaced apart from the bonding pads in lateral directions along the printed surface; forming a plurality of conductive bonding wires that respectively interconnect the bonding pads and the conductive traces; forming a photoresist layer on the printed surface and the pad-mounting surface such that the bonding pads and the bonding wires are embedded in the photoresist layer; forming access holes in the photoresist layer, each of which is registered with and exposes at least a portion of a respective one of the conductive traces; and forming a plurality of conductive bodies in the access holes, wherein each of the conductive bodies is electrically connected to a respective one of the bonding pads
- According to another aspect of the present invention, a semiconductor device is adapted for mounting on a substrate having a chip-mounting region provided with a plurality of solder points. The semiconductor device comprises: a semiconductor chip having a pad-mounting surface provided with a plurality of bonding pads which are disposed on the pad-mounting surface at locations that are offset from locations of corresponding ones of the solder points on the chip-mounting region; a printed circuit sheet attached to the pad-mounting surface and including a non-conductive substrate with a printed surface that is opposite to the pad-mounting surface and that is printed with a plurality of conductive traces which are respectively spaced apart from the bonding pads in lateral directions along the printed surface; a plurality of conductive bonding wires that respectively interconnect the bonding pads and the conductive traces; a photoresist layer overlaid on the printed surface and the pad-mounting surface such that the bonding pads and the bonding wires are embedded in the photoresist layer, and formed with a plurality of access holes, each of which is registered with and exposes at least a portion of a respective one of the conductive traces; and a plurality of conductive bodies respectively disposed in the access holes, and connected electrically and respectively to the bonding pads.
- In drawings which illustrate an embodiment of the invention,
- FIG. 1 is a fragmentary perspective view to illustrate a semiconductor chip connected to a printed circuit sheet via conductive bonding wires according to the method of this invention;
- FIG. 2 is a cross-sectional view of an assembly of the printed circuit sheet, the bonding wire, and the semiconductor chip of FIG. 1;
- FIG. 3 illustrates a photoresist layer and a mask used in a photolithography process for the assembly of FIG. 2 according to the method of this invention;
- FIG. 4 illustrates an access hole formed in the photoresist layer of FIG. 3 and a conductive body formed in the access hole according to the method of this invention;
- FIG. 5 illustrates an assembly of the photoresist layer, the conductive body, the printed circuit sheet, the bonding wire, and the semiconductor chip of FIG. 4; and
- FIGS. 6 and 7 illustrate different configurations of assemblies of the photoresist layer, the conductive bodies, the printed circuit sheet, the bonding wires, and the semiconductor chip that are modified from FIG. 5 according to different layouts of the bonding pads.
- FIG. 5 illustrates a
semiconductor chip 1 to be mounted on asubstrate 9 according to the method of this invention. Thesubstrate 9 has a chip-mounting region provided with a plurality ofsolder points 90. Thesemiconductor chip 1 has a pad-mounting surface 10 provided with a plurality of bonding pads 11 (see FIG. 1) , which are to be connected to corresponding ones of thesolder points 90 and which are disposed on the pad-mounting surface 10 at locations that are offset from locations of the corresponding ones of thesolder points 90 on the chip-mounting region of thesubstrate 9. Thebonding pads 11 are aligned along a center line of the pad-mountingsurface 10. - FIGS.1 to 5 illustrate consecutive steps for processing the
semiconductor chip 1 to form a semiconductor device that is to be mounted on thesubstrate 9 according to the method of this invention. - In FIGS. 1 and 2, a printed
circuit sheet 2 is attached to the pad-mounting surface 10 such that a portion of the pad-mounting surface 10 with thebonding pads 11 is exposed from the printedcircuit sheet 2. The printedcircuit sheet 2 includes anon-conductive substrate 21 with a printedsurface 20 that is opposite to the pad-mounting surface 10 and that is printed with a plurality of spaced apartconductive traces 21 which are to be respectively and electrically connected to thebonding pads 11 and which are respectively spaced apart from thebonding pads 11 in lateral directions along the printedsurface 20. - A plurality of
conductive bonding wires 22 are formed via known wire bonding techniques to respectively interconnect thebonding pads 11 and theconductive traces 21. - In FIG. 3, a light-curable layer, such as a
photoresist layer 3 is formed on the printedsurface 20 and the pad-mounting surface 10 such that thebonding pads 11 and thebonding wires 22 are embedded in thephotoresist layer 3. A mask 4 is superimposed on thephotoresist layer 3, and thephotoresist layer 3 is exposed at positions that are offset fromcontact portions 211 of theconductive traces 21. The exposed portion of thephotoresist layer 3 hardens, and forms an insulative isolating layer that covers the printedsurface 20 and the pad-mounting surface 10. - In FIG. 4, a plurality of access holes30 (only one is shown) are formed in the
photoresist layer 3 by removing the unexposed portion of thephotoresist layer 3 from the isolating layer via solvent washing. Each of theaccess holes 30 exposes thecontact portion 211 of a respective one of theconductive traces 21. Preferably, thecontact portion 211 of each of theconductive traces 21 is registered with a respective one of thesolder points 90 of the substrate 9 (see FIG. 5). - A plurality of
conductive bodies 5 are respectively formed in the access holes 30 (only one is shown in FIG. 5). Each of theconductive bodies 5 is electrically connected to a respective one of thebonding pads 11, and protrudes from a respective one of theaccess holes 30 so as to permit electrical connection with thecorresponding solder point 90 of the substrate 9 (see FIG. 5). - FIGS. 6 and 7 illustrate different configurations of assemblies of the
photoresist layer 3, theconductive bodies 5, the printedcircuit sheet 2, thebonding wires 22, and thesemiconductor chip 1 that are modified from FIG. 5 according to different layouts of thebonding pads 11. In FIG. 6, thebonding pads 11 are formed on a peripheral portion of the pad-mountingsurface 10 of thesemiconductor chip 1. In FIG. 7, thebonding pads 11 are formed into two parallel rows along a center portion of the pad-mountingsurface 10 of thesemiconductor chip 1. - With the printed
circuit sheet 2, the bonding wires, and theconductive bodies 5, the electrical connection between thesemiconductor chip 1 and thesubstrate 9 can be easily and flexibly achieved. - With the invention thus explained, it is apparent that various modifications and variations can be made without departing from the spirit of the present invention. It is therefore intended that the invention be limited only as recited in the appended claims.
Claims (4)
1. A method for mounting a semiconductor chip on a substrate, the substrate having a chip-mounting region provided with a plurality of solder points, the semiconductor chip having a pad-mounting surface provided with a plurality of bonding pads, which are to be connected to corresponding ones of the solder points and which are disposed on the pad-mounting surface at locations that are offset from locations of the corresponding ones of the solder points on the chip-mounting region, said method comprising the steps of:
attaching a printed circuit sheet to the pad-mounting surface, wherein the bonding pads are exposed from the printed circuit sheet, the printed circuit sheet including a non-conductive substrate with a printed surface that is opposite to the pad-mounting surface and that is printed with a plurality of conductive traces which are to be respectively and electrically connected to the bonding pads and which are respectively spaced apart from the bonding pads in lateral directions along the printed surface;
forming a plurality of conductive bonding wires that respectively interconnect the bonding pads and the conductive traces;
forming a photoresist layer on the printed surface and the pad-mounting surface such that the bonding pads and the bonding wires are embedded in the photoresist layer;
forming access holes in the photoresist layer, each of which is registered with and exposes at least a portion of a respective one of the conductive traces; and
forming a plurality of conductive bodies in the access holes, wherein each of the conductive bodies is electrically connected to a respective one of the bonding pads.
2. The method of claim 1 , wherein each of the access holes is formed in the photoresist layer at a location corresponding to a respective one of the solder points on the chip-mounting region of the substrate.
3. A semiconductor device adapted for mounting on a substrate, the substrate having a chip-mounting region provided with a plurality of solder points, said semiconductor device comprising:
a semiconductor chip having a pad-mounting surface provided with a plurality of bonding pads which are disposed on said pad-mounting surface at locations that are offset from locations of corresponding ones of the solder points on the chip-mounting region;
a printed circuit sheet attached to said pad-mounting surface and including a non-conductive substrate with a printed surface that is opposite to said pad-mounting surface and that is printed with a plurality of conductive traces which are respectively spaced apart from said bonding pads in lateral directions along said printed surface;
a plurality of conductive bonding wires that respectively interconnect said bonding pads and said conductive traces;
a photoresist layer overlaid on said printed surface and said pad-mounting surface such that said bonding pads and said bonding wires are embedded in said photoresist layer, and formed with a plurality of access holes, each of which is registered with and exposes at least a portion of a respective one of said conductive traces; and
a plurality of conductive bodies respectively disposed in said access holes, and connected electrically and respectively to said bonding pads.
4. The semiconductor device of claim 3 , wherein each of said access holes is formed in said photoresist layer at a location corresponding to a respective one of the solder points on the chip-mounting region of the substrate.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW089100578A TW434848B (en) | 2000-01-14 | 2000-01-14 | Semiconductor chip device and the packaging method |
TW089100578A04 | 2000-12-08 |
Publications (1)
Publication Number | Publication Date |
---|---|
US20020072148A1 true US20020072148A1 (en) | 2002-06-13 |
Family
ID=21658480
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/520,719 Expired - Fee Related US6239488B1 (en) | 2000-01-14 | 2000-03-08 | Method for mounting a semiconductor chip on a substrate, and semiconductor device adapted for mounting on a substrate |
US09/564,989 Expired - Fee Related US6333561B1 (en) | 2000-01-14 | 2000-05-05 | Method for mounting a semiconductor chip on a substrate, and semiconductor device adapted for mounting on a substrate |
US09/792,003 Abandoned US20020072148A1 (en) | 2000-01-14 | 2001-02-23 | Method for mounting a semiconductor chip on a substrate, and semiconductor device adapted for mounting on a substrate |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/520,719 Expired - Fee Related US6239488B1 (en) | 2000-01-14 | 2000-03-08 | Method for mounting a semiconductor chip on a substrate, and semiconductor device adapted for mounting on a substrate |
US09/564,989 Expired - Fee Related US6333561B1 (en) | 2000-01-14 | 2000-05-05 | Method for mounting a semiconductor chip on a substrate, and semiconductor device adapted for mounting on a substrate |
Country Status (4)
Country | Link |
---|---|
US (3) | US6239488B1 (en) |
JP (4) | JP3328643B2 (en) |
DE (4) | DE10027852A1 (en) |
TW (5) | TW434848B (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050079863A1 (en) * | 2003-10-08 | 2005-04-14 | Macaluso Anthony G. | Over the air provisioning of mobile device settings |
US7078823B2 (en) * | 2003-04-09 | 2006-07-18 | Micron Technology, Inc. | Semiconductor die configured for use with interposer substrates having reinforced interconnect slots |
US20060186535A1 (en) * | 2005-02-23 | 2006-08-24 | Visteon Global Technologies, Inc. | Semi-conductor die mount assembly |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6707159B1 (en) * | 1999-02-18 | 2004-03-16 | Rohm Co., Ltd. | Semiconductor chip and production process therefor |
TW434848B (en) * | 2000-01-14 | 2001-05-16 | Chen I Ming | Semiconductor chip device and the packaging method |
US6400016B2 (en) * | 2000-01-14 | 2002-06-04 | I-Ming Chen | Method for mounting a semiconductor chip on a substrate and semiconductor device adapted for mounting on a substrate |
US6437448B1 (en) * | 2000-01-14 | 2002-08-20 | I-Ming Chen | Semiconductor device adapted for mounting on a substrate |
US7057292B1 (en) | 2000-05-19 | 2006-06-06 | Flipchip International, Llc | Solder bar for high power flip chips |
TW494548B (en) * | 2000-08-25 | 2002-07-11 | I-Ming Chen | Semiconductor chip device and its package method |
US20020170897A1 (en) * | 2001-05-21 | 2002-11-21 | Hall Frank L. | Methods for preparing ball grid array substrates via use of a laser |
JP2003100801A (en) * | 2001-09-25 | 2003-04-04 | Mitsubishi Electric Corp | Semiconductor device |
TW594889B (en) | 2003-05-02 | 2004-06-21 | Yu-Nung Shen | Wafer level package method and chip packaged by this method |
JP4972280B2 (en) * | 2004-12-09 | 2012-07-11 | ローム株式会社 | Semiconductor device |
US7927976B2 (en) * | 2008-07-23 | 2011-04-19 | Semprius, Inc. | Reinforced composite stamp for dry transfer printing of semiconductor elements |
EP2351068B1 (en) * | 2008-11-19 | 2020-11-04 | X Display Company Technology Limited | Printing semiconductor elements by shear-assisted elastomeric stamp transfer |
TW201023314A (en) * | 2008-12-02 | 2010-06-16 | Aflash Technology Co Ltd | Semiconductor chip packaging structure |
US8261660B2 (en) * | 2009-07-22 | 2012-09-11 | Semprius, Inc. | Vacuum coupled tool apparatus for dry transfer printing semiconductor elements |
US8916969B2 (en) * | 2011-07-29 | 2014-12-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices, packaging methods and structures |
US9048222B2 (en) | 2013-03-06 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating interconnect structure for package-on-package devices |
US9583420B2 (en) | 2015-01-23 | 2017-02-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of manufactures |
US9281297B2 (en) | 2014-03-07 | 2016-03-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Solution for reducing poor contact in info packages |
US9293442B2 (en) | 2014-03-07 | 2016-03-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package and method |
US9449947B2 (en) | 2014-07-01 | 2016-09-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package for thermal dissipation |
JP5944979B1 (en) | 2014-12-26 | 2016-07-05 | 千住金属工業株式会社 | Solder transfer sheet, solder bump, and solder pre-coating method using solder transfer sheet |
DE102016109950B3 (en) | 2016-05-30 | 2017-09-28 | X-Fab Semiconductor Foundries Ag | Integrated circuit having a component applied by a transfer pressure and method for producing the integrated circuit |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5894165A (en) * | 1996-06-17 | 1999-04-13 | Micron Technology, Inc. | Leads between chips assembly |
US5923234A (en) * | 1997-10-27 | 1999-07-13 | Lockheed Martin Corp. | Hermetic feedthrough using three-via transmission lines |
US6144102A (en) * | 1997-05-16 | 2000-11-07 | Texas Instruments Incorporated | Semiconductor device package |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08236586A (en) * | 1994-12-29 | 1996-09-13 | Nitto Denko Corp | Semiconductor device and manufacturing method thereof |
US5661086A (en) * | 1995-03-28 | 1997-08-26 | Mitsui High-Tec, Inc. | Process for manufacturing a plurality of strip lead frame semiconductor devices |
JP3060896B2 (en) * | 1995-05-26 | 2000-07-10 | 日本電気株式会社 | Structure of bump electrode |
DE19541039B4 (en) * | 1995-11-03 | 2006-03-16 | Assa Abloy Identification Technology Group Ab | Chip module and method for its production |
US5902686A (en) * | 1996-11-21 | 1999-05-11 | Mcnc | Methods for forming an intermetallic region between a solder bump and an under bump metallurgy layer and related structures |
JP3042613B2 (en) * | 1997-11-27 | 2000-05-15 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
DE19800566A1 (en) * | 1998-01-09 | 1999-07-15 | Siemens Ag | Method for producing a semiconductor component and a semiconductor component produced in this way |
US6075712A (en) * | 1999-01-08 | 2000-06-13 | Intel Corporation | Flip-chip having electrical contact pads on the backside of the chip |
US6011314A (en) * | 1999-02-01 | 2000-01-04 | Hewlett-Packard Company | Redistribution layer and under bump material structure for converting periphery conductive pads to an array of solder bumps |
TW434848B (en) * | 2000-01-14 | 2001-05-16 | Chen I Ming | Semiconductor chip device and the packaging method |
TW494548B (en) * | 2000-08-25 | 2002-07-11 | I-Ming Chen | Semiconductor chip device and its package method |
-
2000
- 2000-01-14 TW TW089100578A patent/TW434848B/en active
- 2000-03-08 US US09/520,719 patent/US6239488B1/en not_active Expired - Fee Related
- 2000-03-15 TW TW89100578A01 patent/TW466715B/en active
- 2000-05-05 US US09/564,989 patent/US6333561B1/en not_active Expired - Fee Related
- 2000-06-06 DE DE2000127852 patent/DE10027852A1/en not_active Withdrawn
- 2000-07-18 JP JP2000217360A patent/JP3328643B2/en not_active Expired - Lifetime
- 2000-09-29 TW TW89100578A02 patent/TW495933B/en active
- 2000-10-21 TW TW89100578A03 patent/TW466716B/en active
- 2000-12-08 TW TW89100578A04 patent/TW503534B/en active
- 2000-12-28 JP JP2000400815A patent/JP3443567B2/en not_active Expired - Fee Related
-
2001
- 2001-01-17 DE DE2001101948 patent/DE10101948B4/en not_active Expired - Fee Related
- 2001-02-23 US US09/792,003 patent/US20020072148A1/en not_active Abandoned
- 2001-03-05 DE DE2001110453 patent/DE10110453A1/en not_active Withdrawn
- 2001-04-06 DE DE2001117239 patent/DE10117239A1/en not_active Ceased
- 2001-04-09 JP JP2001110048A patent/JP2002141438A/en active Pending
- 2001-04-11 JP JP2001112806A patent/JP2002198464A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5894165A (en) * | 1996-06-17 | 1999-04-13 | Micron Technology, Inc. | Leads between chips assembly |
US6144102A (en) * | 1997-05-16 | 2000-11-07 | Texas Instruments Incorporated | Semiconductor device package |
US5923234A (en) * | 1997-10-27 | 1999-07-13 | Lockheed Martin Corp. | Hermetic feedthrough using three-via transmission lines |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7078823B2 (en) * | 2003-04-09 | 2006-07-18 | Micron Technology, Inc. | Semiconductor die configured for use with interposer substrates having reinforced interconnect slots |
US7102217B2 (en) | 2003-04-09 | 2006-09-05 | Micron Technology, Inc. | Interposer substrates with reinforced interconnect slots, and semiconductor die packages including same |
US20050079863A1 (en) * | 2003-10-08 | 2005-04-14 | Macaluso Anthony G. | Over the air provisioning of mobile device settings |
US20060186535A1 (en) * | 2005-02-23 | 2006-08-24 | Visteon Global Technologies, Inc. | Semi-conductor die mount assembly |
Also Published As
Publication number | Publication date |
---|---|
DE10101948A1 (en) | 2002-04-18 |
JP3443567B2 (en) | 2003-09-02 |
JP2002110853A (en) | 2002-04-12 |
DE10117239A1 (en) | 2002-07-25 |
JP2002198464A (en) | 2002-07-12 |
JP3328643B2 (en) | 2002-09-30 |
US6333561B1 (en) | 2001-12-25 |
JP2001196421A (en) | 2001-07-19 |
TW466715B (en) | 2001-12-01 |
TW466716B (en) | 2001-12-01 |
TW495933B (en) | 2002-07-21 |
TW434848B (en) | 2001-05-16 |
US6239488B1 (en) | 2001-05-29 |
DE10101948B4 (en) | 2008-01-10 |
DE10110453A1 (en) | 2002-05-08 |
DE10027852A1 (en) | 2001-08-02 |
JP2002141438A (en) | 2002-05-17 |
TW503534B (en) | 2002-09-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20020072148A1 (en) | Method for mounting a semiconductor chip on a substrate, and semiconductor device adapted for mounting on a substrate | |
US6339260B1 (en) | Wire arrayed chip size package | |
US6400016B2 (en) | Method for mounting a semiconductor chip on a substrate and semiconductor device adapted for mounting on a substrate | |
US7022552B2 (en) | Semiconductor device and method for fabricating semiconductor device | |
US20020113323A1 (en) | Integrated semiconductor circuit | |
EP1443555A3 (en) | Semiconductor device and method of manufacturing the same | |
US6420788B1 (en) | Method for mounting a semiconductor chip on a substrate and semiconductor device adapted for mounting on a substrate | |
US7651886B2 (en) | Semiconductor device and manufacturing process thereof | |
TWI269361B (en) | Structure of substrate integrated embedded passive component and method of forming the same | |
KR970067788A (en) | Semiconductor device, manufacturing method and substrate frame | |
JP5784280B2 (en) | Electronic device package and manufacturing method | |
JP2000150702A (en) | Manufacture of semiconductor device | |
US7053473B2 (en) | Compact integrated circuit package | |
KR100658120B1 (en) | Process for manufacturing semiconductor device using film substrate | |
US7135642B2 (en) | Integrated circuit carrier with conductive rings and semiconductor device integrated with the carrier | |
US6437448B1 (en) | Semiconductor device adapted for mounting on a substrate | |
KR100375248B1 (en) | Method for mounting a semiconductor chip on a substrate, and semiconductor device adapted for mounting on a substrate | |
JPH1174421A (en) | Composite semiconductor device | |
JP2006013205A (en) | Semiconductor device and manufacturing method therefor | |
JPH05326648A (en) | Film carrier and manufacture of semiconductor device employing film carrier | |
KR100420780B1 (en) | Method for mounting a semiconductor chip on a substrate and semiconductor device adapted for mounting on a substrate | |
KR200179418Y1 (en) | Semiconductor package | |
JP3055486B2 (en) | socket | |
US20040135257A1 (en) | Semiconductor device with a multi-level interconnect structure and method for making the same | |
JPH05136327A (en) | Semiconductor package |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: COMPUTECH INTERNATIONAL VENTURES LIMITED, VIRGIN I Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CHEN, I-MING;REEL/FRAME:013317/0153 Effective date: 20020801 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |