US20020048944A1

US20020048944A1 - Multi-level circuit structure

Info

Publication number: US20020048944A1
Application number: US10/011,198
Authority: US
Inventors: Sanh Tang; Rajendra Narasimhan
Original assignee: Individual
Current assignee: Individual
Priority date: 1999-11-02
Filing date: 2001-11-09
Publication date: 2002-04-25
Also published as: US6352916B1

Abstract

In a semiconductor device, a conductive structure comprising an interconnect and an overlying plug integrally extending therefrom is provided. The structure can be provided by a damascene process, wherein an opening is defined in insulation deep enough to accommodate the height of an interconnect and its overlying plug. The opening is filled with metal, and non-plug areas of the metal are then recessed down to a standard interconnect height within the trench. The full height of the metal is retained at the plug site. Oxide is then deposited over the recessed portions. Alternatively, a continuous metal layer is provided that is deep enough to accommodate the height of an interconnect and its overlying plug. The metal is then etched to form the interconnect/plug structure, and insulation is deposited thereover. Multiple structures may be provided at the same level using these processes, and multiple levels of these structures may be similarly provided.

Description

TECHNICAL FIELD

The present invention relates generally to metallization processes used in integrated circuit manufacture. More specifically, the current invention relates to methods of forming a via for electrical communication between multiple levels of interconnects and the devices resulting therefrom.

BACKGROUND OF THE INVENTION

In processing integrated circuits, it is important to be able to establish electrical communication between conductive elements at different locations within a circuit. These elements often take the form of conductive lines or paths known as “interconnects” due to their function of electrically interconnecting circuit nodes. Interconnects at different elevations will be separated by at least one insulation layer, such as an interlayer dielectric. Thus, providing electrical communication between such interconnects will often involve (1) forming the lower interconnect; (2) layering insulation over the lower interconnect; (3) defining an opening, often called a “via,” through the insulation and leading to the lower interconnect; (4) using a conductive material to fill the via, in which case the conductive material may be referred to as a “plug;” and (5) forming the higher interconnect over the plug.

On a larger scale, it should be appreciated that there are often several interconnects at any particular level of a circuit device. Further, one should note that, while one lower level interconnect may need to connect to one higher interconnect at one point, a second lower level interconnect may need to contact a second higher interconnect at a different point. As a result, after the lower level of interconnects have been formed and covered with insulation, a particular pattern of vias are formed in the insulation.

Forming these vias entails etching through the insulation in areas exposed by an overlying patterned mask. Ideally, the etch stops once the lower level of interconnects is reached and before any of the conductive material of that level is etched. In reality, however, the top of the interconnects suffer some degree of etching at the exposure. Polymer may be formed as a result of etching this conductive material. The presence of polymer may interfere with further processing and, therefore, at least one cleaning step may be needed to remove the polymer. Even with cleaning, however, some polymer may remain. The presence of the polymer may then interfere with communication between the plug and the subsequently formed upper interconnect.

Another problem occurs as a result of the constant need in the art to make eversmaller semiconductor devices to allow a more efficient use of the silicon substrate from which such devices are fabricated. This need requires the widths of features, including vias, to become narrower with each generation of devices. However, a layer of insulation must maintain a minimum vertical distance between upper and lower conductive members; if the insulation between the two such members is too thin, an intolerably high level of capacitance will be generated between the members and interfere with their desired operation. Thus, as circuit dimensions continue to scale down, the width of the via decreases, but its depth, determined by the required thickness of the insulation, must remain generally the same. In other words, the aspect ratio of the via increases as the critical lateral dimensions of devices shrink. Unfortunately, high aspect ratios associated with a via make it difficult to ensure that the via has been completely filled with the conductive plug material. Gaps in the plug will degrade the plug's ability to allow electrical communication between conductive members.

Also of note is the fact that each discrete deposition of one conductor on another represents a potential disruption in continuity of conductive material which, in turn, affects the ability to allow electrical communication. Separate deposition steps may allow contaminants to accumulate between those steps. Further, depositing one kind of conductive material onto a different kind may hamper electrical conductivity. Even assuming that the same type of material is deposited in two separate steps and that contaminants are kept to an absolute minimum, there may still be spaces between the discretely deposited layers that would not exist if the two layers had been deposited as one. All of these factors can adversely affect electrical communication between interconnects at different levels. Specifically, these problems can occur at both the lower level interconnect/plug interface and the plug/higher level interconnect interface.

Thus, there is a need in the art to provide electrical communication between conductive elements while at least reducing the problems discussed above. It would also be desirable to be able to reduce the number of deposition steps needed to provide conductive elements and a connector between them.

SUMMARY OF THE INVENTION

Accordingly, at least some exemplary embodiments of the current invention provide methods of connecting conductive elements and further provide the structures resulting from those methods. In one exemplary embodiment, a trench is etched in a layer of insulation or dielectric, wherein the trench is deep and long enough to accommodate an interconnect as well as a plug or other interlayer electrical connection configured to contact a later-formed interconnect at a higher elevation. The entire trench is filled with conductive material. In an area that is not designated as a plug site, the height of the conductive material is reduced. In an area that is designated as a plug site, the height of the conductive material is retained. The recessed portion of conductive material is then covered with additional insulation. Another interconnect may then be formed over the insulative materials so that it contacts the plug. Other embodiments involve etching a plurality of trenches at one level of a semiconductor device, wherein the trenches are deep enough to accommodate interconnects as well as plug sites anywhere along each trench.

Another exemplary embodiment comprises etching at least one plug/interconnect structure from a continuous layer of metal and then depositing insulation around the structure or structures.

Still another exemplary embodiment comprises using at least one of the processes described above to create multiple levels of interconnects.

Yet other embodiments address the in-process apparatus or final product resulting from these and other processes. Such exemplary embodiments include a conductive structure such as an interconnect that is integral to or is continuous with a plug structure configured to contact a higher interconnect.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A, 1B, [0012] 2, and 3 depict an in-process device undergoing processes known in the art.
FIGS. [0013] 4-8B illustrate a first exemplary embodiment of the current invention, with FIGS. 4, 5, 6A, 7A and 8A offering cross-sectional views, while FIGS. 6B, 7B, and 8B offer top-down views.
FIGS. [0014] 9-11 describe a second exemplary embodiment of the current invention.
FIG. 12 depicts a third exemplary embodiment of the current invention. [0015]
FIGS. [0016] 13-19B picture a fourth exemplary embodiment of the current invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIGS. [0017] 1-3 offer a brief review of the prior art discussed above in order to more clearly distinguish exemplary embodiments of the current invention. FIG. 1A illustrates that interconnects 20 and 22 are provided over a surface 24. This surface 24 may define the top of an insulation layer, in which case there may be plugs leading up to the interconnects from lower-level interconnects. These plugs and interconnects are not shown in FIG. 1A for the sake of clarity. The surface 24 could also represent a semiconductor substrate. In the current application, the term “substrate” or “semiconductor substrate” will be understood to mean any construction comprising semiconductor material, including but not limited to bulk semiconductive materials such as a semiconductor wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). Further, the term “substrate” also refers to any supporting structure including, but not limited to, the semiconductive substrates described above. Moreover, it is understood that a semiconductor device may comprise conductive and insulative materials as well as a semiconductive material.
As for the [0018] interconnects 20, 22 themselves, they can be formed out of the same conductive material which, in turn, can be provided to both interconnect sites in a common deposition step. For example, one skilled in the art can deposit a continuous conductive layer; etch the desired interconnect features 20, 22 from that layer; and then deposit insulation 26 over the interconnects 20, 22. Alternatively, as seen in FIG. 1B, a damascene process may be used, wherein at least a portion of insulation 26′ is deposited; trenches are etched into the portion of insulation 26′, wherein the trenches define sites for interconnects 20 and 22; conductive material is deposited into the trenches; and any overflow of conductive material is etched or planarized away. The “MI” designation on interconnects 20 and 22 indicates that both interconnects 20, 22, are metal and further resulted from the same metal deposition step. Specifically, interconnects 20, 22 resulted from the first metal deposition step, hence the term “M1.” An exemplary height of these interconnects 20, 22 is 5,000 Angstroms. Accordingly, the portion of insulation 26′ used to define the interconnect sites is also about 5,000 Angstroms thick. Additional amounts of insulation 26 may then be added over the filled trenches to achieve the state of the inprocess device depicted in FIG. 1B. As an exemplary amount, the additional insulation 26 may add another 3,000 Angstroms to the thickness of insulation 26, resulting in a maximum thickness of 8,000 Angstroms in areas extending to the surface 24. As an exemplary material, borophosphosilicate glass (BPSG) may serve as insulation 26 and 26′.
Regardless of the method used provide interconnects covered in insulation, the next step in the prior art is to etch vias in areas where it is desired to allow contact between an existing interconnect and an interconnect to be formed later at a higher elevation. This step is illustrated in FIG. 2. At the particular cross-section illustrated in that figure, it is desired to contact [0019] interconnect 20 but not interconnect 22. As a result, only one via 28 is etched at this point in the in-process device 30. This via etch is guided by a patterned mask 27, provided over insulation 26. Patterned mask 27 covers the insulation 26 over interconnect 22 but has an opening allowing the etching of via 28 over interconnect 20. Unfortunately, etching the via 28 through the insulation 26 may also result in etching at least a portion of interconnect 20. Etching the conductive material of interconnect 20 may then result in the formation of polymer 32 or other residue.
Even if steps are taken to clean the via [0020] 28 of polymer 32, some polymer 32 may be present in the via 28 when the plug 34 is subsequently deposited, as seen in FIG. 3. Thus, when interconnect 36 is formed over plug 34 as part of a second metal deposition step “M2”, the polymer 32 may interfere with electrical communication between interconnects 20 and 36. What should also be noted is the fact that the prior art method of achieving this structure involves three different depositions of conductive material: one for a lower level of interconnects (such as 20 and 22); one for the plug 34; and one for a higher level of interconnects (such as 36). As a result, there are two interfaces 38, 40, one representing the boundary between interconnect 20 and plug 34; and a second representing the boundary between plug 34 and interconnect 36. Problems discussed in the Background section may be associated with these two interfaces 38, 40.
FIG. 4 illustrates a first stage in an exemplary embodiment of the current invention that reduces if not eliminates such problems. Rather than separately defining interconnect sites and via sites, FIG. 4 discloses providing at least one trench in sufficiently [0021] thick insulation 26, wherein each trench's height encompasses an interconnect site (such as 124 or 126) as well as any overlying plug site (such as 128 or 130) regardless of whether a plug will ultimately appear at those plug sites. For purposes of explaining exemplary embodiments of this invention, the term “site” is understood to designate a region where a structure was, is, or is to be located.
The trench etch may be performed by any known technique. It may be desirable to use a process that will selectively etch the [0022] insulation 26 to the exclusion of the material used for surface 24. It may also be preferable to use an anisotropic etch so that the trenches will have a vertical sidewall, which allows for denser packing of devices. Assuming the insulation 26 is BPSG, exemplary etch parameters include flowing equal amounts of CF₄and CHF₃into a magnetically enhanced reactive ion etch chamber. The chamber pressure should be about 200 mTorr, the chamber temperature can be at room temperature, the applied magnetic field should be about 50 Gauss, and the applied RF energy should be between 600 W and 1000 W. A patterned mask over the BPSG can determine where the trenches are etched, and the BPSG should be etched under these conditions for at least enough time to reach the surface 24.
A conductive material is then deposited into each trench, and the resulting [0023] conductive structures 120, 122 can be seen in FIG. 5. In this exemplary embodiment, the conductive structures 120, 122 are made of metal. Moreover, the conductive structures 120, 122 are made of the same metal and result from the same metal deposition step as indicated once again by the “M1” designation. As an exemplary metal, tungsten could be deposited. Exemplary parameters of a tungsten CVD process involve reacting tungsten hexafluoride (WF₆) with silane (SiH₄) at a pressure of about 4.5 Torr and a temperature of about 450° C. Regardless of the specific deposition process, it continues at least until the trenches are filled. Any metal deposited onto the top of insulation 26 can be removed through etching or by way of planarization techniques, including abrasive planarization methods such as chemical-mechanical planarization (CMP). As an alternative to depositing tungsten, aluminum could be deposited by sputtering, chemical vapor deposition (CVD), or other methods known in the art.
Focusing briefly on sputtering aluminum in a damascene process such as the one described above, it should be noted that exemplary embodiments of the current invention that do so have an advantage over prior art methods that do so. To ensure that a trench is adequately filled with sputtered aluminum, it is desirable to sputter at a high temperature. This allows aluminum to better flow into the trench. Unfortunately, the high temperature also results in a rough surface. In the prior art, an additional (and therefore undesirable) planarization step is necessary to remedy this. To avoid the additional planarization step, prior art methods sputter aluminum into the trench at a relatively low temperature (480° C.) at the risk of poor trench-fill. Some exemplary embodiments of the current invention, however, already comprise a planarization step to achieve the in-process structure depicted in FIG. 5. As a result, nothing is lost by sputtering aluminum at a high temperature (ranging from 510° C. to 520° C., for example), and a more reliable trench-fill process is gained. [0024]
The resulting [0025] conductive structures 120, 122 serve as interconnects or other conductive lines or paths. In addition, the conductive structures 120, 122 also provide conductive material for plugs that may be desired anywhere along those paths. Further, because such plugs will be defined along with the interconnects, the result will be a continuous and homogeneous electrically conductive structure including one part extending from one surface 24 to a more elevated surface 132, where other interconnects could be formed. Accordingly, the height of these conductive structures generally matches the thickness of the insulation 26—here assumed to be 8,000 Angstroms.
In areas where plugs are not desired, excess conductive material may be removed from those areas while still retaining enough conductive material to serve as an interconnect. For example, it is assumed that no plug is desired for [0026] conductive structure 122 at the particular cross-section displayed in FIG. 5, even though a plug site 130 has been etched and filled with metal along with interconnect site 126. It is further assumed that, while a plug is desired for conductive structure 120 at FIG. 5's particular cross-section, plugs may not be desired at other cross-sections for that conductive structure 120.
Thus, in order to isolate portions of [0027] conductive structures 120, 122 from the elevated surface 132, FIGS. 6A and 6B demonstrate that a patterned mask 134 is provided over the elevated surface 132, wherein areas of conductive structures 120 and 122 that should not extend to the elevated surface 132 are exposed. On the other hand, portions of structures that are to extend to the elevated surface 132 (such as plug site 128 of structure 120) are protected by the mask 134. The result is a mask 134 defining a pattern that is generally inverse to the patterned mask 27 used to define the prior art vias 28 in FIG. 2. The prior art pattern, however, requires a mask opening that corresponds to the width of the via 28. Because the narrowest possible via is desired for purposes of shrinking semiconductor devices, the mask opening must be correspondingly small, thereby pushing the limits of the lithography steps used to provide such an opening. In contrast, the mask 134 in FIGS. 6A and B need not meet such tolerances, as the in-process device in those figures allows for a selective etch to remove the conductive material of 122 to the exclusion of insulation 26. (Compare the opening in mask 27 of FIG. 2 used to form via 28 with the opening in mask 134 of FIG. 6A used to clear plug site 130.
If aluminum serves at the [0028] conductive material 122, it could be dry etched anisotropically using a plasma containing chlorine, as is known in the art. Exemplary gasses for the plasma include Cl₂and BCl₃. Regardless of the specific parameters of this etch, it is performed long enough to recess the exposed portions of conductive structures 120 and 122 to a point below the elevated surface 132. Preferably, the exposed portions of conductive structures 120 and 122 are recessed to a height of 5,000 Angstroms. One result depicted in FIG. 6A is a conductive structure 122 that extends through its interconnect site 126 and up to, but not including, its plug site 130. Another result is that conductive structure 120 has been recessed in all areas pictured except for the plug site 128 under the mask 134.
FIGS. 7A and B illustrate that the [0029] mask 134 is subsequently removed and plug site 130, along with other portions of conductive structures 120, 122 that were unmasked during the etch, receive an insulation material 135, such as interlayer dielectrics known in the art. Those dielectrics include oxides and, more specifically, may comprise additional BPSG. Accordingly, processes for depositing this insulation material 135 are also known in the art. Filling these areas may also result in depositing extra insulation onto the elevated surface 132 and onto portions of conductive structures reaching that surface, such as plug site 128 of conductive structure 120. In that event, the extra insulation is removed through etching or planarization steps to expose the tops of conductive structures that remain fully extended.
At least one additional interconnect [0030] 136 (as well as 136′) may then be formed on the elevated surface 132, as seen in FIGS. 8A and 8B. As on the lower surface 24, several interconnects 136, 136′ may be formed on this upper level simultaneously as part of a second metal deposition step M2. FIGS. 8A and 8B show that electrical communication may occur between interconnect 136 and conductive structure 120 through the unetched portion thereof. In contrast to the prior art result of FIG. 3, however, eliminating the separate via etch eliminates the polymer 32 that can result from that etch and interfere with electrical communication. Further, if a third level of interconnects is desired, interconnects 136 and 136′ can be provided in much the same manner as the methods used for conductive structures 120 and 122, wherein integral plugs can be extended from the conductive structures 136 and 136′ at selective sites up to the third level.
An alternative method of forming the first, second, or any level of interconnects involves a non-damascene process, as shown beginning with FIG. 9. That figure illustrates a conductive layer, preferably metal M, deposited as a continuous layer over a [0031] surface 24. The thickness of metal M is generally equal to the height of an interconnect plus an overlying plug. Once again, this thickness is assumed to be 8,000 Angstroms. A patterned mask is then provided over metal M, and an etch is carried out according to the pattern. The mask is then removed. The result is seen in FIG. 10, wherein metal structures 220 and 222 have been formed from the formerly-continuous metal M. FIG. 11 demonstrates that insulation 224 is then provided around the metal structures. This can be achieved with a spin-on-glass process; a process using flowfill, wherein a silane/hydrogen peroxide chemistry allows insulation to literally flow between structures before solidifying; or some other process for providing an oxide. Any amount of insulation 224 appearing over the metal structures 220 and 222 may be removed by planarization or wet or dry etching. The tops of the conductive structures 220 and 222 and the coplanar surface of the insulation 224 once again define an elevated surface 132 configured to receive an additional level of interconnects. Assuming that metal structure 222 is to be isolated at this cross-section, that isolation may be achieved using etch methods as described above, involving recessing selected portions of the metal structure 222 and filling that recess with oxide.
The current invention also includes within its scope processes using a combination of methods to produce combined interconnect/plug structures. For example, the structure in FIG. 12 could be achieved using a damascene-type process (see FIGS. [0032] 4-7B and accompanying text) to provide the first interconnect level 326, comprising conductive structures 320 and 322 and insulation portions 324 and 325; whereas the non-damascene process just described above could be used to provide the second interconnect level 426, comprising conductive structures 420 and 422 and insulation portions 424 and 425. This is, in fact, a preferable embodiment, as higher levels of metallization are usually less restricted in terms of their critical dimension, and this non-damascene process lends itself to such kinds of metallization.
In addition, the current invention is not limited to providing electrical communication between interconnects or other lines or paths. FIG. 13 is the first figure in an embodiment wherein electrical communication is provided between a semiconductor substrate and overlying interconnects. FIG. 13 displays three field-[0033] effect transistors 500, 502, and 504 constructed on a substrate 506, portions of which may be doped. FIG. 14 shows that insulation, in this case BPSG 508, is deposited over the substrate 506 and transistors 500, 502, 504 and is subsequently planarized. A patterned mask (not shown) is provided over the BPSG 508, and etching the BPSG 508 as guided by that mask results in the openings 510, 512, and 514 depicted in FIG. 15A. A top-down view of these openings 510, 512, and 514 is offered in FIG. 15B. FIG. 15B also identifies axis A-A; all of the cross-sectional figures of this exemplary embodiment illustrate a cross section along this axis. It can be seen from FIG. 15B's perspective that openings 510 and 514 are elongated trenches that are not necessarily coextensive, whereas opening 512 is a more cylindrical opening. In addition, FIG. 15B reveals another opening 516 that is not revealed in FIG. 15A.
FIG. 16 demonstrates optional steps for this and other embodiments. First, the [0034] openings 510, 512, 514, and 516 are lined with a titanium layer 518. At some point in the process, this titanium layer 518 can be sintered at a high temperature, thereby forming titanium silicide at the interface between the titanium layer 518 and the substrate 506, which results in good ohmic contact. In addition, nitrogen can be incorporated into the titanium layer 518 so that it may act as an adhesion layer for the subsequently deposited conductive material. Methods of providing these liners are known in the art. Subsequently, a conductive material 522, assumed to be tungsten or aluminum in this embodiment, is deposited into the openings 510, 512, 514, and 516. Amounts of conductive material 522 that deposit beyond the openings are etched back or removed by planarization.
FIG. 17A next shows that areas in which it is desired to maintain electrical access to the [0035] substrate 506 from the top of BPSG 508 are protected by patterned photoresist 524, while other portions of the conductive material 522 are left exposed for the subsequent etch step. FIG. 17B offers another perspective that more clearly demonstrates the coverage of a portion of the patterned photoresist 524. Specifically, the photoresist 524 completely covers openings 512 and 516. Photoresist 524 also extends to cover a portion of the conductive material 522 in the trench-shaped opening 514. None of the conductive material 522 in opening 510 is protected by photoresist 524 (at least, none of the conductive material 522 viewable in FIGS. 17A and B is protected). Accordingly, the unprotected portions of conductive material 522 in openings 510 and 514 are etched. The photoresist 524 is subsequently removed.
In FIG. 18, the recessed areas of openings [0036] 510 (and 514 not shown in this cross section) are filled with oxide 526. That oxide 526 can be etched back, as can the BPSG 508 in order to better expose the “plugs” included as an integral part of the conductive material 522 in openings 512, 514, and 516.
FIGS. 19A and B illustrate that [0037] interconnects 528 and 530 can then be provided over the remaining “plugs.” For example, interconnect 530 contacts the conductive material 522 in opening 516. A second interconnect 528 contacts the conductive material 522,in opening 512 as well as a portion of the conductive material 522 in opening 514. Other portions of conductive material 522 in opening 514 are covered by oxide 526, as is the conductive material 522 in opening 510.
One skilled in the art can appreciate that, although specific embodiments of this invention have been described above for purposes of illustration, various modifications may be made without departing from the spirit and scope of the invention. For example, it may not be necessary in certain embodiments to recess the interconnect/plug structure if there will be no higher interconnect structure extending thereover. Moreover, while the exemplary embodiments discussed above are explained in terms of multiple layers of interconnects or interconnects electrically communicating with portions of a substrate, the current invention applies to other conductive lines, paths, or conductive elements in general. Further, while at least some exemplary embodiments could be described in terms of a multi-level structure in that a first part of the structure is located in one level of a device and a second part seamless with the first part extends to a second level of the device; exemplary embodiments could also be described as a multi-axial structure, wherein a first part extends primarily along a first axis and an integral second part extends primarily along a second axis, wherein the second axis and first axis are perpendicular. In addition, the present invention may be implemented in a variety of integrated circuit devices such as memory devices, including DRAM and SRAM; logic devices, including those having embedded memory; application specific integrated circuits; microprocessors; microcontrollers; digital signal processors; and the like incorporating a memory array. Accordingly, the invention is not limited except as stated in the claims. [0038]

Claims

What is claimed is:

1. A method of forming at least one conductive plug in a semiconductor device, comprising:

including an insulator material as part of said semiconductor device;

defining a trench in said insulator material, said trench having a length sufficient to accommodate an interconnect, and said trench further having a depth sufficient to accommodate said interconnect and said at least one plug over said interconnect anywhere along said length;

filling said trench with a conductive material;

recessing said conductive material except in at least one site respectively designated for said at least one plug; and

providing insulation within said trench and over a recessed portion of said conductive material.

2. A method of processing a circuit device including insulation material, comprising:

etching a plug site in said insulation material of said circuit device;

etching an interconnect site in said insulation material under said plug site;

initiating a deposition of a metal into said interconnect site; and

continuing said deposition of said metal into said plug site.

3. The method in claim 2, further comprising contacting said metal in said plug site with an interconnect over said plug site.

4. The method in claim 2, further comprising:

etching said metal from said plug site;

filling said plug site with an oxide; and

contacting said oxide in said plug site with an interconnect over said plug site.

5. A method of constructing a semiconductor device, comprising:

providing a first plurality of integrated interconnect/plug structures within a first insulation layer of said semiconductor device; and

replacing a plug portion of at least one interconnect/plug structure of said first plurality with additional insulation.

6. The method in claim 5, wherein said step of providing a first plurality of integrated interconnect/plug structures comprises providing said first plurality of integrated interconnect/plug structures using a damascene process.

7. The method in claim 6, further comprising providing a plurality of interconnects on said-first insulation layer.

8. The method in claim 7, wherein said step of providing a plurality of interconnects comprises providing a second plurality of integrated interconnect/plug structures.

9. The method in claim 8, wherein said step of providing a second plurality of integrated interconnect/plug structures further comprises:

providing a conductive layer on said first insulation layer, wherein said conductive layer has a height defining an interconnect height and a plug height; and

etching said second plurality of integrated interconnect/plug structures from said conductive layer.

10. The method in claim 9, wherein said step of providing a second plurality of integrated interconnect/plug structures comprises providing said second plurality of integrated interconnect/plug structures within a second insulation layer.

11. The method in claim 10, wherein said step of providing said second plurality of integrated interconnect/plug structures within a second insulation layer comprises flowing insulation between each of said second plurality of integrated interconnect/plug structures.

12. The method in claim 10, wherein said step of providing said second plurality of integrated interconnect/plug structures within a second insulation layer comprises spinning glass between each of said second plurality of integrated interconnect/plug structures.

13. A method of integrating an interconnect and an overlying plug in a semiconductor wafer structure, comprising:

etching an elongated trench from at least one layer of said semiconductor wafer structure;

filling said trench with metal;

masking a portion of said trench; and

etching some of said metal from an unmasked portion of said trench.

14. The method in claim 13, further comprising a step of depositing insulation within said trench.

15. A method of forming a conductive plug over an interconnect in a semiconductor device, comprising:

providing a layer of insulation as a part of said semiconductor device, said layer of insulation having a thickness sufficient to accommodate a plug site and an interconnect site;

etching said plug site from said layer of insulation; and

filling said plug site with conductive material.

16. The method in claim 15, wherein said step of etching said plug site from said layer of insulation comprises further etching said interconnect site from said layer of insulation.

17. The method in claim 16, wherein said step of filling said plug site with conductive material comprises filling said interconnect site with said conductive material.

18. A method of forming a conductive plug over an interconnect in a memory device, comprising:

providing a layer of insulation as a part of said memory device;

etching a via from said layer of insulation;

etching a portion of said layer of insulation from an area lateral to and extending from said via;

filling said via and said area with conductive material; and

etching said conductive material from said area.

19. The method in claim 18, further comprising:

masking said via before said step of etching said conductive material; and

filling said area with additional insulation.

20. A method of forming a conductive plug over an interconnect in an electronic device, comprising:

providing a layer of insulation over a portion of said electronic device;

etching a plug site from said layer of insulation;

continuing to etch an interconnect site; and

filling said plug site with metal.

21. The method in claim 20, wherein said step of filling said plug site comprises initially filling said interconnect site with said metal.

22. A method of processing a wafer having an insulation layer flanking conductive paths and configured to receive a patterned first mask on top of said insulation layer, wherein said first mask is configured to expose plug sites within said insulation layer, said method comprising:

allowing said conductive paths to extend to said top of said insulation layer of said wafer; and

patterning a second mask on said insulation layer, wherein said second mask is generally inverse to said first mask.

23. The method in claim 22, wherein said step of patterning a second mask comprises masking said plug sites.

24. The method in claim 23, wherein said step of patterning a second mask comprises exposing portions of said conductive paths external to said plug sites.

25. The method in claim 24, wherein said step of patterning a second mask comprises exposing said portions of said conductive paths and portions of said insulation layer external to said plug sites.

26. The method of claim 25, further comprising a step of etching said portions of said conductive paths.

27. The method of claim 26, wherein said etching step further comprises selectively etching said portions of said conductive paths to a general exclusion of said insulation layer.

28. A method of allowing electrical connection to a conductive path of a semiconductor apparatus, comprising

providing a dielectric as a part of processing said semiconductor apparatus;

etching an opening in said dielectric to a depth configured to accommodate said conductive path and a plug over said path;

filling said opening with conductive material;

designating a conductive path site comprising a lower portion of said conductive material within said opening;

designating a plug site comprising a first upper portion of said conductive material within said opening;

etching a second upper portion of said conductive material next to said first upper portion; and

avoiding etching said plug site while etching said second upper portion.

29. The method in claim 28, wherein said step of avoiding etching said plug site comprises masking said plug site.

30. The method in claim 29, further comprising a step of avoiding etching said lower portion of said conductive material while etching said second upper portion.

31. A system of interconnects for a semiconductor structure, comprising:

a first interconnect within said semiconductor structure; and

a second interconnect coupled to said first interconnect through a plug, wherein

said second interconnect and said plug define an integral structure.

32. The system in claim 31, wherein at least a portion of said second interconnect is under said first interconnect.

33. The system in claim 32, wherein said portion of said second interconnect is coupled to said first interconnect through said plug.

34. The system in claim 33, farther comprising a third interconnect laterally contacting a first insulator and at least partially isolated from said first interconnect by a second insulator.

35. The system in claim 34, wherein said second interconnect laterally contacts said first insulator.

36. The system in claim 35, wherein said second insulator laterally contacts said plug, and wherein said second insulator is over a part of said second interconnect.

37. A portion of a memory array, comprising at least one integrated structure comprising a first interconnect within said memory array and an electrical connector extending upward.

38. A portion of a semiconductor device comprising:

at least two portions of insulation defining:

a first opening within said semiconductor device, defining:

a first plug site, and

a first interconnect site in communication with said first plug site,

wherein said first plug site and said first interconnect site are filled with a continuous amount of conductive material; and

a second opening lateral to said first opening, said second opening defining:

a second plug site filled with at least one portion of said at least two portions of insulation, and

a second interconnect site in communication with said second plug site, wherein said second interconnect site is filled with said conductive material.

39. A level of interconnects for a semiconductor device, comprising:

a layer of insulation defining a plurality of trenches within said semiconductor device, wherein each trench of said plurality defines a lower portion and an upper portion, and wherein:

said lower portion is filled with metal,

said metal extends up into at least one area of said upper portion, and

said upper portion is filled with oxide except in said at least one area.

40. The level of interconnects in claim 39, wherein said each trench is lined with a barrier layer.

41. The level of interconnects in claim 39, wherein said each trench is lined with an adhesion layer.

42. A multi-layer interconnect structure for a memory apparatus, comprising:

a first layer of insulation forming a part of said memory apparatus;

a second layer of insulation over said first layer;

a first conductive path within said first layer of insulation, wherein said first conductive path comprises a first integral plug extending toward said second layer;

a discrete portion of insulation within said first layer, over said first conductive path, and under said second layer of insulation; and

a second conductive path within said second layer of insulation, wherein said second conductive path contacts said first plug.

43. The multi-layer interconnect structure of claim 42, wherein said second layer of insulation has a top, and wherein said second conductive path comprises a second integral plug extending toward said top.

44. A semiconductor device, comprising:

a first surface of said semiconductor device;

a first conductive element on said first surface;

a second surface below said first surface; and

a second conductive element on said second surface, wherein said second conductive element comprises a first part extending to said first conductive element and a second part integral to said first part and recessed from said first surface.

45. The semiconductor device in claim 44, further comprising:

a first insulator lateral to said second conductive element; and

a second insulator above said second part of said second conductive element;

wherein a top of said first insulator and a top of said second insulator define said second surface.

46. The semiconductor device in claim 45, wherein said first conductive element is a conductive line.

47. The semiconductor device in claim 45, wherein said second conductive element is an interconnect.

48. A portion of circuitry, comprising:

a surface;

an insulation layer over said surface;

a conductive element over said insulation layer; and

a conductive circuitry structure comprising:

a first part extending from said surface, through said insulation layer, to said conductive element, and

a second part integral to said first part, insulated from said conductive element, and extending laterally from said first part.

49. The portion of circuitry in claim 48, wherein said surface is a semiconductor substrate.

50. A method of forming a vertical and horizontal electrical connection structure for a semiconductor device, comprising:

forming an insulating layer onto a part of said semiconductor device;

defining a trench in said insulating layer;

filling said trench with a conductor; and

reducing a height of said conductor within said trench at all but at least one location.

51. A method of forming a lateral interconnect circuitry structure including at least one vertically-protruding plug, comprising:

forming a circuitry insulating layer having a laterally-extending recess therein;

filling said laterally-extending recess with a conductive material; and

removing a depth of said conductive material from said recess except at at least one location.

52. The method in claim 51, further comprising a step of retaining at least some of said conductive material in a portion of said recess that is external to said at least one location.

53. A method of treating an in-process circuit, comprising:

forming a trench from an insulation material;

sputtering an interconnect material into said trench, wherein said sputtering step occurs at a temperature ranging from 510° C. to 520° C.;

forming a plug over said interconnect material; and

refraining from planarizing said in-process circuit between said sputtering step and said step of forming a plug.

54. The method in claim 53, wherein said sputtering step comprises sputtering aluminum.

55. The method in claim 54, wherein said step of forming a trench comprises forming a trench having a depth sufficient to accommodate a height of an interconnect and a height of a plug anywhere along said trench; and wherein said step of forming a plug comprises:

continuing to sputter aluminum into said trench; and

recessing a surface of said aluminum except at at least one region representing at least one respective plug site.

56. A multi-level circuit structure, comprising:

a first part of said circuit structure positioned in a lower level of a semiconductor device and isolated from a higher level of said device; and

a second part of said circuit structure seamlessly coupled to said first part, wherein said second part extends to said higher level.

57. The structure in claim 56, wherein said first part and said second part are metal.

58. A multi-axial circuit structure, comprising:

a first part of said circuit structure extending primarily along a first axis;

a second part of said circuit structure integral to said first part, wherein said second part extends upward from said first part primarily along a second axis perpendicular to said first axis.