US20010023139A1 - Center bond flip chip semiconductor carrier and a method of making and using it - Google Patents
Center bond flip chip semiconductor carrier and a method of making and using it Download PDFInfo
- Publication number
- US20010023139A1 US20010023139A1 US09/469,630 US46963099A US2001023139A1 US 20010023139 A1 US20010023139 A1 US 20010023139A1 US 46963099 A US46963099 A US 46963099A US 2001023139 A1 US2001023139 A1 US 2001023139A1
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- carrier
- substrate
- traces
- seat
- cut out
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- H01L23/4985—Flexible insulating substrates
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- Engineering & Computer Science (AREA)
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- Computer Hardware Design (AREA)
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
Abstract
Description
- The present invention generally relates to semiconductor chip fabrication. More particularly, the present invention relates to a center bond flip chip semiconductor carrier and a method for making and using it to produce a semiconductor device.
- Semiconductor device packaging techniques are well known. In some conventional packaged devices, a die is attached to a carrier, and contacts of each are electrically connected. In one such packaged device called a flip-chip device, a semiconductor chip is flipped and bonded with a carrier such that contacts of the die face and bond to contacts of the carrier.
- With reference to FIGS.1-3, a conventional center bond
flip chip device 10 is shown as including a flippeddie 30 and acarrier 11. Thecarrier 11 has aflexible substrate 12 and anelastomeric cover material 14. Theelastomeric material 14 may be formed of a silicone or a silicone-modified epoxy. Theelastomeric material 14 includes afirst portion 15 and asecond portion 17 of generally equal size. Theflexible substrate 12 is formed of a material exhibiting high temperature stability as well as high mechanical rigidity. Thesubstrate 12 may be a flexible tape, such as, for example, a polyimide tape. Two commercially available polyimide tapes, KAPTON® from E. I. DuPont Nemours and Company and UPILEX® from Ube Industries, Ltd., can be used to form thesubstrate 12. -
Conductive traces flexible substrate 12 and positioned below theelastomeric material 14. Thetraces flexible substrate 12 in a variety of ways, the most preferred method being electrolytic deposition. Other suitable methods include sputter coating and laminating a sheet of conductive material and etching away excess material to form the traces. - A
gap 20 separates the twoportions elastomeric material 14.Conductive lands conductive traces gap 20. The die 30 has been removed from the FIG. 1 for clarity of illustration of thelands gap 20 is rectangularly shaped, although any configured gap will suffice as long as theconductive pads elastomeric material 14. - A die30 is positioned on the
elastomeric material 14 of thecarrier 11. Thecarrier 11 is electrically connected with the die 30 by way of suitable conductive connecting structures, such as, for example, inner lead solder balls orbumps lands Conductive vias traces bumps traces circuit board 35. Preferably, theouter lead balls - Conventional center bond flip chip semiconductor devices have several disadvantages, particularly as die30 sizes decrease and the contacts thereof are positioned closer together. One disadvantage is that
adjacent traces carrier 11 and their associatedconductive lands inner lead balls inner lead balls conductive lands conductive land 18 of thecarrier 11. - There is, therefore, a need for a center bond flip chip semiconductor device design which alleviates to some extent these disadvantages.
- The present invention provides a carrier for a semiconductor device which includes a substrate, at least one conductive trace located on the substrate, the trace including a recessed seat sized and configured to receive a conductive connecting structure, for example, a solder ball, and an elastomeric covering material, the material including a gap in which the conductive connecting structure may be located in the recessed seat to provide a reliable electrical connection of the trace with a flipped semiconductor die.
- The present invention further provides a semiconductor device including a semiconductor die electrically connected to a carrier. The carrier includes at least one conductive trace located on a substrate. The trace includes a recessed seat sized and configured to receive a conductive connecting structure to allow electrical connection of the trace with the semiconductor die.
- The present invention further provides an electronic system which includes a semiconductor die, a carrier and a structure for mounting the carrier. The carrier has a substrate, a plurality of conductive traces located on the substrate, and an elastomeric covering material. Each trace includes a recessed seat having a cut out portion sized and configured to receive a conductive connecting structure. The elastomeric material includes a gap corresponding to the location of the recessed seats to allow electrical connection of the traces with the semiconductor die.
- The present invention further provides a method for making a carrier for a semiconductor die. The method includes locating at least one conductive trace on a substrate, and creating a recessed seated portion on the trace, which recessed seated portion can be used to seat a conductive connecting structure used for interconnecting the carrier to a semiconductor die.
- The present invention further provides a method of making a semiconductor device. The method includes forming a carrier and electrically connecting the carrier with a semiconductor die. The forming includes locating at least one conductive trace on a substrate, creating a recessed seated portion on the trace, and affixing a conductive connecting structure which is coupled to the semiconductor die to the recessed seated portion.
- The foregoing and other advantages and features of the invention will be more readily understood from the following detailed description of the invention, which is provided in connection with the accompanying drawings.
- FIG. 1 is a top view of a conventional center bond flip chip carrier.
- FIG. 2 is a side view of a conventional center bond flip chip semiconductor device incorporating the carrier of FIG. 1.
- FIG. 3 is a cross-sectional view taken along line III-III of FIG. 2.
- FIG. 4 is a top view of a carrier for a center bond flip chip semiconductor device constructed in accordance with an embodiment of the invention.
- FIG. 5 is a cross-sectional view taken along line V-V of the semiconductor device of FIG. 3.
- FIG. 6 is a cross-sectional view taken along line VI-VI of the semiconductor device of FIG. 3.
- FIG. 7 is a cross-sectional view of another carrier for a center bond flip chip semiconductor device constructed in accordance with another embodiment of the invention.
- FIG. 8 is a cross-sectional view taken along line VIII-VIII of the semiconductor device of FIG. 7.
- FIG. 9 is a cross-sectional view of a carrier for a center bond flip chip semiconductor device constructed in accordance with another embodiment of the invention.
- FIG. 10 is a cross-sectional view taken along line X-X of the semiconductor device of FIG. 9.
- FIG. 11 illustrates a processor-based system utilizing a carrier constructed in accordance with an embodiment of the present invention.
- FIG. 12 is a flow diagram of the steps in making the flip chip carrier of FIGS.4-10 and a semiconductor device using the carrier.
- FIG. 13 is a side view of a portion of a flip chip carrier constructed in accordance with another embodiment of the present invention.
- FIG. 14 is a side view of a portion of a flip chip carrier constructed in accordance with another embodiment of the present invention.
- Referring to FIGS.4-6, where like numerals designate like elements, there is shown a
semiconductor device 100, which includes the die 30 and acarrier 111 having theflexible substrate 12 and theelastomeric material 14 with the first andsecond portions - As with the
device 10 in FIGS. 1-3, agap 20 is provided in thedevice 100 between the twoportions elastomeric material 14. Further, electricallyconductive traces flexible substrate 12 below theelastomeric material 14. The conductive traces 116 a, 116 b, 116 c may be included with theflexible substrate 12, or they may be provided subsequently on thesubstrate 12.Seats conductive traces gap 20. The pitch (the distance between eachtrace seats inner lead balls inner lead balls - Each of these cut out portions121 a, 121 b, 121 c provides a recessed seat for the
inner lead balls inner lead balls traces inner lead balls conductive traces carrier 111 will be shorted out by contact of adjacentinner lead balls inner lead balls conductive trace - The ends of the
conductive traces seats seats seats seats inner lead balls conductive traces - FIGS.7-8 show a center bond flip
chip semiconductor device 200 which includes thedie 30 and acarrier 211 with theelastomeric material 14 and theflexible substrate 12. A plurality of recessedseats substrate 12. Each of the recessedseats gap 20 formed between theportion elastomeric material 14. The recessedseats portions lead balls semiconductor device 200 of FIGS. 7-8 is different fromsemiconductor device 100 in FIGS. 4-6 in that the cut outportions portions - FIGS.9-10 show another flip
chip semiconductor device 300 which includes thedie 30 and acarrier 311 having theelastomeric material 14 and theflexible substrate 12.Seats portions lead balls seats elastomeric material 14 and theflexible substrate 12. Thesemiconductor device 300 differs from the devices 100 (FIGS. 4-6) and 200 (FIGS. 7-8) in that the cut outportions flexible substrate 12. - FIG. 13 shows a portion of a flip chip semiconductor device. Specifically, an
outer lead ball 124 c is shown in a via 122 c. In this embodiment, theouter lead ball 124 c is sufficiently large to contact theconductive trace 16 c as well as the printedcircuit board 35. Thus, electroplating of the sides of the via 122 c are not necessary, as theouter lead ball 124 c alone electrically connects theconductive trace 16 c with the printedcircuit board 35 itself. The via 122 c is dimensioned to receive theouter lead ball 124 c. - Alternatively, as shown in FIG. 14, the
outer lead ball 24 c is positioned within a via 222 c. The via 222 c differs from the via 22 c in that the via 222 c lacks electroplating of its sides. Instead, aconductive material 223 is positioned in the via 222 c to provide electrical contact between theouter lead ball 24 c and theconductive trace 16 c. Theconductive material 223 may be formed of a conductive paste or epoxy, or instead a conductive metal such as copper. - Referring now to FIG. 11, next will be described the use of the
carrier system 500. The processor-basedsystem 500 may be a computer system, a process control system or any other system employing a processor and associated memory. Thesystem 500 includes a central processing unit (CPU) 502, which may be a microprocessor. TheCPU 502 communicates with theDRAM 512, which includes the carrier 111 (or thecarrier 211 or 311) over abus 516. TheCPU 502 further communicates with one or more I/O devices bus 516. Although illustrated as a single bus, thebus 516 may be a series of buses and bridges commonly used in a processor-based system. Further components of thesystem 500 include a read only memory (ROM) 514 and peripheral devices such as afloppy disk drive 504, andCD ROM drive 506. Thefloppy disk drive 504 and CD ROM drive 506 communicate with theCPU 502 over thebus 516. - With reference to FIG. 12, next will be described a method for making the
flip chip carriers carriers flexible substrate 12 atstep 400. The conductive traces 116 a, 116 b, 116 c (or 216 a, 216 b, 216 c or 316 a, 316 b, 316 c) may be included with thesubstrate 12, or optionally, they are deposited on thesubstrate 12 atstep 405 by way of electrolytic deposition, sputter coating, laminating a conductive material to thesubstrate 12 and etching away the excess, or other suitable deposition method. The cut out portions 121 a, 121 b, 121 c (or 221 a, 221 b, 221 c or 321 a, 321 b, 321 c) are created within the traces atstep 410 by laser or mechanical drilling or by etching. Atstep 415, theelastomeric material 14 is deposited over thesubstrate 12 and the traces to form thecarriers -
Inner lead balls traces seats step 420. Alternatively, the inner lead balls 19 a) 19 b, 19 c may be affixed to thedie 30. The thus formedcarrier step 425 by bringing the two into contact and melting the solder balls to provide a solid mechanical and electrical contact of the die to the carrier. - Users of the thus manufactured
semiconductor devices circuit board 35 or other common base for mounting of components to form an electronic system. - The present invention provides a flip chip carrier and a semiconductor device employing it which is inhibited from being shorted out by closely spaced interconnected conductors, e.g., solder balls, and which reduces the chance of solder wicking along the electrical traces.
- While the invention has been described in detail in connection with the preferred embodiments known at the time, it should be readily understood that the invention is not limited to such disclosed embodiments. Rather, the invention can be modified to incorporate any number of variations, alterations, substitutions or equivalent arrangements not heretofore described, but which are commensurate with the spirit and scope of the invention. For example, while the description and illustrations depict a center bond flip chip semiconductor device, it is to be understood that the invention is not so limited. Further, while three traces have been shown and described for the
carriers inner lead balls
Claims (80)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/469,630 US6413102B2 (en) | 1999-12-22 | 1999-12-22 | Center bond flip chip semiconductor carrier and a method of making and using it |
US09/680,473 US6647620B1 (en) | 1999-12-22 | 2000-10-06 | Method of making center bond flip chip semiconductor carrier |
US10/667,391 US7091065B2 (en) | 1999-12-22 | 2003-09-23 | Method of making a center bond flip chip semiconductor carrier |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/469,630 US6413102B2 (en) | 1999-12-22 | 1999-12-22 | Center bond flip chip semiconductor carrier and a method of making and using it |
Related Child Applications (1)
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US09/680,473 Division US6647620B1 (en) | 1999-12-22 | 2000-10-06 | Method of making center bond flip chip semiconductor carrier |
Publications (2)
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US20010023139A1 true US20010023139A1 (en) | 2001-09-20 |
US6413102B2 US6413102B2 (en) | 2002-07-02 |
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US09/469,630 Expired - Lifetime US6413102B2 (en) | 1999-12-22 | 1999-12-22 | Center bond flip chip semiconductor carrier and a method of making and using it |
US09/680,473 Expired - Lifetime US6647620B1 (en) | 1999-12-22 | 2000-10-06 | Method of making center bond flip chip semiconductor carrier |
US10/667,391 Expired - Fee Related US7091065B2 (en) | 1999-12-22 | 2003-09-23 | Method of making a center bond flip chip semiconductor carrier |
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US09/680,473 Expired - Lifetime US6647620B1 (en) | 1999-12-22 | 2000-10-06 | Method of making center bond flip chip semiconductor carrier |
US10/667,391 Expired - Fee Related US7091065B2 (en) | 1999-12-22 | 2003-09-23 | Method of making a center bond flip chip semiconductor carrier |
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US (3) | US6413102B2 (en) |
Cited By (3)
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US20090166396A1 (en) * | 2007-12-28 | 2009-07-02 | Lakshmi Supriya | Microball attachment using self-assembly for substrate bumping |
US20100207266A1 (en) * | 2009-02-16 | 2010-08-19 | Industrial Technology Research Institute | Chip package structure |
US20110061910A1 (en) * | 2009-09-16 | 2011-03-17 | Samsung Electro-Mechanics Co., Ltd. | Multi-layer ceramic circuit board, method of manufacturing the same, and electric device module using the same |
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JP3822040B2 (en) * | 2000-08-31 | 2006-09-13 | 株式会社ルネサステクノロジ | Electronic device and manufacturing method thereof |
US7115986B2 (en) * | 2001-05-02 | 2006-10-03 | Micron Technology, Inc. | Flexible ball grid array chip scale packages |
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SG115456A1 (en) * | 2002-03-04 | 2005-10-28 | Micron Technology Inc | Semiconductor die packages with recessed interconnecting structures and methods for assembling the same |
US6975035B2 (en) * | 2002-03-04 | 2005-12-13 | Micron Technology, Inc. | Method and apparatus for dielectric filling of flip chip on interposer assembly |
SG115455A1 (en) * | 2002-03-04 | 2005-10-28 | Micron Technology Inc | Methods for assembly and packaging of flip chip configured dice with interposer |
SG121707A1 (en) | 2002-03-04 | 2006-05-26 | Micron Technology Inc | Method and apparatus for flip-chip packaging providing testing capability |
US20040036170A1 (en) * | 2002-08-20 | 2004-02-26 | Lee Teck Kheng | Double bumping of flexible substrate for first and second level interconnects |
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US5691041A (en) * | 1995-09-29 | 1997-11-25 | International Business Machines Corporation | Socket for semi-permanently connecting a solder ball grid array device using a dendrite interposer |
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US5880590A (en) * | 1997-05-07 | 1999-03-09 | International Business Machines Corporation | Apparatus and method for burn-in and testing of devices with solder bumps or preforms |
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-
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Cited By (4)
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US20090166396A1 (en) * | 2007-12-28 | 2009-07-02 | Lakshmi Supriya | Microball attachment using self-assembly for substrate bumping |
US7651021B2 (en) * | 2007-12-28 | 2010-01-26 | Intel Corporation | Microball attachment using self-assembly for substrate bumping |
US20100207266A1 (en) * | 2009-02-16 | 2010-08-19 | Industrial Technology Research Institute | Chip package structure |
US20110061910A1 (en) * | 2009-09-16 | 2011-03-17 | Samsung Electro-Mechanics Co., Ltd. | Multi-layer ceramic circuit board, method of manufacturing the same, and electric device module using the same |
Also Published As
Publication number | Publication date |
---|---|
US6413102B2 (en) | 2002-07-02 |
US6647620B1 (en) | 2003-11-18 |
US7091065B2 (en) | 2006-08-15 |
US20040057222A1 (en) | 2004-03-25 |
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