EP1983679A3 - Clock regeneration circuit - Google Patents

Clock regeneration circuit Download PDF

Info

Publication number
EP1983679A3
EP1983679A3 EP08102173.5A EP08102173A EP1983679A3 EP 1983679 A3 EP1983679 A3 EP 1983679A3 EP 08102173 A EP08102173 A EP 08102173A EP 1983679 A3 EP1983679 A3 EP 1983679A3
Authority
EP
European Patent Office
Prior art keywords
signal
level
xor
bit
outputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP08102173.5A
Other languages
German (de)
French (fr)
Other versions
EP1983679A2 (en
Inventor
Hideaki c/o Oki Electric Industry Co. Ltd. Tamai
Masayuki c/o Oki Electric Industry Co. Ltd. Kashima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Publication of EP1983679A2 publication Critical patent/EP1983679A2/en
Publication of EP1983679A3 publication Critical patent/EP1983679A3/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0002—Multistate logic
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4917—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0087—Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection

Abstract

A clock regeneration circuit includes a half-bit delay device that outputs a half-bit delayed signal B of a multi-level input signal A, a one-bit delay device that outputs a one-bit delayed signal C of the signal A, an adder, an attenuator that forms an threshold signal, an XOR circuit, and a BPF that outputs a clock signal with a frequency corresponding to a bit rate of the XOR signal. The XOR signal is calculated as an XOR of a two-level input signal F, which is a logical zero when a level of the signal A is no more than a level of the threshold signal and otherwise is a logical one, and a two-level input signal G, which is a logical zero when a level of the signal B is no more than the level of the threshold signal and otherwise is a logical one.
EP08102173.5A 2007-04-18 2008-02-29 Clock regeneration circuit Withdrawn EP1983679A3 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007108839A JP4992526B2 (en) 2007-04-18 2007-04-18 Clock recovery circuit

Publications (2)

Publication Number Publication Date
EP1983679A2 EP1983679A2 (en) 2008-10-22
EP1983679A3 true EP1983679A3 (en) 2016-07-13

Family

ID=39612243

Family Applications (1)

Application Number Title Priority Date Filing Date
EP08102173.5A Withdrawn EP1983679A3 (en) 2007-04-18 2008-02-29 Clock regeneration circuit

Country Status (4)

Country Link
US (1) US7564286B2 (en)
EP (1) EP1983679A3 (en)
JP (1) JP4992526B2 (en)
CN (1) CN101291210A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010101222A1 (en) * 2009-03-05 2010-09-10 日本電気株式会社 Receiver, semiconductor device, and signal transmission method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4339823A (en) * 1980-08-15 1982-07-13 Motorola, Inc. Phase corrected clock signal recovery circuit
EP0530776A2 (en) * 1991-09-03 1993-03-10 Matsushita Electric Industrial Co., Ltd. Timing recovering apparatus and automatic slice apparatus including the same
US20020067786A1 (en) * 1997-10-20 2002-06-06 Hiroaki Tomofuji Timing circuit

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5728448A (en) * 1980-07-29 1982-02-16 Fujitsu Ltd Timing extraction system
JPS57147351A (en) * 1981-03-06 1982-09-11 Nec Corp Timing extractor
JPH036541A (en) * 1989-06-02 1991-01-14 Matsushita Electric Ind Co Ltd Clock extracting device
JPH0570044A (en) 1991-09-11 1993-03-23 Hitachi Ltd Safety device for home elevator
JPH0570044U (en) 1992-02-28 1993-09-21 株式会社アドバンテスト Clock recovery circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4339823A (en) * 1980-08-15 1982-07-13 Motorola, Inc. Phase corrected clock signal recovery circuit
EP0530776A2 (en) * 1991-09-03 1993-03-10 Matsushita Electric Industrial Co., Ltd. Timing recovering apparatus and automatic slice apparatus including the same
US20020067786A1 (en) * 1997-10-20 2002-06-06 Hiroaki Tomofuji Timing circuit

Also Published As

Publication number Publication date
EP1983679A2 (en) 2008-10-22
US7564286B2 (en) 2009-07-21
CN101291210A (en) 2008-10-22
JP2008270994A (en) 2008-11-06
JP4992526B2 (en) 2012-08-08
US20080258786A1 (en) 2008-10-23

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