EP1958261A1 - Transistor de type i-mos comportant deux grilles independantes, et procede d'utilisation d'un tel transistor - Google Patents
Transistor de type i-mos comportant deux grilles independantes, et procede d'utilisation d'un tel transistorInfo
- Publication number
- EP1958261A1 EP1958261A1 EP06841838A EP06841838A EP1958261A1 EP 1958261 A1 EP1958261 A1 EP 1958261A1 EP 06841838 A EP06841838 A EP 06841838A EP 06841838 A EP06841838 A EP 06841838A EP 1958261 A1 EP1958261 A1 EP 1958261A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- intermediate zone
- grid
- transistor
- drain
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
- 238000000034 method Methods 0.000 title claims description 6
- 230000005684 electric field Effects 0.000 claims abstract description 23
- 239000004065 semiconductor Substances 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 2
- 239000002800 charge carrier Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
- H01L27/1057—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components comprising charge coupled devices [CCD] or charge injection devices [CID]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7391—Gated diode structures
Definitions
- I-MOS type transistor comprising two independent gates, and method of using such a transistor
- the invention relates to an I-MOS type transistor comprising a source, constituted by a first zone doped by a first doping type, a drain, constituted by a second zone doped by a second doping type, and an intermediate zone of low doping disposed between the source and the drain, the intermediate zone forming first and second junctions respectively with the source and with the drain, the transistor comprising a first gate for generating an electric field in the intermediate zone, on the side of the first junction.
- the document WO2004 / 001801 describes an MOS (metal / oxide / semiconductor) transistor comprising a structure of the PIN type.
- This PIN structure comprises an intermediate zone (I), semiconductor and of low doping, either n " or p " , disposed between a doped zone P and a doped zone N.
- the intermediate zone I forms a first semiconductor junction PI with the P doped zone and a second semiconductor junction IN with the second zone.
- An insulated grid makes it possible to apply an electric field closer to one of the two junctions than to the other junction. The electric field causes the transistor to switch between a blocked state and a conductive state. In the conductive state, an avalanche breakdown occurs in the intermediate zone I.
- a PIN diode is thus obtained, the avalanche voltage of which can be controlled by the gate.
- the abrupt transition from a blocked regime to a passing regime is obtained through impact ionization phenomena.
- the transistor obtained is also called an I-MOS transistor (impact ionization MOSFET).
- the current-voltage characteristic (I-V) of an I-MOS transistor has a very low value of the inverse of the slope below the threshold, of the order of 5 to 10 mV per decade.
- the document WO2004 / 001801 proposes applications of the I-MOS transistor such as, for example, a memory cell or an inverter having a shorter switching time than CMOS type devices.
- I-MOS transistors A method for manufacturing I-MOS transistors is described in the article "Impact lonization MOS (l-MOS) -Part-ll: Experimental Results” by K. Gopalakrishnan et al. (IEEE Transactions on Electron Devices, volume 52, p.77-84, 2005).
- the invention aims to improve the I-MOS type transistors, more particularly to allow the realization of additional electronic and logic functions.
- This object is achieved by a transistor according to the appended claims and more particularly by the fact that the transistor has a second gate for generating an electric field in the intermediate zone on the side of the second junction.
- the object of the invention is also a method of using a transistor according to the invention, comprising:
- Figures 1 to 4 show, in section, four particular embodiments of a transistor according to the invention.
- Figures 5 and 6 show, respectively in top view and in section along the axis AA, a fifth particular embodiment of the transistor according to the invention.
- FIG. 7 illustrates a particular embodiment of the transistor according to the invention and of its operation.
- an I-MOS type transistor impact ionization MOSFET
- a first semiconductor zone 1 doped with a first type of doping, for example P +
- a second semiconductor zone 2 doped with a second type of doping, for example N +.
- the first type and the second type of doping are opposite.
- the first zone 1 and the second zone 2 thus constitute respectively source (1) and drain (2) electrodes of the transistor.
- An intermediate zone I also called intrinsic zone of low doping, for example of n or p type, is disposed between the first and second zones.
- the intermediate zone I forms first (3) and second (4) junctions, respectively with the first zone 1 and with the second zone 2, thus constituting a PIN diode.
- a first grid 5 makes it possible to generate an electric field in the intermediate zone I, on the side of the first junction 3.
- a second grid 6 makes it possible to generate an electric field in the intermediate zone I, on the side of the second junction 4.
- the grids 5 and 6 are separated from the intermediate zone I by respective insulating layers 7.
- the lengths L 0 of the two grids are preferably of the same order of magnitude.
- the first grid 5 is arranged on a front face of the intermediate zone I and the second grid 6 is arranged on a rear face of the intermediate zone I.
- the grids 5 and 6 are integrated in the intermediate zone I so that each grid 5 and 6 forms a common flat face with the intermediate zone I. This has the advantage of obtaining the impact ionization effect not only on the surface but also in the volume of the intermediate zone I.
- the first grid 5 and the second grid 6 are arranged on the same face of the intermediate zone I.
- the grids 5 and 6 can partially cover the associated doped zone 1 and 2.
- each grid generates an electric field in the intermediate zone I, on the side of the corresponding junction.
- the gates are offset with respect to a transverse median axis T ( Figure 4) of the transistor.
- the first grid 5 is offset in the direction of the first junction 3 and the second grid 6 is offset in the direction of the second junction 4.
- the electric field of each grid is therefore essentially located in a region of the intermediate zone I closer from the corresponding junction as from the opposite junction.
- the PIN diode is thus controlled by one of the grids, which partially covers the area intermediate between the source (P-doped area) and the drain (N-doped area) and which is close to the source (P-type I-MOS) or the drain (N-type I-MOS).
- an I-MOS type transistor works like a switch. Indeed, depending on the polarization of the gate, the transistor is on (high current between the drain and the source) or blocked (very low current between the drain and the source).
- the transistor obtained can also be considered as a transistor with two independent gates having distinct effects.
- the conduction channels generated by the grids are independent.
- the transistor therefore has four independent electrodes: source (1), drain (2), first gate 5 and second gate 6.
- the gate voltage Vg 1 of the first gate 5 and the gate voltage Vg2 of the second gate 6 have not exceeded the threshold voltages Vt1 and Vt2 respectively, the total current is substantially zero.
- the gate voltage of the other gate being maintained at OV, the transistor behaves like a conventional I-MOS transistor corresponding to the modulated gate.
- the use of the two gates however makes it possible to obtain the superposition of two I-MOS transistors of opposite polarizations, that is to say of an NI-MOS transistor and of a PI-MOS transistor.
- the PI-MOS transistor has a negative threshold voltage and is blocked for gate voltages greater than its threshold voltage
- the NI-MOS transistor has a positive threshold voltage and is blocked for voltages grid lower than its threshold voltage.
- the total current It is the sum of individual currents 11 and 12 corresponding respectively to the first junction 3 and to the second junction 4, 11 and 12 being positive.
- the truth table of such a transistor has four conduction states:
- the impact ionization phenomenon occurs when the electric field in the intermediate zone I is greater than the critical field Ec.
- the supply voltages are fixed and this imposes a maximum value that the critical field Ec must not exceed.
- the semiconductor material used for the intermediate zone I can then be chosen, in particular, as a function of the critical field Ec.
- a source-drain voltage V D is applied. S between the first (1) and second (2) doped zones, so that a corresponding electric field, generated in the intermediate zone I, is less than the critical impact ionization field Ec of the semiconductor material used . A source-drain voltage V D is applied. S positive between the drain (2) and the source (1) -
- a grid voltage is applied to one of the grids, for example a first grid voltage Vg1 on the first grid 5, as illustrated in FIG. 1.
- the grid voltage Vg1 creates a conductive inversion channel 8 near the first gate 5, so that the source-drain voltage
- V D. S falls over a distance d shorter than an initial length L of the intermediate zone I.
- the corresponding electric field is thus greater than the critical field Ec.
- the critical field Ec impact ionization occurs and the triggering of the avalanche causes the transistor to go from a blocked state to a passing state.
- the second grid 6 operates in a similar manner. We can thus establish the current 11 or the current 12 mentioned in the truth table above.
- a first gate voltage Vg1 is applied to the first gate 5 greater in absolute value than the first threshold voltage Vt1.
- a second gate voltage Vg2 is applied to the second gate 6, greater in absolute value than the second threshold voltage Vt2.
- two inversion channels 8 conductors are created, respectively near the first and second gates (5, 6), so that the source-drain voltage V D. S falls, for each grid, over a distance d shorter than an initial length L of the intermediate zone I (FIG. 1), the corresponding electric field being greater than the critical field Ec.
- Ec is the critical field.
- the voltage on the gate must create an inversion channel of the same type as the corresponding doped area, that is to say the closest source or drain area. For example, for a gate close to an N-type drain (NI-MOS), a positive voltage is applied. For a gate close to a P-type source (PI-MOS), a negative voltage is applied.
- NI-MOS N-type drain
- PI-MOS P-type source
- the grids 5 and 6 partially envelop the intermediate zone I.
- the grids are arranged on a front face of the intermediate zone I and on lateral flanks of the intermediate zone I, while by being isolated from the intermediate zone by respective insulating layers 7.
- the first gate 5 and the second gate 6 are arranged on the same face of the transistor, advantageously on the front face, which facilitates their production compared to the other embodiments.
- the grids 5 and 6 can partially cover the doped zones 1 and 2 associated in the embodiments corresponding to FIGS. 2, 3, 5 and 6.
- the respective values of the gate length L Gl of the distance L between the source and the drain and of the thickness e of the semiconductor film, preferably in Si, Ge or SiGe, in which are formed the source, the drain and the intermediate zone of the transistor can be the following:
Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0512358A FR2894386B1 (fr) | 2005-12-06 | 2005-12-06 | Transistor de type i-mos comportant deux grilles independantes, et procede d'utilisation d'un tel transistor |
PCT/FR2006/002628 WO2007065985A1 (fr) | 2005-12-06 | 2006-12-01 | Transistor de type i-mos comportant deux grilles independantes, et procede d'utilisation d'un tel transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
EP1958261A1 true EP1958261A1 (fr) | 2008-08-20 |
Family
ID=36830769
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP06841838A Ceased EP1958261A1 (fr) | 2005-12-06 | 2006-12-01 | Transistor de type i-mos comportant deux grilles independantes, et procede d'utilisation d'un tel transistor |
Country Status (4)
Country | Link |
---|---|
US (1) | US7732282B2 (fr) |
EP (1) | EP1958261A1 (fr) |
FR (1) | FR2894386B1 (fr) |
WO (1) | WO2007065985A1 (fr) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103688362B (zh) * | 2011-07-22 | 2017-03-29 | 国际商业机器公司 | 隧道场效应晶体管 |
EP2568506A1 (fr) * | 2011-09-09 | 2013-03-13 | Imec | Transistor à effet tunnel, porte logique comprenant le transistor, mémoire statique à accès aléatoire utilisant la porte logique et procédé de fabrication d'un tel transistor à effet tunnel |
KR20140078326A (ko) * | 2012-12-17 | 2014-06-25 | 경북대학교 산학협력단 | 터널링 전계효과 트랜지스터 및 터널링 전계효과 트랜지스터의 제조 방법 |
JP5784652B2 (ja) * | 2013-02-14 | 2015-09-24 | 株式会社東芝 | 半導体装置 |
US9287406B2 (en) | 2013-06-06 | 2016-03-15 | Macronix International Co., Ltd. | Dual-mode transistor devices and methods for operating same |
JP6083707B2 (ja) * | 2013-09-09 | 2017-02-22 | 国立研究開発法人産業技術総合研究所 | 半導体装置およびその製造方法 |
US9685528B2 (en) * | 2015-06-30 | 2017-06-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin semiconductor device and method of manufacture with source/drain regions having opposite conductivities |
CN110444585B (zh) * | 2019-08-19 | 2023-06-09 | 上海华力微电子有限公司 | 一种栅控P-i-N二极管及其制造方法 |
CN110504325B (zh) * | 2019-08-29 | 2023-06-02 | 上海华力微电子有限公司 | 一种新型栅控P-i-N二极管ESD器件及其实现方法 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020117689A1 (en) * | 2001-02-28 | 2002-08-29 | Hajime Akimoto | Field effect transistor and image display apparatus using the same |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0425175A (ja) * | 1990-05-21 | 1992-01-28 | Canon Inc | ダイオード |
TW273039B (fr) * | 1993-02-16 | 1996-03-21 | At & T Corp | |
JPH09213921A (ja) * | 1996-02-05 | 1997-08-15 | Sharp Corp | 増幅型固体撮像素子及び増幅型固体撮像装置 |
DE19848596C2 (de) * | 1998-10-21 | 2002-01-24 | Roland Sittig | Halbleiterschalter mit gleichmäßig verteilten feinen Steuerstrukturen |
DE10029501C1 (de) * | 2000-06-21 | 2001-10-04 | Fraunhofer Ges Forschung | Vertikal-Transistor mit beweglichen Gate und Verfahren zu dessen Herstelllung |
DE10217610B4 (de) * | 2002-04-19 | 2005-11-03 | Infineon Technologies Ag | Metall-Halbleiter-Kontakt, Halbleiterbauelement, integrierte Schaltungsanordnung und Verfahren |
AU2003258948A1 (en) * | 2002-06-19 | 2004-01-06 | The Board Of Trustees Of The Leland Stanford Junior University | Insulated-gate semiconductor device and approach involving junction-induced intermediate region |
FR2884052B1 (fr) * | 2005-03-30 | 2007-06-22 | St Microelectronics Crolles 2 | Transistor imos |
DE102006022126B4 (de) * | 2006-05-11 | 2015-04-09 | Infineon Technologies Ag | Verfahren zum Herstellen eines elektronischen Bauelementes |
FR2912838B1 (fr) * | 2007-02-15 | 2009-06-05 | Commissariat Energie Atomique | Procede de realisation de grille de transistor |
US20090072279A1 (en) * | 2007-08-29 | 2009-03-19 | Ecole Polytechnique Federale De Lausanne (Epfl) | Capacitor-less memory and abrupt switch based on hysteresis characteristics in punch-through impact ionization mos transistor (PI-MOS) |
WO2009058695A2 (fr) * | 2007-10-30 | 2009-05-07 | Northrop Grumman Systems Corporation | Transistor à ionisation par choc froid et son procédé de fabrication |
-
2005
- 2005-12-06 FR FR0512358A patent/FR2894386B1/fr not_active Expired - Fee Related
-
2006
- 2006-12-01 US US12/085,866 patent/US7732282B2/en not_active Expired - Fee Related
- 2006-12-01 WO PCT/FR2006/002628 patent/WO2007065985A1/fr active Application Filing
- 2006-12-01 EP EP06841838A patent/EP1958261A1/fr not_active Ceased
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020117689A1 (en) * | 2001-02-28 | 2002-08-29 | Hajime Akimoto | Field effect transistor and image display apparatus using the same |
Non-Patent Citations (1)
Title |
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See also references of WO2007065985A1 * |
Also Published As
Publication number | Publication date |
---|---|
WO2007065985A1 (fr) | 2007-06-14 |
US20090096028A1 (en) | 2009-04-16 |
FR2894386B1 (fr) | 2008-02-29 |
FR2894386A1 (fr) | 2007-06-08 |
US7732282B2 (en) | 2010-06-08 |
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