EP1402328A2 - Stromquellenschaltung - Google Patents
StromquellenschaltungInfo
- Publication number
- EP1402328A2 EP1402328A2 EP02704588A EP02704588A EP1402328A2 EP 1402328 A2 EP1402328 A2 EP 1402328A2 EP 02704588 A EP02704588 A EP 02704588A EP 02704588 A EP02704588 A EP 02704588A EP 1402328 A2 EP1402328 A2 EP 1402328A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- current
- transistor
- current source
- source circuit
- control device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
- G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
Definitions
- the present invention relates to a device according to the preamble of claim 1, i.e. a power source circuit.
- Figures 1A, IB, and IC show different embodiments of such an arrangement.
- the mentioned differential pair consists of transistors TU, T12, and the foot current source consists of a transistor T2.
- the foot current source supplies a foot current IT, also referred to as tail current, to the common source node of the differential pair.
- the magnitude of this current (the magnitude of a voltage VB2 controlling the transistor T2) is usually generated via a transistor T2D connected as a diode and a current source IQ.
- the drain connection of the differential pair can consist, for example, of load resistors R1, R2 (FIG. 1A), a so-called folded cascode (FIG. IB) or any other circuit (FIG. IC).
- a significant disadvantage of arrangements of this type is the dependency of the tail current IT on the common-mode modulation of the differential pair at its inputs E + (gate connection of the transistor TU) and E- (gate connection of the transistor T12). This is due to the finite initial conductance of the Transistor T2, which can be very large, especially in contemporary CMOS processes with a channel length of 0.12 ⁇ m, so that there are strong fluctuations in IT.
- the conditions occurring at the common source node are also influenced from the drain side of the transistors TU and T12, namely by finite output conductance values from TU, T12, or by typical short-channel effects such as DIBL. These influences can be remedied by known measures such as drain-side cascodes (see for example Figure IB).
- the foot current source T2 could also be cascoded (see FIG. IC; cascode transistor T4), but such a measure restricts the common-mode modulation range at E +, E-, since another drain-source saturation voltage (the drain-source saturation voltage of T4) is accommodated must be, and this is often no longer feasible, especially at low supply voltages of typically 1.2 V or less.
- the present invention is therefore based on the object of finding a possibility by means of which common-mode control errors in the foot current source of differential pairs or other electrical circuits can be minimized without restricting the possible uses.
- the current source circuit contains a control device (T2 1 , TU ', T12', T6, IQl, IQ2) which determines the size of the current delivered by the current source circuit controls tuning component (T2) of the current source circuit, and - that the control takes place depending on the conditions prevailing in the unit supplied with current by the current source circuit.
- a control device T2 1 , TU ', T12', T6, IQl, IQ2
- Figures la, lb, and lc different known embodiments of an arrangement containing a differential pair and a foot current source for the differential pair
- FIG. 2a shows the structure of an arrangement containing a differential pair and a current source circuit described in more detail below
- FIG. 2b shows the structure of the arrangement shown in FIG. 2a in the event that another circuit is provided instead of the differential pair
- Figure 7 is an illustration of the currents generated by conventional current source circuits and one of those below current source circuits described in more detail are output under various conditions.
- the arrangement shown in FIG. 2a contains a circuit to be supplied with current and a current source circuit which supplies this circuit with current, the current source circuit consisting of a component which determines the size of the output current and a control device which controls this component.
- the circuit to be supplied with current is in the figure
- FIG. 2a shows a differential pair consisting of transistors TU and T12 with any drain connection, but, as will be explained later with the aid of examples, it can also be any other circuit.
- the component of the current source circuit which determines the size of the output current is a transistor T2 connected on the drain side to the common source node of the transistors TU and T12 and on the source side to a supply voltage VSS; In the following, this transistor is also sometimes referred to as foot current source transistor T2.
- the control device controlling this transistor T2 is a control circuit designated FKS in the figures, which in the example shown in FIG. 2a comprises a first current source IQ1, a second current source IQ2, and transistors T6, T2 ', and TU'.
- the transistor T2 1 is a replica transistor, on which the common source potential Vs of the differential pair, which is also the drain potential of the foot current source transistor T2, is mapped to a replica transistor T2 '. Diening takes place via the transistor 'TU' connected in series with T2 '(or more transistors connected in series with T2'). The gate of the transistor TU 1 is driven so that the drain potentials Vs of T2 and Vs 'of T2' are largely the same.
- the drain-side output current of the series circuit comprising T2 'and TU' thus largely corresponds to the tail current IT of the differential pair, ie it is a replica of the same, possibly scaled with a constant factor which results from the scaling of the transistor widths.
- the replicated current is IT / 2, for example, if the width of TU is the same as the width of TU 1 , but T2 is twice as large as T2 ', with the same length of the transistors.
- This ratio 1: 2 can be changed by varying the transistor geometries. What is important for the best possible replication of the potential Vs to Vs 'are only the same current densities in the transistor pairs T2, T2' and TU, TU *.
- the already mentioned first current source IQ1 supplies the control circuit with a current which corresponds to the sum of the setpoint value IS of the foot current, possibly scaled by a factor, selected here as IS / 2, for example, and the working current IB of the control circuit. Its operating current IB is withdrawn from the control loop via the second current source IQ2.
- the gate potential VB2 at the common gate connection of T2 and T2 1 increases when the replicated current IT / 2 is smaller than the target current IS / 2, and decreases when it is larger. This • regulation law regulates the gate potential VB2 so that the tail current IT corresponds to the target current IS.
- the circuit topology allows very high bandwidths and is generally stable without further measures, the gate-source capacitances of T2 and T2 'acting as compensation capacitors.
- connection of the gate connection from TU 'to one of the inputs E +, E- of the differential pair is sufficient to transmit the three-potential Vs from T2 as Vs' to the drain from T2'.
- control loop variant according to FIG. 2a is preferably used in cases in which the differential pair is always in equilibrium in the steady state.
- FIG. 6 Another variant of the current control loop is shown in FIG. 6, which will be described in more detail later.
- This variant contains two control transistors TU 1 , T12 'for the replication of the drain potential Vs, so that both inputs E +, E- of the differential pair are included in the control.
- This control loop variant is preferred if the differential pair is not always operated in equilibrium. This is the case, for example, with fast analog-digital converters of the flash or folding type.
- FIG. 3 shows an example of a practical implementation of the current control loop according to the invention without ideal current sources IQ1, IQ2.
- the current source IQ1 from FIGS. 2a, 2b, 6 is implemented by a transistor T7, which forms a current mirror together with a transistor T7 '.
- a cascode transistor T6' is connected in series with T7 *, which preferably has the same current density as the cascode transistor T6 in the current control loop.
- the cascode transistors T6, T6 * are supplied with a gate potential VB6, which sets the operating point of the cascode.
- the current source IQ2 from FIGS. 2a, 2b, 6 is implemented by a transistor T8.
- the working current IB and the scaled nominal current IS / 2 are supplied to the circuit via two terminals Kl, K2 and further current mirrors, T8 '', T8 ', T8 and T9', T9.
- the IB and IS / 2 for the current source IQ1, that is to say transistor T7, are summed at the common gate connection of the transistors T7, T7 '.
- This implementation example for the current control circuit according to the invention has the disadvantage that the current mirrors at the terminals K1, K2 are not cascode. For lower requirements, however, it is often possible in practice to ensure by suitable dimensioning of T2 1 and T8 that the gate potential of T8 ", T8 ', T8 is approximately as large as the potential VB2. This at least eliminates the error by finite Output conductivities of the transistors T8 ", T8 ', T8 alleviated.
- FIG. 4 shows an example of a circuit suitable for higher accuracy requirements, which can be seen in FIG. 3 if the current mirrors connected to terminals K1 and K2 are also cascoded.
- the transistors T10, T10 1 which are connected in series to the transistors T9, T9 ', and the transistors T13, T13', T13 ' 1 , which are connected in series to the transistors T8, T8', T8 '', are used for this purpose
- a gate potential VB10 is supplied to the gate connections of T10, T10 'in order to set the operating point of the cascode.
- the gate potential VB13 supplied to the gate connections of T13, T13 1 , T13 '* has the same purpose.
- the modulation range of the potential VB2 is somewhat narrower than with the circuit according to FIG. 3, but today's CMOS processes usually provide a sufficient selection of threshold voltages to suitably implement the gate-source voltage of T2. In CMOS processes with separate troughs, it is also possible to make the threshold voltages adjustable by means of a corresponding pretensioning of the trough, and here the circuit according to FIG. 4 is generally problem-free since the control of VB2 by the nominal value due to the amplification of the loop is only minor.
- FIG. 5 shows an example of a further implementation variant of the circuit according to the invention, in which the current source IQ1 is implemented by transistors T7 and T14 connected in parallel.
- T7 supplies the working current IB to the control loop, while T14 supplies the scaled target current IS / 2.
- the current source circuit described is an error compensated current source based on replication of the error in a current control loop. It enables a high performance of the current source without cascoding the current source transistor.
- T2D as a diode-switched transistor to generate VB2
- T41, T42 cascode transistors of a "Folded Cascode"
- T7 current source transistor for realizing IQl ⁇ 7 ⁇ transistor in the bias circuit with current density like T7
Abstract
Description
Claims
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10102443 | 2001-01-19 | ||
DE10102443A DE10102443A1 (de) | 2001-01-19 | 2001-01-19 | Stromquellenschaltung |
PCT/DE2002/000111 WO2002057864A2 (de) | 2001-01-19 | 2002-01-16 | Stromquellenschaltung |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1402328A2 true EP1402328A2 (de) | 2004-03-31 |
EP1402328B1 EP1402328B1 (de) | 2016-01-13 |
Family
ID=7671168
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP02704588.9A Expired - Lifetime EP1402328B1 (de) | 2001-01-19 | 2002-01-16 | Stromquellenschaltung |
Country Status (4)
Country | Link |
---|---|
US (1) | US6885220B2 (de) |
EP (1) | EP1402328B1 (de) |
DE (1) | DE10102443A1 (de) |
WO (1) | WO2002057864A2 (de) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7425862B2 (en) * | 2004-08-10 | 2008-09-16 | Avago Technologies Ecbu Ip (Singapore) Pte Ltd | Driver circuit that employs feedback to enable operation of output transistor in triode region and saturation region |
ITMI20041671A1 (it) * | 2004-08-26 | 2004-11-26 | Atmel Corp | "sistema e metodo e apparecchio per conservare un margine di errore per una memoria non volatile" |
DE102006014655A1 (de) * | 2006-03-28 | 2007-10-11 | Micronas Gmbh | Kaskoden-Spannungs-Erzeugung |
US20070229150A1 (en) * | 2006-03-31 | 2007-10-04 | Broadcom Corporation | Low-voltage regulated current source |
CN114020089B (zh) * | 2021-11-02 | 2022-12-06 | 苏州中科华矽半导体科技有限公司 | 一种适用于低电流增益型npn三极管的带隙基准电压源 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0244413A (ja) * | 1988-08-05 | 1990-02-14 | Nec Corp | 定電流供給回路 |
JP2705169B2 (ja) * | 1988-12-17 | 1998-01-26 | 日本電気株式会社 | 定電流供給回路 |
DE69118693T2 (de) * | 1991-09-25 | 1996-11-28 | Bell Telephone Mfg | Differenzverstärkeranordnung |
US5306964A (en) * | 1993-02-22 | 1994-04-26 | Intel Corporation | Reference generator circuit for BiCMOS ECL gate employing PMOS load devices |
US5552724A (en) * | 1993-09-17 | 1996-09-03 | Texas Instruments Incorporated | Power-down reference circuit for ECL gate circuitry |
US5682108A (en) * | 1995-05-17 | 1997-10-28 | Integrated Device Technology, Inc. | High speed level translator |
US5767699A (en) * | 1996-05-28 | 1998-06-16 | Sun Microsystems, Inc. | Fully complementary differential output driver for high speed digital communications |
US5986479A (en) * | 1997-05-05 | 1999-11-16 | National Semiconductor Corporation | Fully switched, class-B, high speed current amplifier driver |
US6040720A (en) * | 1998-06-12 | 2000-03-21 | Motorola, Inc. | Resistorless low-current CMOS voltage reference generator |
US6094074A (en) * | 1998-07-16 | 2000-07-25 | Seiko Epson Corporation | High speed common mode logic circuit |
-
2001
- 2001-01-19 DE DE10102443A patent/DE10102443A1/de not_active Ceased
-
2002
- 2002-01-16 WO PCT/DE2002/000111 patent/WO2002057864A2/de active Application Filing
- 2002-01-16 EP EP02704588.9A patent/EP1402328B1/de not_active Expired - Lifetime
-
2003
- 2003-07-21 US US10/623,846 patent/US6885220B2/en not_active Expired - Fee Related
Non-Patent Citations (1)
Title |
---|
See references of WO02057864A3 * |
Also Published As
Publication number | Publication date |
---|---|
US6885220B2 (en) | 2005-04-26 |
EP1402328B1 (de) | 2016-01-13 |
US20040017249A1 (en) | 2004-01-29 |
DE10102443A1 (de) | 2002-08-01 |
WO2002057864A3 (de) | 2004-01-15 |
WO2002057864A2 (de) | 2002-07-25 |
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