EP1282134A3 - Dual bank flash memory device and method - Google Patents

Dual bank flash memory device and method Download PDF

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Publication number
EP1282134A3
EP1282134A3 EP02255372A EP02255372A EP1282134A3 EP 1282134 A3 EP1282134 A3 EP 1282134A3 EP 02255372 A EP02255372 A EP 02255372A EP 02255372 A EP02255372 A EP 02255372A EP 1282134 A3 EP1282134 A3 EP 1282134A3
Authority
EP
European Patent Office
Prior art keywords
memory device
memory
dual bank
bank
flash memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP02255372A
Other languages
German (de)
French (fr)
Other versions
EP1282134A2 (en
Inventor
Luca Giovanni Fasoli
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
STMicroelectronics lnc USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics lnc USA filed Critical STMicroelectronics lnc USA
Publication of EP1282134A2 publication Critical patent/EP1282134A2/en
Publication of EP1282134A3 publication Critical patent/EP1282134A3/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/22—Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously

Abstract

A user configurable dual bank memory device is disclosed. The memory device includes a plurality of core banks of memory cells and a set of storage elements having stored therein configuration information. The configuration may be used to configure or group core banks of memory cells together to form a dual bank memory device. The memory device includes control circuitry for preventing a memory read operation from being completed in a core bank or user-configured dual bank in which an ongoing memory modify (program or erase) operation is being performed. The memory device further includes a first set of sense amplifiers dedicated to performing sense amplification only during memory read operations, and a second set of sense amplifiers dedicated to performing sense amplification only during memory modify operations.
EP02255372A 2001-08-02 2002-07-31 Dual bank flash memory device and method Withdrawn EP1282134A3 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/922,044 US6552935B2 (en) 2001-08-02 2001-08-02 Dual bank flash memory device and method
US922044 2001-08-02

Publications (2)

Publication Number Publication Date
EP1282134A2 EP1282134A2 (en) 2003-02-05
EP1282134A3 true EP1282134A3 (en) 2004-06-23

Family

ID=25446414

Family Applications (1)

Application Number Title Priority Date Filing Date
EP02255372A Withdrawn EP1282134A3 (en) 2001-08-02 2002-07-31 Dual bank flash memory device and method

Country Status (3)

Country Link
US (1) US6552935B2 (en)
EP (1) EP1282134A3 (en)
JP (1) JP2003123490A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8913413B2 (en) 2008-08-25 2014-12-16 Sandisk 3D Llc Memory system with sectional data lines

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US6279114B1 (en) * 1998-11-04 2001-08-21 Sandisk Corporation Voltage negotiation in a single host multiple cards system
US7009910B2 (en) * 2001-08-23 2006-03-07 Winbond Electronics Corporation Semiconductor memory having a flexible dual-bank architecture with improved row decoding
US6721227B2 (en) * 2002-02-11 2004-04-13 Micron Technology, Inc. User selectable banks for DRAM
US7170315B2 (en) * 2003-07-31 2007-01-30 Actel Corporation Programmable system on a chip
US7521960B2 (en) * 2003-07-31 2009-04-21 Actel Corporation Integrated circuit including programmable logic and external-device chip-enable override control
US7138824B1 (en) 2004-05-10 2006-11-21 Actel Corporation Integrated multi-function analog circuit including voltage, current, and temperature monitor and gate-driver circuit blocks
US7099189B1 (en) 2004-10-05 2006-08-29 Actel Corporation SRAM cell controlled by non-volatile memory cell
US7116181B2 (en) * 2004-12-21 2006-10-03 Actel Corporation Voltage- and temperature-compensated RC oscillator circuit
US7119398B1 (en) 2004-12-22 2006-10-10 Actel Corporation Power-up and power-down circuit for system-on-a-chip integrated circuit
US7446378B2 (en) * 2004-12-29 2008-11-04 Actel Corporation ESD protection structure for I/O pad subject to both positive and negative voltages
ITMI20050063A1 (en) * 2005-01-20 2006-07-21 Atmel Corp METHOD AND SYSTEM FOR THE MANAGEMENT OF A SUSPENSION REQUEST IN A FLASH MEMORY
FR2890200A1 (en) * 2005-08-25 2007-03-02 St Microelectronics Sa METHOD FOR CONFIGURING A MEMORY SPACE DIVIDED IN MEMORY ZONES
US7492632B2 (en) * 2006-04-07 2009-02-17 Innovative Silicon Isi Sa Memory array having a programmable word length, and method of operating same
US20110060868A1 (en) * 2008-02-19 2011-03-10 Rambus Inc. Multi-bank flash memory architecture with assignable resources
US8082385B2 (en) * 2008-05-02 2011-12-20 Sony Corporation Systematic memory shift for pre-segmented memory
US8375173B2 (en) * 2009-10-09 2013-02-12 Qualcomm Incorporated Accessing a multi-channel memory system having non-uniform page sizes
KR20110064041A (en) * 2009-12-07 2011-06-15 삼성전자주식회사 Semiconductors including sense amplifier connected to wordline
US8699293B2 (en) 2011-04-27 2014-04-15 Sandisk 3D Llc Non-volatile storage system with dual block programming
US8947944B2 (en) 2013-03-15 2015-02-03 Sandisk 3D Llc Program cycle skip evaluation before write operations in non-volatile memory
US8947972B2 (en) 2013-03-15 2015-02-03 Sandisk 3D Llc Dynamic address grouping for parallel programming in non-volatile memory
US9711225B2 (en) 2013-10-16 2017-07-18 Sandisk Technologies Llc Regrouping and skipping cycles in non-volatile memory
US9564215B2 (en) 2015-02-11 2017-02-07 Sandisk Technologies Llc Independent sense amplifier addressing and quota sharing in non-volatile memory
TWI758117B (en) * 2021-03-04 2022-03-11 旺宏電子股份有限公司 Flash memory and writing method thereof

Citations (2)

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EP1052647A2 (en) * 1999-05-10 2000-11-15 Kabushiki Kaisha Toshiba Semiconductor device
EP1052646A2 (en) * 1999-05-11 2000-11-15 Fujitsu Limited Non-volatile semiconductor memory device permitting data-read operation performed during data-write/erase operation

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US5245572A (en) 1991-07-30 1993-09-14 Intel Corporation Floating gate nonvolatile memory with reading while writing capability
US5822256A (en) 1994-09-06 1998-10-13 Intel Corporation Method and circuitry for usage of partially functional nonvolatile memory
US5815456A (en) * 1996-06-19 1998-09-29 Cirrus Logic, Inc. Multibank -- multiport memories and systems and methods using the same
US5841696A (en) 1997-03-05 1998-11-24 Advanced Micro Devices, Inc. Non-volatile memory enabling simultaneous reading and writing by time multiplexing a decode path
US5732017A (en) 1997-03-31 1998-03-24 Atmel Corporation Combined program and data nonvolatile memory with concurrent program-read/data write capability
US6151268A (en) * 1998-01-22 2000-11-21 Matsushita Electric Industrial Co., Ltd. Semiconductor memory and memory system
US6016270A (en) * 1998-03-06 2000-01-18 Alliance Semiconductor Corporation Flash memory architecture that utilizes a time-shared address bus scheme and separate memory cell access paths for simultaneous read/write operations
US6154821A (en) * 1998-03-10 2000-11-28 Rambus Inc. Method and apparatus for initializing dynamic random access memory (DRAM) devices by levelizing a read domain
JP2001052495A (en) 1999-06-03 2001-02-23 Toshiba Corp Semiconductor memory
US6163489A (en) 1999-07-16 2000-12-19 Micron Technology Inc. Semiconductor memory having multiple redundant columns with offset segmentation boundaries
JP3822412B2 (en) 2000-03-28 2006-09-20 株式会社東芝 Semiconductor memory device
KR100383259B1 (en) 2000-11-23 2003-05-09 삼성전자주식회사 semiconductor memory device and programmed defect address identifying method thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1052647A2 (en) * 1999-05-10 2000-11-15 Kabushiki Kaisha Toshiba Semiconductor device
EP1052646A2 (en) * 1999-05-11 2000-11-15 Fujitsu Limited Non-volatile semiconductor memory device permitting data-read operation performed during data-write/erase operation

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8913413B2 (en) 2008-08-25 2014-12-16 Sandisk 3D Llc Memory system with sectional data lines

Also Published As

Publication number Publication date
EP1282134A2 (en) 2003-02-05
JP2003123490A (en) 2003-04-25
US20030026130A1 (en) 2003-02-06
US6552935B2 (en) 2003-04-22

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