EP0985790A1 - Dynamically controlled electronic lock and control system with such a lock - Google Patents

Abstract

The electronic bolt opening system has digital words which are entered through an input panel (10) to drive an electronic circuit (12) driving a bolt (28) to an open or closed position. The electronic circuit has a memory holding a reference value. Another memory holds a current value. Logic and a second register are used to determine whether the input code is correct, to determine bolt opening.

Description

The present invention relates to electronic control locks dynamic. It relates more particularly to a lock of the type comprising an instrument for entering data, a device electromagnetic actuator for actuating a lock and a circuit electronic.

Such a lock is, for example, described in US Patent 5,488,660. His opening is controlled by a combination, given by a unit central and modified each time the lock is opened. As the lock and the central unit are not directly connected to each other it is necessary that they can work in synchronism, so that the code issued by the central unit can be checked as correct by the lock.

These locks are particularly intended to allow unique access to a protected space, for example inside a cash dispenser bank, to ensure its maintenance and loading. They allow in particular to prevent people once responsible for an operation of maintenance can use the code given to them to open subsequently the lock. In this way, it is not possible to access protected space without first obtaining an access code from the central managing the system. As a result, the security of access.

• un dispositif activé lors de l'introduction d'une combinaison d'entrée, pour générer une combinaison à partir d'informations précédemment mémorisées,
• un comparateur, pour comparer la combinaison d'entrée avec la combinaison générée et, en cas d'égalité, pour adresser des signaux de commande du verrou et de mémorisation des nouvelles informations.

More specifically, the lock described in the aforementioned patent includes a keyboard for entering combinations in the lock, a display for displaying information relating to data entry, and an electronic circuit for receiving the combination and for compare with an authorized combination. The electronic circuit includes:

• a device activated during the introduction of an input combination, to generate a combination from previously stored information,
• a comparator, to compare the input combination with the generated combination and, in the event of a tie, to send signals for controlling the lock and memorizing new information.

• la dernière combinaison acceptée,
• un paramètre spécifique à la serrure,
• une combinaison maítresse, et
• une valeur variable selon une loi prédéfinie, par exemple le nombre d'ouvertures.

In this lock, the combination is obtained from mathematical operations in which inter alia intervene:

• the last accepted combination,
• a parameter specific to the lock,
• a master suit, and
• a variable value according to a predefined law, for example the number of openings.

The input combination is defined by a central computer managing the system, which has the same means of calculation and keeps in memory the same information as the lock. The combinations are calculated, as long in the lock than at the central, on the basis of numbers in memory and in applying pre-established mathematical formulas. The lock has, in in addition, comparison means for comparing the combination entered with the combination generated, the lock being released if the combinations are equal.

By combination is meant a number introduced into the lock to be compared with a number generated in the lock, these two numbers in front to be equal.

By developing a different approach, in which information in memories are processed by means of logic functions, it is possible to make locks to further improve access security.

• une première mémoire pour mémoriser une valeur de référence,
• une deuxième mémoire pour mémoriser une valeur courante,
• une unité de traitement comprenant un premier registre pour appliquer une fonction sur la valeur de référence, un deuxième registre pour traiter la valeur courante, un troisième registre pour traiter une valeur d'entrée, des moyens pour transférer la valeur de référence et la valeur courante de sa mémoire dans son registre respectif et réciproquement, et des moyens logiques pour:
  • traiter la valeur de référence contenue dans le premier registre pour définir une nouvelle valeur de référence remplaçant la valeur antérieure dans le premier registre,
  • combiner la valeur courante contenue dans le deuxième registre et la valeur d'entrée contenue dans le troisième registre, pour définir une nouvelle valeur courante remplaçant l'ancienne dans le deuxième registre,
  • comparer le contenu des premier et deuxième registres et,
  • en cas de concordance uniquement, adresser un ordre au dispositif électromagnétique d'actionnement pour commander le verrou, remplacer dans la première mémoire la valeur de référence qui s'y trouve par la nouvelle valeur de référence contenue dans le premier registre, et remplacer dans la deuxième mémoire la valeur courante qui s'y trouve par la nouvelle valeur courante contenue dans le deuxième registre.

To this end, the lock according to the invention comprises an instrument for entering data, an electromagnetic actuation device for controlling a lock and an electronic circuit. It is characterized in that the electronic circuit includes:

• a first memory for storing a reference value,
• a second memory for storing a current value,
• a processing unit comprising a first register for applying a function to the reference value, a second register for processing the current value, a third register for processing an input value, means for transferring the reference value and the current value of his memory in his respective register and vice versa, and logical means for:
  • process the reference value contained in the first register to define a new reference value replacing the previous value in the first register,
  • combine the current value contained in the second register and the input value contained in the third register, to define a new current value replacing the old one in the second register,
  • compare the content of the first and second registers and,
  • in the event of a match only, send an order to the electromagnetic actuation device to control the lock, replace in the first memory the reference value therein with the new reference value contained in the first register, and replace in the second memory the current value which is there by the new current value contained in the second register.

Such a lock requires a new access code for each manipulation correct, which reduces the risk of unauthorized access, as mentioned above, and this remarkably well.

Code means a number or word entered in the lock and processed by the electronic circuit to give a value which, compared to another value also defined by the circuit, allows or not the opening of the lock.

In a particular embodiment, the processing unit comprises shift registers, each comprising a plurality of cells, numbered from 0 to n and in which the last information entered occupies the cell of lowest rank.

More specifically, the processing unit further comprises three doors Exclusive OR, each with two inputs and one output and defining with the shift registers of the recurrence shift registers, generally known by their English name: "Linear feed shift register" (LFSR).

• un registre à décalage à récurrence de traitement de valeur, comprenant un premier registre à décalage et une porte OU exclusif, pour traiter l'ancienne valeur de référence en vue d'obtenir une nouvelle valeur de référence, et
• un registre à décalage à récurrence, de combinaison, comprenant un deuxième registre à décalage, dans lequel est introduite la valeur courante, et un troisième registre à décalage, dans lequel est introduite la valeur d'entrée et deux portes OU exclusif pour combiner la valeur courante et la valeur d'entrée et pour définir la nouvelle valeur courante.

More particularly, the processing unit comprises:

• a value processing recurrence shift register, comprising a first shift register and an exclusive OR gate, for processing the old reference value in order to obtain a new reference value, and
• a recurrence, combination shift register, comprising a second shift register, into which the current value is entered, and a third shift register, into which the input value is entered and two exclusive OR gates for combining the value current value and the input value and to define the new current value.

The processing unit further comprises a logical processing unit arranged to verify that cells of the same rank from at least part first and second shift registers have identical content.

It will be noted that the system which is the subject of the patent mentioned above leads to combinations that are perfectly determined. In other words, in knowing the algorithm, which can be easily done by having a system of this type, and by analyzing a few successive combinations, it the following combinations are possible. Admittedly, access to the lock is made more difficult than when the code doesn't change, but it's still possible, with relatively modest means, to generate the subsequent opening combinations based on information relatively easy to obtain and thus gain unauthorized access to protected space.

An important object of the present invention is to overcome this drawback. In this effect, the lock is further characterized in that the processing unit is arranged so that it compares only a fraction of the elements of the current value and the reference value. In a more precise, the logical processing unit takes into account only a part only cells of the first and second shift registers.

The present invention also relates to a control system comprising a central device arranged to generate codes of different successive controls and a dynamically controlled lock.

• une première mémoire pour mémoriser une valeur de référence, égale à la valeur de référence contenue dans la première mémoire de la serrure,
• une deuxième mémoire pour mémoriser une valeur courante, égale à la valeur courante contenue dans la deuxième mémoire de la serrure,
• une unité de traitement comprenant :
  • un premier registre pour traiter la valeur de référence,
  • un deuxième registre pour traiter la valeur courante,
  • des moyens pour transférer la valeur de référence et la valeur courante de sa mémoire dans son registre respectif et réciproquement,
  • des moyens pour traiter la valeur de référence contenue dans le premier registre, pour définir une nouvelle valeur de référence remplaçant la valeur contenue antérieurement dans le premier registre,
  • des moyens pour combiner la valeur courante contenue dans le deuxième registre et la nouvelle valeur de référence, pour définir une valeur d'entrée contenue dans un troisième registre et une nouvelle valeur courante contenue dans le deuxième registre.

This control system is characterized in that the central device comprises:

• a first memory for storing a reference value, equal to the reference value contained in the first memory of the lock,
• a second memory for storing a current value, equal to the current value contained in the second memory of the lock,
• a processing unit comprising:
  • a first register to process the reference value,
  • a second register to process the current value,
  • means for transferring the reference value and the current value of its memory into its respective register and vice versa,
  • means for processing the reference value contained in the first register, for defining a new reference value replacing the value previously contained in the first register,
  • means for combining the current value contained in the second register and the new reference value, to define an input value contained in a third register and a new current value contained in the second register.

In order to use means as simple as possible for the creation of access codes, the control system is characterized in that the central device and the lock comprise shift registers each comprising cells, numbered from 0 to n , and in which the last information entered occupies the lowest ranking cell.

• un registre à décalage à récurrence de traitement de valeur, comprenant un premier registre à décalage dans lequel est introduite la valeur de référence et une porte OU exclusif pour traiter l'ancienne valeur de référence en vue d'obtenir une nouvelle valeur de référence, et
• un registre à décalage à récurrence, de combinaison, comprenant un deuxième registre à décalage dans lequel est introduite la valeur courante, et un troisième registre à décalage dans lequel est introduite la valeur d'entrée et deux portes OU exclusif, pour combiner la valeur courante et la valeur d'entrée et pour définir la nouvelle valeur courante,

et en ce que l'unité de traitement du dispositif comporte, en outre, trois portes OU exclusif et un commutateur, définissant ensemble:

• un registre à décalage à récurrence de traitement de valeur, comprenant un premier registre à décalage dans lequel est introduite la valeur de référence, et une porte OU exclusif pour traiter l'ancienne valeur de référence en vue d'obtenir une nouvelle valeur de référence, et
• un registre à décalage à récurrence de combinaison et mixage, comprenant un deuxième registre à décalage dans lequel la valeur courante est introduite, un troisième registre à décalage dans lequel la valeur d'entrée est introduite, et un quatrième registre à décalage dans lequel une valeur provenant au moins médiatement du premier registre à décalage est introduite, et deux portes OU exclusif, pour traiter la valeur contenue dans le quatrième registre et l'ancienne valeur courante, en vue d'obtenir la valeur d'entrée et une nouvelle valeur courante.

In a particularly advantageous embodiment of the invention, the control system is characterized in that the lock processing unit further comprises three exclusive OR doors each provided with two inputs and one output, defining with said registers:

• a value processing recurrence shift register, comprising a first shift register into which the reference value is introduced and an exclusive OR gate for processing the old reference value in order to obtain a new reference value, and
• a combination recurrence shift register, comprising a second shift register into which the current value is entered, and a third shift register into which the input value is entered and two exclusive OR gates, for combining the current value and the input value and to define the new current value,

and in that the processing unit of the device further comprises three exclusive OR gates and a switch, defining together:

• a shift register with value processing recurrence, comprising a first shift register into which the reference value is introduced, and an exclusive OR gate for processing the old reference value with a view to obtaining a new reference value, and
• a combination and mixing recurrence shift register, comprising a second shift register into which the current value is entered, a third shift register into which the input value is entered, and a fourth shift register into which a value from at least the first shift register is introduced, and two exclusive OR gates, to process the value contained in the fourth register and the old current value, in order to obtain the input value and a new current value.

To ensure the processing of information, the lock processing unit further includes a logic processing unit to verify that the cells of the same rank of at least part of the first and second register have identical content.

As explained above, the analysis of successive codes and the knowledge of the algorithm generating them can help define the codes to come up. As soon as the lock is arranged so that part only information contained in the code is read by the comparator, it is possible to introduce random values, thus making illusory determining the codes to come. To this end, the system of control is characterized in that the logic processing unit of the lock is arranged so that it compares only a part elements of the current value and the reference value and in that the processing unit of the central device further comprises a processing unit logical processing to process the reference value contained in the first shift register and to enter the value after processing in the fourth shift register, a fifth shift register and a sixth shift register cooperating with the logic processing unit to respectively hide a number of cells from the first register and to introduce a random value in cells whose elements do not are not subject to comparison.

• La figure 1 montre un schéma général d'une serrure à commande dynamique selon l'invention,
• Les figures 2 à 4 montrent respectivement des schémas de registres à décalage à récurrence, de traitement de valeur, de combinaison de valeurs et de combinaison et mixage, et
• Les figures 5a et 5b représentent la structure schématique du système selon l'invention, de l'unité centrale en a et de la serrure en b.

Other advantages and characteristics of the invention will emerge from the description which follows, given with reference to the appended drawing, in which:

• FIG. 1 shows a general diagram of a dynamically controlled lock according to the invention,
• FIGS. 2 to 4 respectively show diagrams of shift registers with recurrence, value processing, combination of values and combination and mixing, and
• Figures 5a and 5b show the schematic structure of the system according to the invention, the central unit at a and the lock at b.

The lock as schematically shown in Figure 1 has a instrument 10 for entering data into the lock, an electronic circuit of information processing 12 and a control system 14 of the locking and unlocking.

The instrument 10 has a keyboard 16 and a screen 18, allowing respectively the user to enter and obtain relative information current operations.

The electronic circuit includes a microprocessor 20, a memory 22 of type ROM, containing the control programs, a set of 24 programmable memories, E2PROM type, allowing to memorize successive values intended for managing the opening of the lock and a set of volatile memories 25, of RAM type, in which are defined registers which will be described in more detail with reference to Figures 2, 3 and 4.

The control system 14 comprises a motor 26 and a lock 28, driven by a wheel 27 secured to the axis of the motor 26. We will raise incidentally, the lock could also be controlled by an electromagnet.

The lock as described allows, for example, to control the opening a cash machine. When the person responsible for ensure loading must occur, it requests an access code to the company managing this distributor. The code is defined by a central unit, which will be the subject of a more detailed description with reference to FIG. 5a.

The code is entered using the keyboard 16. The microprocessor 20 processes the values contained in the corresponding reprogrammable memories 24 to the last recognized code as well as the new code entered, to obtain a REF reference value, function only of reference values previous, and a current value CRT. If there is a match between REF and CRT, it allows the opening of lock 28 and stores the new values obtained by combining the old values and the code entered.

If, on the contrary, there is no match, the lock remains blocked and the content of memories 24 is not modified. After he finished the job he had to perform, the user gives receipt to the company managing the distributor, which enters the information in the central unit.

To fully understand the way in which the information processing function is ensured, it is necessary to understand what a recurrence shift register, better known by its English name of "Linear feed shift register" (LFSR) and described by example in EDN ACCESS, January 4, 1996, under the title "The Ouroboros of the digital consciousness: Linear feedback-shift registers". One of them is shown in Figure 2. It includes, in this figure, a shift register 30, comprising forty cells numbered from 0 to 39 and each containing an element of a recorded binary value, and a gate Exclusive OR 32, one of the inputs of which, bearing the reference 32a, is connected to the row 1 cell and the other 32b to the row 32 cell. The output 32c is connected to the input of the shift register 30, that is to say the cell of rank 0 .

According to the principle of shift registers, a new element in the cell of rank 0 is introduced to each clock signal CLK and the content of the cells is shifted by one row. In the recurrence shift register of Figure 2, the value entered is defined by the contents of the shift register itself. Each time the register is advanced by one step, the new value entered is defined by the values contained in the cells of rank 1 and 32 which are respectively connected to the inputs 32a and 32b of the gate 32.

When the contents of these cells are equal (0-0 or 1-1), the signal exit from gate 32 is worth 0. If, on the contrary, the contents are different (0-1 or 1-0), the output signal is equal to 1. We can thus generate, so simple, a succession of binary numbers having a quasi character random, yet evolving in a predictable manner. The rehearsal period depends on the cells to which inputs 32a and 32b of gate 32 are connected. With the solution described above, this period represents several billion rotations.

Figure 3 shows a combination combination recurrence shift register values, intended to define a new current value CRT, starting from the old current value and an INT input value whose characteristics will be specified later. It has two registers to offsets 36 and 38 and two exclusive OR doors 40 and 42, each having two inputs defined by the letters a and b and an output defined by the letter c. The access code, in decimal code, entered into the lock using the keypad 16. An electronic circuit 43 transforms it into binary code, defining a input value INT, introduced into register 38 by parallel loading.

The two shift registers 36 and 38 each include forty cells, numbered from 0 to 39 . The inputs 40a and 40b of the door 40 are respectively connected to the cells of rows 1 and 32 of the register 36. The inputs 42a and 42b of the door 42 are respectively connected to the output 40c of the door 40 and to the cell of the row 39 from register 38.

The register 36 therefore initially contains the value CRT originating from the previous transaction and the register 38 the value INT newly introduced. As the cell of rank 39 of register 38 is connected to the input 42b of the door 42, while the other input 42a is connected to the output 40c of the door 40, the logic states of these two inputs define binary information introduced into the row 0 cell of register 36. In this way, each time a clock signal is applied to register 38, its content is shifted by one row and a bit is introduced into register 36, a function its own content and that of the register 38.

A value combination recurrence shift register allows to obtain a predictable value, from two known values. It is however extremely difficult to determine this value if one does not know not the structure of the shift registers.

To further improve access security, it is possible to introduce random parameters in the input value and compare only the share predictable parameters. For this purpose, a structure such as shown in Figure 4, which shows three shift registers bearing the references 44, 46 and 48 respectively, two doors OR exclusive 50 and 52 and a switch with two inputs and two outputs, schematically represented in 54. The assembly forms a shift register with recurrence of combination and mixing. It allows you to enter into registers 44 and 46 part of the information contained in the cells of register 48, these parts being complementary, the other cells being charged of information obtained by combining the information initially contained in registers 44 and 48.

More precisely, it makes it possible to obtain, in the register 46, the input value INT comprising information making it possible to ensure control of the lock. To this end, the door 50 has two inputs 50a and 50b respectively connected to the cells of rows 32 and 1 of the register 44. The door 52 comprises inputs 52a and 52b respectively connected to the output 50c of the door 50 and to the cell row 39 of register 48. The switch 54 comprises two inputs 54a and 54b and two outputs 54c and 54d. The row 39 cell of the register 48 is also connected to the first input 54a of the switch 54. The second input 54b is connected to the output 52c of the door 52. Finally, the outputs 54c and 54d are respectively connected to the cells of rank 0 registers 44 and 46.

When the switch 54 is in position as shown in the drawing, that is, input 54a is connected to output 54d, the information contained in register 48 are transferred without modification to the register 46. In other words, they are transferred without encryption. This position corresponds to the transfer of random elements from the input value INT. In register 44, on the contrary, the information entered is obtained by processing the content of register 44 and the content of register 48, by the exclusive OR function applied by gate 52. The situation is reversed when the switch toggles. In this way, the contents of the register 48 is transferred in clear to register 44 while register 46 receives a information obtained by processing the contents of registers 44 and 48, at door 52.

The content of register 46 is then transformed into decimal code by means not shown in the drawing, the number obtained taking the place of code access.

Figure 5a shows, schematically, the device of the central unit intended to define the successive access codes of a control lock dynamic, the logic of which is shown in Figure 5b.

The central unit device has two reprogrammable memories 58 and 60, a value processing recurrence shift register 62, such that defined with reference to FIG. 2 and a shift register with recurrence of combination and mixing 63, as defined with reference to FIG. 4. The constituent parts of these registers bear the same references as those used in these figures. It further comprises two shift registers 64 and 68, and a logic processing unit 70 comprising means schematically represented in 72 and 76, and intended to ensure an AND logic function and an OR logic function respectively.

Memories 58 and 60 respectively contain REF and CRT values whose characteristics will be specified later.

The registers 64 and 68 have the same number of cells. The register 64 contains a constant MAS value, defining the cells whose content is encrypted, identified by 1, while cells with clear content contain a 0. Register 68 is intended to receive a random value ALE. It is obtained from a random binary number, comprising as many digits as the registers have cells, generated by the unit central by means known to those skilled in the art and not shown in drawing, and treated by comparison with the contents of register 64 so that for all the cells of register 64 containing a 1, the cell of the same rank of register 68 is brought to 0. In this way, the cells occupied by the variable elements of the ALE value correspond to the cells of register 64 whose content is equal to 0. The other cells contain the value 0.

When the central unit device receives a code request, the contents of memories 58 and 60 are respectively introduced, by parallel loading, in the registers 30 of the shift register at recurrence of value processing 62, and 44 of the shift register at combination recurrence and mixing 63. A CLK REF clock signal is applied to register 30, to define a new REF value.

After which, the contents of registers 30, 64 and 68 are then processed in parallel, by means of the logic processing unit 70. More specifies, the contents of registers 30 and 64 are processed using the AND function represented in 72. The value thus obtained is equal to the content of register 30 when the content of register 64 is equal to 1, and to 0 in the other cases. We thus free cells to introduce a random part ALE, entered using the OR function, so that the value obtained at the output of the unit 70 is formed of two parts comprising respectively, a random part and reference information. The value thus obtained is introduced in parallel in register 48, the content of which is then processed through register 63.

A CLK clock signal is then applied to registers 44, 46, 48 and 64. The information contained in register 64 commands the switch 54 so that the signals from register 48 are directly entered into register 46 when the contents of the cell of register 64 is equal to 0 and in register 44 when it is equal to 1. At the end of this operation, register 46 contains the value, called INT, comprising a random part and a part intended for controlling opening the lock. The INT value is then transformed on code decimal, by means not shown, to render the reading and the easier processing. The code is thus transmitted to the person who is to open the lock.

It should be noted that all of the components necessary to perform the functions of the central unit device can be found in any computer personnel and that the programming of the functions to be performed are the scope of the skilled person.

The access code, thus obtained, is processed, after introduction by means of the keyboard and transformation into binary value, by the logical device of the lock as shown in Figure 5b. This device includes, for this purpose, two reprogrammable memories 80 and 82, a shift register with value processing recurrence 84, as defined with reference to the figure 2 and a combination value shift register 86, such as defined with reference to Figure 3. The constituent parts of these registers bear the same references as those used in these figures. This device further comprises a shift register 88, and a unit for logic processing 90 comprising means schematically represented year 92, 94 and 96, and intended to ensure respectively logical functions OR exclusive, AND and SI.

Memories 80 and 82 respectively contain REF and CRT values, equal to the values contained in the central unit. To make it so, there suffices that at the start, equal values are entered in the memories the lock and the central unit. These values adjust then automatically.

Register 88 contains a constant value MAS equal to the value contained in register 64.

To ensure the opening of the lock, the starting of the system causes the respective transfer of the contents of memories 80 and 82 in the registers 30 and 36. As shown in FIG. 3, the access code, decimal, is transformed into binary and gives the value INT introduced in parallel in register 38. The content of this register is then processed by the combination value shift register 86. Simultaneously, the content of register 30 is processed as explained on reference to figure 2.

The elements of cells of the same rank in registers 30, 36 and 88 are then processed in parallel by means of logic unit 90. Whenever elements of the same rank in registers 30 and 36 are equal, the element resulting from the exclusive OR function is equal to 0, while if they differ, it is equal to 1. By treating the resulting elements with the same elements rank of the MAS value contained in register 88, by means of the function AND 94, the variable elements of the ALE value are always equal to 0. In other words if all the same encrypted items of registers 30 and 36 are equal, the signal from the AND gate is always equal to 0. If this is if so, the IF function answers YES and the lock is open or released. If at contrary, at least one of the encrypted elements differs, the IF function responds NO and the lock remains blocked.

When the entered value is refused, the contents of the memories are not amended. If the value entered is accepted, the contents of registers 30 and 36 are transferred respectively to memories 80 and 82, as new REF and current CRT reference values.

The person requesting the code gives a receipt to the central unit which transfer to memories 58 and 60 the respective contents of registers 30 and 44, as new reference values REF and current CRT, in the device as described with reference to FIG. 5a.

It will be noted that in the system as described, the decimal code given to the person to open the lock is defined by the combination of elements obtained from the processing of the stored values REF and CRT and random elements. So it is impossible, based on the code as well given, to determine precisely what will be the value of the next code to introduce. In addition, even knowing the ranks occupied by the cells containing elements relating to the random part, it is impossible to define a code to come without knowing, at the same time, the content of the REF values and CRT and the structure of recurrence shift registers.

Because of this particular approach, the means implemented in the unit central different from those associated with the lock and the knowledge of this does not allow to carry out a program likely to generate codes to come. Access security is thus considerably improved.

It is understood that the concept defined above may include many variations. The dynamically controlled system can be associated with a classic constant code system.

It is common for such locks to have a double control, with an electronic key and an access code. The hidden part of the value INT could be enlarged, so as to introduce, in the code, an indication of the key to be used together. Such a solution further increases access security.

It will be noted that with the system according to the invention, the disclosure of all of the algorithm used does not reduce the level of security of the lock, which is not the case of that described in US Patent 5,488,660.

Claims (11)

Dynamically controlled electronic lock comprising an instrument (10) for entering data, an electromagnetic actuation device (26) for controlling a lock (28) and an electronic circuit (12), characterized in that said circuit comprises: a first memory (80) for storing a reference value (REF), a second memory (82) for storing a current value (CRT), a processing unit comprising, a first register (30) for applying a function to the reference value (REF), a second register (36) for processing the current value (CRT), a third register (38) for processing a value input (INT), means for transferring the reference value (REF) and the current value (CRT) from its memory into its respective register and vice versa, and logic means (32, 40, 42, 90) for: process the reference value (REF) contained in the first register to define a new reference value replacing, in the first register (30), the previous value (REF), combine the current value (CRT) contained in the second register (36) and the input value (INT) contained in the third register (38), to define a new current value contained in the second register (36), compare the content of the first (30) and second (36) registers and, in the event of a match only, send an order to the electromagnetic actuating device (26) to control the lock (28), and replace in the first memory (80) the reference value therein with the new reference value contained in the first register (30) and replace in the second memory (82) the current value therein by the new current value contained in the second register (36). Lock according to claim 1, characterized in that said processing unit comprises shift registers, each comprising cells, numbered from 0 to n , and in which the last information entered occupies the cell of lowest rank. Dynamically controlled electronic lock according to claim 2, characterized in that said processing unit further comprises three exclusive OR doors (32, 40, 42) each provided with two inputs and one output, defining with said registers: a recurrence shift register (84) for processing value, comprising a first shift register (30) and an exclusive OR gate (32), for processing the old reference value in order to obtain a new reference value , and a combination shift register (86) comprising a second shift register (36) into which the current value is entered (CRT), and a third shift register (38) into which the value of input (INT) and two exclusive OR gates (40, 42) to combine the current value and the input value and to define the new current value. Lock according to claim 3, characterized in that the unit of processing further comprises a logic processing unit (90) for check that the cells of the same rank of at least part of the first and the second shift register (30, 36), have identical content. Lock according to one of claims 1 to 3, characterized in that said processing unit is arranged so that it compares only one part only of the elements of the current value (CRT) and the value of reference (REF). Lock according to claims 4 and 5, characterized in that the unit logical processing (90) compares only a part of the cells first and second shift registers (30, 36). Control system comprising a central control device and at least one lock according to claim 1, characterized in that said device comprises: a first memory (58) for storing a reference value (REF), equal to the reference value contained in the first memory (80) of the lock, a second memory (60) for storing a current value (CRT), equal to the current value contained in the second memory (82) of the lock, a processing unit comprising: a first register (30) for processing the reference value (REF), a second register (44) for processing the current value (CRT), means for transferring the reference value (REF) and the current value (CRT) from its memory into its respective register and vice versa, means (62) for processing the reference value contained in the first register (30) to define a new reference value replacing the value previously contained in the first register, means (63) for combining the current value contained in the second register (44) and the new reference value, to define an input value contained in a third register and a new current value contained in the second register. Control system according to claim 7, characterized in that the processing unit and the lock comprise shift registers (30, 36, 38, 44, 46, 48, 64, 66, 68, 88) each comprising cells , numbered from 0 to n , and in which the last information entered occupies the lowest rank cell. Control system according to claim 8, characterized in that the lock processing unit further comprises three exclusive OR doors (32, 40, 42) each provided with two inputs and one output, defining with said registers: a recurrence shift register (84) for processing value, comprising a first shift register (30) into which the reference value (REF) is introduced, and an exclusive OR gate (32) for processing the old value of reference in order to obtain a new reference value, and a combination shift register (86) comprising a second shift register (36) into which the current value is entered (CRT), and a third shift register (38) into which the value of input (INT) and two exclusive OR gates (40, 42), to combine the current value and the input value and to define the new current value, and in that the processing unit of said device further comprises three exclusive OR gates (32, 50, 52) and a switch (54), defining together: a recurrence shift register (62) for processing value, comprising a first shift register (30) into which the reference value (REF) is introduced, and an exclusive OR gate (32) for processing the old value of reference in order to obtain a new reference value, and a combination and mixing recurrence shift register (63), comprising a second shift register (44) into which the current value (CRT) is entered, a third shift register (46) into which the input value ( INT) is introduced, and a fourth shift register (48) into which is entered a value originating at least medially from the first shift register (30), and two exclusive OR gates (40, 42), for processing the value contained in the fourth register and the old current value, in order to obtain the input value (INT) and a new current value (CRT). System according to claim 9, characterized in that the unit of processing of the lock also includes a logic processing unit (90) to verify that cells of the same rank of at least part of the first (30) and second register (36), have identical content. System according to claim 10, characterized in that said unit logic processing (90) of the lock is arranged so that it does not compare only part of the elements of the current value (CRT) and of the reference value (REF) and what the processing unit of said device further comprises a logic processing unit (70) for processing the reference value (REF) contained in the first shift register (30) and to enter the value after processing in said fourth register shift (48), a fifth (64) and a sixth shift register (68) cooperating with the logic processing unit (70) for respectively hide a certain number of cells from the first register (30) and for enter a random value (ALE) in cells whose elements do not are not the subject of said comparison.

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