EP0877386A1

EP0877386A1 - Method and device for analog programming of non-volatile memory cells, in particular flash memory cells

Info

Publication number: EP0877386A1
Application number: EP97830216A
Authority: EP
Inventors: Pierluigi Rolandi; Roberto Canegallo; Ernestina Chioffi; Danilo Gerna; Marco Pasotti
Original assignee: STMicroelectronics SRL; SGS Thomson Microelectronics SRL
Current assignee: STMicroelectronics SRL
Priority date: 1997-05-09
Filing date: 1997-05-09
Publication date: 1998-11-11
Anticipated expiration: 2017-05-09
Also published as: DE69723814D1; US6195283B1; EP0877386B1

Abstract

For each cell (1) to be programmed, the present threshold value (V_o) of the cell is determined; the desired threshold value (V_TAR) is acquired; the analog distance between the present threshold value and the desired threshold value is calculated; and a programming pulse (S) is then generated, the duration of which is proportional to the analog distance calculated. The programming and reading cycle is repeated until the desired threshold is reached. By this means a time saving is obtained, owing to the reduction of the number of intermediate reading steps. The method permits programming in parallel and simultaneously of a plurality of cells (1) of a memory array (2) which is connected to a single word line (5₁) and to different bit lines (4₁ - 4_N), each with a programming pulse (S₁ - S_N) the duration of which is proportional to the analog distance calculated for the same cell. The programming process is thus very fast, owing to parallel application of the programming and the saving in the intermediate reading cycles.

Description

The present invention relates to a method and a device for analog programming of non-volatile memory cells, in particular flash memory cells.

As is known, analog programming of a memory cell consists of modifying to a desired analogue value the threshold voltage value of the cell (i.e. the minimum voltage to be applied between the gate terminals and the source of the cell itself, in order for the latter to begin to conduct current). Programming is currently carried out in a memory array by connecting the gate terminal of the cell to be programmed to a reference voltage, the drain terminal to a high programming voltage, and the source terminal to ground. Since the programming is a non-reproducible process, it is carried out in multi-level memories by providing a plurality of programming pulses of short duration, and by reading the threshold voltage value reached by the cell at the end of each programming pulse (verify step). In general during each programming pulse, the gate terminal of the cell to be programmed is supplied with a high programming voltage. In general the programming process is preceded by a cell erasing step, such that the cells have a low initial threshold voltage (lower than the minimum analog value to be stored) and each programming pulse gives rise to an increase of the threshold voltage of the cell; when the desired threshold voltage is reached, the programming process is interrupted. Generally speaking therefore, programming is carried out at present by gradually modifying the initial threshold voltage value through short programming pulses, followed by reading the reached level, until the desired level is obtained.

In order to avoid programming the cell excessively, the programming pulses are short, as indicated above, such that when a cell must sustain a large threshold jump, the described process requires a large number of programming/reading cycles, and thus involves a considerable programming time.

The object of the invention is thus to provide a method and a programming device which permit reduction of the programming time of memory cells.

According to the present invention, a method for analog programming of non-volatile memory cells, in particular flash memory cells, is provided, as defined in claim 1.

Furthermore, according to the invention, a device for analog programming of non-volatile memory cells, in particular flash memory cells, is provided, as defined in claim 4.

In order to allow the present invention to be understood, a preferred embodiment is now described, purely by way of non-limiting example, with reference to the attached drawings, in which:

figure 1 is a circuit diagram for the device for programming a memory cell;
figure 2 is a schematic circuit diagram of the device for programming a memory array; and
figure 3 is the circuit diagram of a detail of the present invention.

According to the present method, the present threshold value is determined directly or indirectly for each cell to be programmed; the desired threshold value is acquired; the analog distance between the present threshold value and the desired threshold value is calculated; and a programming pulse is then generated, the duration of which is proportional to the analog distance calculated. Subsequently, the threshold level reached is read and compared once more with the desired threshold value, and further programming pulses can be supplied, the duration of which can be determined on the basis of the distance between the desired threshold value and the threshold value reached, or the pulses can be fixed and short, similarly to known solutions.

Therefore, when a cell is to be programmed with a desired threshold voltage, the value of which is remote from the present value, at least the first programming pulse is much longer than the standard pulse, reducing substantially the total programming time by reducing the number of reading operations and saving the corresponding intermediate times necessary in order to transfer the circuit from the reading condition to the programming condition and vice versa in the various programming/reading cycles.

This process also permits programming in parallel of a plurality of cells which belong to the same line and different columns, each with a programming pulse, the duration of which is proportional to the analog distance between the present threshold value of each cell and the desired threshold value for the same cell. This process requires suitable pulse control circuitry for each column, and involves a programming time for each cycle which is related with the duration of the longest programming pulse from among those planned for the various columns programmed in parallel. In this case therefore, with increased complexity of the control circuitry, a considerable saving of time is obtained altogether by means of parallel application of the programming, and the saving in the reading cycles.

An example of a programming device for a cell which uses a specific circuit for reading the threshold voltage is shown in figure 1, and is described hereinafter. In particular, the reading circuit in figure 1 provides an indirect value of the present threshold voltage of the cell to be programmed, and is described in detail in European patent application 97830172.9 dated 15.4.97 with the title "High-precision analogue reading circuit for memory matrices, in particular flash analog memory matrices", incorporated herein for reference. However the present invention is not limited to this type of reading circuit, although it is advantageously applicable to the latter, and can also be implemented with other reading circuits which directly or indirectly can supply the present threshold voltage value of the cell.

In figure 1, the cell 1 to be programmed has a source terminal 11 which is connected to ground, a gate terminal 12 which is biased to a reading voltage V_R, and a drain terminal 13 which is connected to a first node 14 through an NMOS-type selector switch 15. The first node 14 is connected to a second node 16 through a first biasing transistor 17; the second node 16 is in turn connected to a current mirror circuit 19 formed by two PMOS transistors 21, 22; in detail, the PMOS transistor 21 is diode-connected (i.e it has short-circuited drain and gate terminals) and has the drain terminal connected to the node 18, the source terminal connected to the supply line 23 which is set to V_dd, and the gate terminal connected to the gate terminal of the PMOS transistor 22; the latter has the source terminal connected to the supply line 23, and the drain terminal connected to a node 24.

The node 24 is connected through a second biasing transistor 25 also of the NMOS type and a dummy switch 26 which is always maintained closed, to the drain terminal 28 of a reference cell 27, for example a virgin cell, which has the source terminal 29 connected to ground and the gate terminal 30 connected to the output of an operational amplifier 31; the latter has an inverting input which is connected to the node 16, and a non-inverting input which is connected to the node 24.

The node 14 is connected to a programming voltage line 33, which is set to the programming voltage V_PD, through a controlled switch 34 which has a control terminal 35 connected to an output 36 of a pulse generator 37. The pulse generator 37 has a first and a second input 38, 39 which receive a target threshold voltage V_TAR (which is proportional to the desired threshold voltage) and the output voltage V_o of the operational amplifier 31 (which, as explained hereinafter, is proportional to the present threshold voltage of the cell 1 to be programmed), such as to generate a control pulse S which is supplied to the controlled switch 34, and has a duration proportional to the difference between the target threshold voltage V_TAR and the output voltage V_o, and thus between the desired threshold voltage and the present threshold voltage.

A control unit 40 provides the pulse generator 37 with a signal EN which enables and de-enables the pulse generator 37 when the cell 1 is to be programmed and when the programming is completed.

The circuit in figure 1 operates as follows. Initially, the initial value of the output voltage V_o of the operational amplifier 31 is determined, and the target voltage V_TAR is acquired; the pulse generator 37 then generates the control pulse S, which causes controlled switch 34 to close and node 14 to be connected to the programming voltage V_PD for a time which is proportional to the difference between the desired threshold voltage and the present threshold voltage of the cell 1. At the end of the pulse S, the new value of the output voltage V_o is determined, and on the basis of the latter a further programming and reading cycle is optionally initiated; the programming and reading cycles are then repeated until the desired threshold value is reached.

Reading of the present threshold voltage of the cell 1 through output voltage V_o is carried out as follows. As described in detail in the aforementioned European patent application 97830172.9, the current mirror circuit 19 forces the same currents I₁ = I₂₇ into the cell 1 to be programmed and into the reference cell 27; the biasing transistors 17 and 25 maintain the cells 1 and 27 in the linear region, keeping the voltage drop between their drain and source terminals constant; in addition, in a condition of equilibrium, the voltages at the inputs of the operational amplifier 31 (voltages at the nodes 16 and 24) are the same, and, since the biasing transistors 17, 25 receive the same biasing voltage V_s (for example 1.5 V) at the gate terminal, they have the same gate-source drop; consequently, leaving out of consideration the voltage drop across the selector switch 15 and the dummy switch 26, the following is obtained: VDS,1 = VDS,27 i.e. the drain-source voltage is the same in the cell 1 to be programmed and in the reference cell 27.

Furthermore, provided that the cell 1 to be read and the reference cell 27 are equal and manufactured using the same technology, the current I₁ which flows through the cell 1 to be programmed and the current I₂₇ which flows through the reference cell 27 are provided by the following, in the first approximation: I1 = K*(W/L)*[(VR - Vth,1)]*VDS,1 I27 = K*(W/L)*[(Vo - Vth,27)]*VDS,27 where V_th,1 and V_th,27 are respectively the threshold voltages of the cell 1 to be programmed and the reference cell 27, K is a constant which is associated with the production process, and W/L is the dimensional ratio (width to length) of the cells.

Since I₁ = I₂₇, by equalising (1) and (2), the following is obtained by means of simple calculations: Vo = VR - (Vth,1 - Vth,27) i.e. the output voltage V_o is linearly dependent on the threshold voltage of the cell to be read 2, via the gate biasing voltage V_R and the threshold voltage V_th,27 of the reference cell 27.

The presence of the values V_R and V_th,27 in (3) does not create problems, since the target voltage V_TAR can be calculated by summing the desired threshold value for the cell 1 and values V_R and V_th,27. However, this would require accurate knowledge of the threshold voltage V_th,27 of the reference cell 27, which is not always present. In effect, this knowledge is not necessary. In fact for programming and subsequent reading of the threshold voltage of the cell 1, it is possible to use solely the relative value of the threshold voltage of the cell 1 with respect to the threshold voltage of the reference cell 27, i.e. the difference between them which thus becomes the value to be stored. In this case, programming of the cell 1 consists of modifying the threshold of the cell itself such that the output voltage V_o becomes equal to the sum of the value to be stored (desired difference between the thresholds of cells 1 and 27) and the gate biasing voltage V_R. In this case, the target voltage V_TAR is equal to this sum, and the pulse generator supplies a pulse, the duration of which is proportional to the distance between the desired difference between the thresholds of the cells 1 and 27 (value to be stored) and the present difference, since the term V_R is cancelled out.

Figure 2 shows an embodiment which permits programming in parallel of a plurality of cells which belong to different columns. The cells 1 are disposed on lines and in columns in order to form a portion (for example a sector or part of the latter) of a memory array 2 which belongs to a memory 3, of which only the components essential for understanding of the invention are shown.

In detail, the cells 1 are connected to a plurality of bit lines 4₁-4_N and a plurality of word lines 5₁-5_M. The word lines 5₁-5_M are connected to a row decoder 6; the bit lines 4₁-4_N are connected to the programming voltage line 33 via a selection transistor 15₁-15_N which belongs to a column decoder 7. In addition, a controlled switch 34₁-34_N is disposed between each selection transistor 15₁-15_N and the programming voltage line 33.

Each controlled switch 34₁-34_N receives a control signal S₁-S_N from a pulse generator 37₁ - 37_N which in turn receives at its input a target threshold voltage value V_TAR1-V_TARN and a threshold voltage value read V₀₁-V_ON supplied by a reading circuit 42₁-42_N. Each reading circuit 42₁-42_N has an input which is connected to the node 14₁-14_N present between each selection transistor 15₁-15_N and the controlled switch 34₁-34_N. The reading circuits are the same as one another; they are preferably produced as shown in figure 1, and comprise the biasing transistors 17, 25; the current mirror circuit 19; the dummy transistor 26, the reference cell 27 and the operational amplifier 31.

In the diagram in figure 2, it is possible to carry out programming in parallel of all the cells connected to the bit lines 4₁-4_N and to a specific word line, for example the word line 5₁; in this case, the line decoder 6, which is controlled in a known manner by a logic unit not shown, polarises the word line 5₁ to the reference voltage V_R and maintains the other word lines 5₂-5_M grounded, such that the cells connected to these word lines 5₂-5_M continue to be switched off; each reading circuit 42₁-42_N reads the present value of the threshold voltage of the cell 1, and supplies it to the pulse generator 37₁-37_N which also receives the value of the target threshold voltage V_TAR1-V_TARN; when the enabling signal EN is received, the pulse generators 37₁-37_N then each supply their own pulse S₁-S_N of different duration. Repetition of the reading/ programming cycles then makes it possible to reach the desired threshold value for all the N cells connected to the word line 5₁, thus permitting simultaneous programming of a plurality of cells.

Fig. 3 shows a possible implementation of the pulse generator 37 by means of an operational amplifier 44 in a differential amplifier configuration, and a comparator 45; this figure does not show the enabling input for the signal EN. In detail, the operational amplifier 44 has the non-inverting input connected to the input 38 through a first resistor 47, and to ground through a second resistor 48, and has the inverting input connected to the input 39 through a third resistor 49, and to the output 51 through a fourth resistor 50. The comparator 45 has the positive input connected to the output 51 of the operational amplifier 44, the negative input receives a ramp signal, and the output forms the output 36 of the pulse generator 37.

The resistors 47-50 all have the same resistance R; consequently at the output 51 of the operational amplifier 44, there is a voltage signal VOP = VTAR - Vo which is compared with the ramp signal supplied to the negative input of the comparator 45. The signal S at the output of the comparator 45 thus has a high value until the amplitude of the ramp signal is lower than the signal V_OP, and switches to the low state as soon as the ramp signal exceeds the signal V_OP. By this means, the duration of the signal S is proportional to the difference between the threshold voltages V_TAR - V_o.

The advantages which can be obtained by means of the method and the device described are as follows. Firstly, as described above, they permit considerable reduction of the programming times of each memory cell. Additionally, compared with memories which permit programming of a single cell at a time, a considerable saving of time is obtained by means of programming in parallel of a plurality of cells. The device is inherently simple and reliable, and can be used without problems in present flash memories.

Finally, it will be appreciated that numerous modifications and variants, all of which come within the scope of the inventive concept, can be made to the method and the device described and illustrated here.

Claims

A method for analog programming of a non-volatile memory cell which can store an analog value, comprising the steps of:

acquiring a desired programming value; and

detecting a value stored in the memory cell;
characterised in that it comprises the steps of:

detecting a difference value which is equal to the difference between said desired programming value and said stored value; and

generating a programming pulse for said memory cell, which has a duration which is correlated to said difference value.
A method according to claim 1, for a plurality of memory cells connected to a single selection line and to a plurality of biasing lines, characterised in that it comprises the steps of:

acquiring the desired programming value for each memory cell;

detecting the value stored in each memory cell;

calculating the difference value associated with each memory cell, each difference value being equal to the difference between said desired programming value and said stored value for the respective memory cell; and

generating in parallel a plurality of programming pulses, one for each memory cell, each programming pulse having a duration which is correlated to said difference value associated with said respective cell.
A method according to claim 1 or 2, characterised in that after said generating step, the stored value is determined once more, and if the newly determined stored value differs from said desired programming value, a new programming pulse is generated.
An analog programming device for a non-volatile memory cell which can store an analog value, comprising input means (38) for acquiring a desired programming value and reading means (42) for determining a value stored in said memory cell (1), characterised in that it comprises pulse modulation means (37) determining a difference value equal to the difference between said desired programming value and said stored value, and generating a programming pulse for said memory cell, with a duration correlated to said difference value.
A device according to claim 4 for a memory array (2), comprising a plurality of memory cells (1) connected to a single selection line (5₁) and to a plurality of biasing lines (4₁-4_N), characterised in that it comprises a plurality of input means (38) each acquiring a desired programming value for a respective memory cell (1); a plurality of reading means (42₁-42_N) each determining the value stored in a respective memory cell; and a plurality of pulse modulation means (37) determining a difference value associated with each memory cell and equal to the difference between said desired programming value and said value stored by the respective memory cell, and generating in parallel a plurality of programming pulses for a respective memory cell, each programming pulse having a duration correlated to said difference value associated with said respective memory cell.
A device according to claim 4 or 5, characterised in that said pulse modulation means (37) comprise a first operational amplifier (44) in a differential configuration, and a comparator (45) which has a first input which is connected to an output (51) of said operational amplifier and a second input which receives a comparative ramp signal.
A device according to any one of claims 4-6, characterised in that it comprises a programming voltage line (33) which is connected to a drain terminal (13) of said memory cell (1) via a controlled switch (34) which has a control terminal (35) connected to said pulse modulation means (37).
A device according to any one of claims 4-7, characterised in that said reading means (42) comprise a current mirror circuit (19) having a first and a second node (16, 24) which supply equal first and second currents to a first terminal (13) of said memory cell (1) and, respectively, to a first terminal (28) of a reference cell (27); and a second operational amplifier (31) which has a first input connected to said first node (16), a second input connected to said second node (24) and an output connected to a control terminal (30) of said reference cell (27) and to an input (39) of said pulse modulation means (37), said first terminal (13) of the memory cell (1) receiving said programming pulse.