EP0473789A1

EP0473789A1 - Bit map display controller

Info

Publication number: EP0473789A1
Application number: EP19910904650
Authority: EP
Inventors: Kenji Otsu
Original assignee: Matsushita Electric Industrial Co Ltd
Current assignee: Panasonic Holdings Corp
Priority date: 1990-02-26
Filing date: 1991-02-26
Publication date: 1992-03-11
Also published as: WO1991013428A1; JPH03246596A

Abstract

A controller capable of changing arbitrarily the order of address of a video memory (2) in a bit map display. The controller is provided with an address translator which writes translation data for the address for making access from a CPU (3) to the video memory (2) in accordance with the write content of the address in the order of a luster scanning generated by a display controller (1) and outputs the data as the conversion address for the address from the CPU (3) to the video memory (2).

Description

TECHNICAL FIELD

The present invention relates to a bit map display controlling apparatus used with a word processor, personal computer, data terminal equipment or the like.

BACKGROUND ART

In a conventional bit map display controlling apparatus of this type, addresses of a video memory are assigned sequentially in the order of raster scanning, and a display controller accesses the video memory in the order of addresses to perform a refresh display of the contents of the video memory.
Addresses of the video memory as seen from a central processing unit (hereinafter called a CPU) are also assigned in the above-described manner. Fig. 4 shows the structure of a conventional bit map display controlling apparatus. In Fig. 4, a display controller 1 generates addresses a2 for writing to the video memory 2 sequentially in the order of raster scanning and supplies them to a video memory 2 storing the raster scan type display contents. The video memory 2 outputs display data d2 in the order of raster scanning.
CPU 3 accesses, when necessary, the video memory 2 fixedly assigned with the addresses in the order of raster scanning, and changes the data in the video memory 2 to a data d1.
Fig. 5 shows an example of an address map of the video memory 2 of a conventional bit map display controlling apparatus. This example of Fig. 5 is applied to a bit map display controlling apparatus wherein 1024 dots are scanned in the horizontal direction, and 512 dots are repeatedly scanned (having 512 scan lines) in the vertical direction. Byte addresses are sequentially assigned in the horizontal direction on the 8 dots (bits) unit basis. Numbers in Fig. 5 represent the byte addresses.
The numbers of dots in the horizontal and vertical directions may vary depending upon a bit map display controlling apparatus. However, in general, the address assignment of a conventional bit map display controlling apparatus is in the order of raster scanning such as shown in Fig. 5.
The above-described conventional bit map display controlling apparatus is, however, associated with a problem that in writing data into the video memory 2 under control of CPU 3, an address translation calculation to be executed by a program may sometimes become complicated depending upon the contents of the data, because the addresses of the video memory 2 are fixedly assigned, thereby increasing the processing time and the quantity of program.
Consider for example the case where a program of CPU 3 reads a character "A" composed of 8 bits in the horizontal direction and 8 bits in the vertical direction as shown in Fig. 3(a), from a character generator read-only memory at addresses from 0 to 7, and writes the character data in the video memory at addresses from 0 to 894 at the interval of every 128-th addresses. In this case, although the consecutive 8 bytes are accessed for reading the data on the side of the character generator read-only memory, data writing on the side of the video memory requires an address addition calculation for each byte by using a program, because the corresponding addresses of the video memory are not consecutive.
The present invention solves such conventional problems and aims at providing a bit map display controlling apparatus wherein in writing data in a video memory by using a program of CPU, the addresses generated by a display controller sequentially in the order of raster scanning can be translated as desired depending upon the contents of the data so as to satisfy the program, thereby reducing the load on the program of CPU.

DISCLOSURE OF THE INVENTION

In order to achieve the above object of the present invention, an address translator is provided for reducing the load of a program of CPU. There is written in the address translator a translation data for an address from CPU for accessing a video memory, and the translation data is outputted to the video memory as a translated address of the address from CPU. Thus, the load of program of CPU can be reduced.
According to the present invention, an address from CPU for accessing the video memory is translated by the address translator, and thereafter the video memory is accessed using the translated address. Therefore, in writing data in a video memory using a program of CPU, the video memory address can be accessed most properly for the program of CPU in accordance with the contents of the data to be written.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a block diagram showing a bit map display controlling apparatus according to an embodiment of the present invention, Fig. 2 is a diagram illustrating the correspondence between addresses and their contents in an address memory of the address translator of the apparatus shown in Fig. 1, Fig. 3(a) is a diagram showing addresses and their contents read from a character generator of the apparatus shown in Fig. 1, Fig. 3(b) is a diagram showing addresses of a video memory corresponding to the addresses shown in Fig. 3(a), and their contents, Fig. 4 is a block diagram showing a conventional bit map display controlling apparatus, and Fig. 5 illustrates an address assignment of a video memory in a conventional bit map display controlling apparatus.

BEST MODE FOR CARRYING OUT THE INVENTION

Fig. 1 shows the structure of an embodiment of the present invention. In Fig. 1, reference numeral 1 represents a display controller which generates an address signal a2 sequentially in the order of raster scanning for accessing a video memory 2 storing the raster scan type display contents, and supplies it to the video memory 2 to access it.
d2 represents a display data outputted from the video memory 2 when the display controller 1 accesses the video memory 2.
Reference numeral 3 represents a stored-program type CPU which outputs a data d1 to be written in the video memory 2.
Reference numeral 4 represents an address translator which is constructed of a random access memory. In this address translator 4, CPU 3 writes in advance an address translation data d3 for an address a1 to be outputted from CPU 3 for accessing the video memory 2. The address translator 4 outputs an address a3 as a translated address of the address a1 for accessing the video memory 2.
Fig. 2 shows the contents of the address translation data d3 outputted from CPU 3 and written in the address translator 4 for addresses "0" to "7" designated by the address a1 outputted from CPU 3.
Fig. 3(a) shows the contents of a character "A" to be read from a character generator read-only memory (not shown) at addresses from "0" to "7". Fig. 3(b) shows the read-out contents of Fig. 3(a) written in the video memory 2 at addresses from "0" to 894 at the interval of every 128-th addresses.
The addresses from "0" to "894" shown in Fig. 3(b) correspond to the addresses of the video memory 2 assigned with byte addresses on the 8 bits unit basis in the horizontal direction shown in Fig. 5.
The operation of the above-described embodiment will be described next. In the embodiment, the display controller 1 generates the address a2 in the order of caster scanning for accessing the video memory 2. The video memory 2 outputs the display data d2 in the order of caster scanning.
CPU 3 changes the data assigned fixedly and in the order of raster scanning to the video memory 2, to the data d1. The above operation is the same as that of a conventional apparatus.
Next, the operation of the address translator 4 will be described. In writing data in the video memory 2 using a program of CPU 3, the address translator 4 translates the address al accessed by CPU 3 to the address a3 such that the address generated by the display controller 1 in the order of raster scanning can be translated as desired in accordance with the contents of the data to be written so as to satisfy the program of CPU 3.
In this case, CPU 3 writes in advance the address translation data d3.
In data writing, the corresponding addresses of the video memory 2 are written in the address translator 4 at addresses "0" to "7" as shown in Fig. 2.
This pre-process allows the following operation. Consider the case where CPU 3 reads a character (e.g., "A") composed of 8 bits in the horizontal direction and 8 bits in the vertical direction as shown in Fig. 3(a) from a character generator memory at addresses "0" to "7", and writes it in the video memory 2 at addresses from "0" to "894" at the interval of every "128-th" addresses as shown in Fig. 3(b). In this case, the address translator 4 outputs the address a3 to the video memory 2 so that the video memory 2 can be accesses by using consecutive addresses for the addresses from "0" to "7".
Specifically, CPU 3 reads the character generator read-only memory at addresses from "0" to "7", and writes the data d1 in the video memory 2 at the addresses from "0" to "894" at the interval of every "128-th" addresses. In reading the character generator read-only memory, the consecutive 8 bytes are accessed, and also in writing into the video memory 2, the consecutive addresses for the addresses from "0" to "7" can be accessed.
According to the present embodiment, therefore, if for example a display area is divided into areas for character data and image data which are displayed at the same time, the address translator 4 constructed of a random access memory may be written such that address translation data is provided for the character display area as in the above embodiment, and address translation data is not provided for the image display area.
Furthermore, in the case where characters of different sizes are displayed at the same time, translated addresses corresponding to the positions of characters to be displayed can be properly determined as desired in accordance with the sizes of characters and stored in the address translator 4.
Still further in the case that the same character pattern or image is copied to another position of the same display screen, the pattern or image can be copied not by accessing the video memory 2 but by accessing only the address translator 4 constructed of a random access memory.
The above embodiment will further be described using a particular example of an image on the screen.
It is assumed that n lines of 8 x 8 dot characters are displayed on the upper area of a display screen, and a figure is displayed on the area under the upper area.
In such a case, for a program of CPU 3, it is preferable that the character pattern for each character on the character area can be written using consecutive addresses, and that the figure can be written using addresses of the video memory 2 without translation ("preferable" means that a program can be made which is easy to understand and easy to speed up the access time).
According to the present invention, such a preferable condition can be easily realized by properly writing the contents of the address translator 4 constructed of a random access memory.
Namely, as the contents of the address translator 4 constructed of a random access memory for the n line character display area, addresses those starting from 0 and following integer multiples of 128 such as explained with Fig. 2 are written in the address translator 4 constructed of a random access memory.
As the contents of the address translator 4 constructed of a random access memory for the display area other than the character display area, the same addresses for the video memory are written.
As described above, according to the present invention, using the contents of the address translator 4 constructed of a random access memory, the order of addresses of the video memory 2 can be changed as desired most properly for an image display program. Easy programming and high speed processing can be effectively realized for a bit map display controlling apparatus which displays freely a complicated combination of characters of desired sizes, figures, and graphics images.

INDUSTRIAL APPLICABILITY

As apparent from the above-described embodiment of the present invention, in writing data in a video memory using a program of CPU, CPU writes a translation data of an address from CPU for accessing the video memory, into an address translator. The address translator outputs a translated address of the address from CPU to the video memory. Thus, the address from CPU can be changed as desired so as to satisfy the program, thereby reducing the load of the CPU program.

Claims

A bit map display controlling apparatus comprising:
a video memory for storing raster scan type display contents, a data in said video memory being capable of changed as desired by a central processing unit of a stored-program type;
a display controller for generating a signal and address for accessing said video memory in a predetermined order, synchronously with raster scanning; and
an address translator for translating as desired, when said central processing unit writes a data in said video memory using a program of said central processing unit, addresses in the order of raster scanning in accordance with the contents of said data so as to satisfy said program, and supplying addresses for accessing said video memory.