DE69838852D1 - Verfahren und vorrichtung zur kopplung von signalen zwischen zwei schaltungen, in verschiedenen taktbereichen arbeitend - Google Patents

Verfahren und vorrichtung zur kopplung von signalen zwischen zwei schaltungen, in verschiedenen taktbereichen arbeitend

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Publication number
DE69838852D1
DE69838852D1 DE69838852T DE69838852T DE69838852D1 DE 69838852 D1 DE69838852 D1 DE 69838852D1 DE 69838852 T DE69838852 T DE 69838852T DE 69838852 T DE69838852 T DE 69838852T DE 69838852 D1 DE69838852 D1 DE 69838852D1
Authority
DE
Germany
Prior art keywords
signal
circuit
coupling
gates
output signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69838852T
Other languages
English (en)
Other versions
DE69838852T2 (de
Inventor
Troy A Manning
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of DE69838852D1 publication Critical patent/DE69838852D1/de
Application granted granted Critical
Publication of DE69838852T2 publication Critical patent/DE69838852T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H04L7/0012—Synchronisation information channels, e.g. clock distribution lines by comparing receiver clock with transmitter clock
DE69838852T 1997-10-10 1998-10-13 Verfahren und vorrichtung zur kopplung von signalen zwischen zwei schaltungen, in verschiedenen taktbereichen arbeitend Expired - Lifetime DE69838852T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/948,712 US6000022A (en) 1997-10-10 1997-10-10 Method and apparatus for coupling signals between two circuits operating in different clock domains
US948712 1997-10-10
PCT/US1998/021582 WO1999019786A1 (en) 1997-10-10 1998-10-13 Method and apparatus for coupling signals between two circuits operating in different clock domains

Publications (2)

Publication Number Publication Date
DE69838852D1 true DE69838852D1 (de) 2008-01-24
DE69838852T2 DE69838852T2 (de) 2008-12-11

Family

ID=25488173

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69838852T Expired - Lifetime DE69838852T2 (de) 1997-10-10 1998-10-13 Verfahren und vorrichtung zur kopplung von signalen zwischen zwei schaltungen, in verschiedenen taktbereichen arbeitend

Country Status (6)

Country Link
US (2) US6000022A (de)
EP (1) EP1040404B1 (de)
AT (1) ATE381051T1 (de)
AU (1) AU1082099A (de)
DE (1) DE69838852T2 (de)
WO (1) WO1999019786A1 (de)

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US6661554B2 (en) * 2001-08-23 2003-12-09 Cyoptics (Israel) Ltd. Biasing of an electro-optical component
US6920540B2 (en) 2001-10-22 2005-07-19 Rambus Inc. Timing calibration apparatus and method for a memory device signaling system
US6959398B2 (en) * 2001-12-31 2005-10-25 Hewlett-Packard Development Company, L.P. Universal asynchronous boundary module
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US7310396B1 (en) 2003-03-28 2007-12-18 Xilinx, Inc. Asynchronous FIFO buffer for synchronizing data transfers between clock domains
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US7272672B1 (en) 2003-04-01 2007-09-18 Extreme Networks, Inc. High speed bus with flow control and extended burst enhancements between sender and receiver wherein counter is maintained at sender for free buffer space available
US7366935B1 (en) * 2003-04-01 2008-04-29 Extreme Networks, Inc. High speed bus with alignment, re-timing and buffer underflow/overflow detection enhancements
US6987404B2 (en) * 2003-10-10 2006-01-17 Via Technologies, Inc. Synchronizer apparatus for synchronizing data from one clock domain to another clock domain
US20050259692A1 (en) * 2004-05-19 2005-11-24 Zerbe Jared L Crosstalk minimization in serial link systems
US7526704B2 (en) * 2005-08-23 2009-04-28 Micron Technology, Inc. Testing system and method allowing adjustment of signal transmit timing
US8001409B2 (en) * 2007-05-18 2011-08-16 Globalfoundries Inc. Synchronization device and methods thereof
US7882385B2 (en) * 2007-12-05 2011-02-01 International Business Machines Corporation Reducing inefficiencies of multi-clock-domain interfaces using a modified latch bank
DE102008004857B4 (de) * 2008-01-17 2013-08-22 Entropic Communications, Inc. Verfahren zur Übertragung von Daten zwischen wenigstens zwei Taktdomänen
KR100942978B1 (ko) * 2008-07-10 2010-02-17 주식회사 하이닉스반도체 반도체 메모리 소자
US8332661B2 (en) * 2008-09-11 2012-12-11 Mostovych Andrew N Method and apparatus for prevention of tampering, unauthorized use, and unauthorized extraction of information from microdevices
TW201044791A (en) * 2009-04-24 2010-12-16 Integrated Device Tech Clock, frequency reference, and other reference signal generator with frequency stability over temperature variation
US8397195B2 (en) * 2010-01-22 2013-03-12 Synopsys, Inc. Method and system for packet switch based logic replication
US8638792B2 (en) 2010-01-22 2014-01-28 Synopsys, Inc. Packet switch based logic replication
US9438256B2 (en) 2014-06-03 2016-09-06 Apple Inc. Slow to fast clock synchronization
US9607674B1 (en) * 2016-01-06 2017-03-28 Qualcomm Incorporated Pulse latch reset tracking at high differential voltage

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JP4040140B2 (ja) 1997-05-14 2008-01-30 富士通株式会社 半導体装置及びそのアクセスタイム調整方法
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Also Published As

Publication number Publication date
ATE381051T1 (de) 2007-12-15
WO1999019786A1 (en) 1999-04-22
US6366991B1 (en) 2002-04-02
AU1082099A (en) 1999-05-03
EP1040404B1 (de) 2007-12-12
US6000022A (en) 1999-12-07
DE69838852T2 (de) 2008-12-11
EP1040404A1 (de) 2000-10-04

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