DE69620945T2 - Skalierte, adaptive Lithographie - Google Patents

Skalierte, adaptive Lithographie

Info

Publication number
DE69620945T2
DE69620945T2 DE69620945T DE69620945T DE69620945T2 DE 69620945 T2 DE69620945 T2 DE 69620945T2 DE 69620945 T DE69620945 T DE 69620945T DE 69620945 T DE69620945 T DE 69620945T DE 69620945 T2 DE69620945 T2 DE 69620945T2
Authority
DE
Germany
Prior art keywords
scaled
adaptive lithography
lithography
adaptive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69620945T
Other languages
English (en)
Other versions
DE69620945D1 (de
Inventor
Leonard Richard Douglas
Richard Joseph Sala
Kevin Matthew Durocher
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Electric Co
Original Assignee
General Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Electric Co filed Critical General Electric Co
Publication of DE69620945D1 publication Critical patent/DE69620945D1/de
Application granted granted Critical
Publication of DE69620945T2 publication Critical patent/DE69620945T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides
DE69620945T 1995-05-30 1996-05-20 Skalierte, adaptive Lithographie Expired - Fee Related DE69620945T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/453,110 US5844810A (en) 1995-05-30 1995-05-30 Scaled adaptive lithography

Publications (2)

Publication Number Publication Date
DE69620945D1 DE69620945D1 (de) 2002-06-06
DE69620945T2 true DE69620945T2 (de) 2002-12-12

Family

ID=23799247

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69620945T Expired - Fee Related DE69620945T2 (de) 1995-05-30 1996-05-20 Skalierte, adaptive Lithographie

Country Status (5)

Country Link
US (1) US5844810A (de)
EP (1) EP0746020B1 (de)
JP (1) JP4100728B2 (de)
CA (1) CA2176880C (de)
DE (1) DE69620945T2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6003715A (en) * 1998-09-15 1999-12-21 Harris; Walter H. Plastic bucket air vent and method
US6330708B1 (en) * 1998-09-17 2001-12-11 International Business Machines Corporation Method for preparing command files for photomask production
US6622295B1 (en) * 2000-07-05 2003-09-16 Dupont Photomasks, Inc. Network-based photomask data entry interface and instruction generator for manufacturing photomasks
US6760640B2 (en) * 2002-03-14 2004-07-06 Photronics, Inc. Automated manufacturing system and method for processing photomasks
US7669167B2 (en) * 2002-07-30 2010-02-23 Photronics, Inc. Rule based system and method for automatically generating photomask orders by conditioning information from a customer's computer system
US7269813B2 (en) * 2004-11-19 2007-09-11 Alcatel Off-width pitch for improved circuit card routing
US9595485B2 (en) * 2014-06-26 2017-03-14 Nxp Usa, Inc. Microelectronic packages having embedded sidewall substrates and methods for the producing thereof

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4933042A (en) * 1986-09-26 1990-06-12 General Electric Company Method for packaging integrated circuit chips employing a polymer film overlay layer
US4783695A (en) * 1986-09-26 1988-11-08 General Electric Company Multichip integrated circuit packaging configuration and method
US4835704A (en) * 1986-12-29 1989-05-30 General Electric Company Adaptive lithography system to provide high density interconnect
GB2202673B (en) * 1987-03-26 1990-11-14 Haroon Ahmed The semi-conductor fabrication
US4972311A (en) * 1988-08-15 1990-11-20 Kulicke And Soffa Industries Inc. X-Y table error mapping apparatus and method
US5019946A (en) * 1988-09-27 1991-05-28 General Electric Company High density interconnect with high volumetric efficiency
US4894115A (en) * 1989-02-14 1990-01-16 General Electric Company Laser beam scanning method for forming via holes in polymer materials
US5019997A (en) * 1989-06-05 1991-05-28 General Electric Company Adaptive lithography accommodation of tolerances in chip positioning in high density interconnection structures
US5161093A (en) * 1990-07-02 1992-11-03 General Electric Company Multiple lamination high density interconnect process and structure employing a variable crosslinking adhesive
US5257178A (en) * 1991-12-19 1993-10-26 General Electric Company Method of optimally operating a computer numerical control milling machine to mill optimal high density interconnect substrates
US5285571A (en) * 1992-10-13 1994-02-15 General Electric Company Method for extending an electrical conductor over an edge of an HDI substrate
US5324687A (en) * 1992-10-16 1994-06-28 General Electric Company Method for thinning of integrated circuit chips for lightweight packaged electronic systems
US5355306A (en) * 1993-09-30 1994-10-11 Motorola, Inc. Alignment system and method of alignment by symmetrical and asymmetrical analysis
US5506793A (en) * 1994-01-14 1996-04-09 Gerber Systems Corporation Method and apparatus for distortion compensation in an automatic optical inspection system

Also Published As

Publication number Publication date
CA2176880C (en) 2007-11-13
EP0746020A3 (de) 1997-07-02
CA2176880A1 (en) 1996-12-01
JP4100728B2 (ja) 2008-06-11
EP0746020A2 (de) 1996-12-04
DE69620945D1 (de) 2002-06-06
US5844810A (en) 1998-12-01
JPH09102576A (ja) 1997-04-15
EP0746020B1 (de) 2002-05-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: ROEGER UND KOLLEGEN, 73728 ESSLINGEN

8339 Ceased/non-payment of the annual fee