DE69422120D1 - Synchroner dynamischer Speicher mit wahlfreiem Zugriff - Google Patents

Synchroner dynamischer Speicher mit wahlfreiem Zugriff

Info

Publication number
DE69422120D1
DE69422120D1 DE69422120T DE69422120T DE69422120D1 DE 69422120 D1 DE69422120 D1 DE 69422120D1 DE 69422120 T DE69422120 T DE 69422120T DE 69422120 T DE69422120 T DE 69422120T DE 69422120 D1 DE69422120 D1 DE 69422120D1
Authority
DE
Germany
Prior art keywords
random access
dynamic memory
synchronous dynamic
synchronous
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69422120T
Other languages
English (en)
Other versions
DE69422120T2 (de
Inventor
Haruki Toda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE69422120D1 publication Critical patent/DE69422120D1/de
Application granted granted Critical
Publication of DE69422120T2 publication Critical patent/DE69422120T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/103—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/105—Aspects related to pads, pins or terminals
DE69422120T 1993-09-29 1994-09-29 Synchroner dynamischer Speicher mit wahlfreiem Zugriff Expired - Lifetime DE69422120T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP05242932A JP3099931B2 (ja) 1993-09-29 1993-09-29 半導体装置

Publications (2)

Publication Number Publication Date
DE69422120D1 true DE69422120D1 (de) 2000-01-20
DE69422120T2 DE69422120T2 (de) 2000-05-25

Family

ID=17096366

Family Applications (2)

Application Number Title Priority Date Filing Date
DE69429289T Expired - Lifetime DE69429289T2 (de) 1993-09-29 1994-09-29 Synchroner dynamischer Direktzugriffspeicher
DE69422120T Expired - Lifetime DE69422120T2 (de) 1993-09-29 1994-09-29 Synchroner dynamischer Speicher mit wahlfreiem Zugriff

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE69429289T Expired - Lifetime DE69429289T2 (de) 1993-09-29 1994-09-29 Synchroner dynamischer Direktzugriffspeicher

Country Status (5)

Country Link
US (9) US5596541A (de)
EP (2) EP0902433B1 (de)
JP (1) JP3099931B2 (de)
KR (1) KR0139874B1 (de)
DE (2) DE69429289T2 (de)

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Publication number Priority date Publication date Assignee Title
JP3099931B2 (ja) * 1993-09-29 2000-10-16 株式会社東芝 半導体装置
JP3351692B2 (ja) * 1995-09-12 2002-12-03 株式会社東芝 シンクロナス半導体メモリ装置
JPH09161476A (ja) 1995-10-04 1997-06-20 Toshiba Corp 半導体メモリ及びそのテスト回路、並びにデ−タ転送システム
JPH09223389A (ja) * 1996-02-15 1997-08-26 Mitsubishi Electric Corp 同期型半導体記憶装置
US5953278A (en) * 1996-07-11 1999-09-14 Texas Instruments Incorporated Data sequencing and registering in a four bit pre-fetch SDRAM
JPH1055674A (ja) * 1996-08-09 1998-02-24 Nec Corp 半導体記憶装置
US5802005A (en) * 1996-09-23 1998-09-01 Texas Instruments Incorporated Four bit pre-fetch sDRAM column select architecture
JP3280867B2 (ja) * 1996-10-03 2002-05-13 シャープ株式会社 半導体記憶装置
JP3317187B2 (ja) * 1997-04-25 2002-08-26 日本電気株式会社 半導体記憶装置
EP1895538A1 (de) * 1997-10-10 2008-03-05 Rambus, Inc. Vorrichtung und Verfahren für geleitete Speicherbetriebe
JP3334589B2 (ja) * 1998-01-13 2002-10-15 日本電気株式会社 信号遅延装置及び半導体記憶装置
US6295231B1 (en) * 1998-07-17 2001-09-25 Kabushiki Kaisha Toshiba High-speed cycle clock-synchronous memory device
KR100306966B1 (ko) * 1998-08-04 2001-11-30 윤종용 동기형버스트반도체메모리장치
KR100306965B1 (ko) * 1998-08-07 2001-11-30 윤종용 동기형반도체메모리장치의데이터전송회로
JP2000137983A (ja) * 1998-08-26 2000-05-16 Toshiba Corp 半導体記憶装置
KR100287190B1 (ko) 1999-04-07 2001-04-16 윤종용 선택되는 메모리 모듈만을 데이터 라인에 연결하는 메모리 모듈 시스템 및 이를 이용한 데이터 입출력 방법
KR100507855B1 (ko) * 1999-07-14 2005-08-17 주식회사 하이닉스반도체 디디알 에스디램의 읽기 동작을 위한 데이터 스위치 제어 신호발생 회로
JP4083944B2 (ja) * 1999-12-13 2008-04-30 東芝マイクロエレクトロニクス株式会社 半導体記憶装置
US6473838B1 (en) * 2000-01-04 2002-10-29 International Business Machines Corporation Data transfer system for multiple network processors using dual DRAM storage
JP2001344976A (ja) * 2000-06-05 2001-12-14 Mitsubishi Electric Corp 半導体集積回路
US6438062B1 (en) 2000-07-28 2002-08-20 International Business Machines Corporation Multiple memory bank command for synchronous DRAMs
US6501698B1 (en) * 2000-11-01 2002-12-31 Enhanced Memory Systems, Inc. Structure and method for hiding DRAM cycle time behind a burst access
JP2002222590A (ja) * 2001-01-24 2002-08-09 Nec Corp センスアンプ及び半導体記憶装置
KR100414715B1 (ko) * 2001-07-03 2004-01-13 (주)실리콘세븐 메모리 어레이별 구동이 가능한 분할 워드라인 구조의반도체 메모리 장치
JP2003281890A (ja) * 2002-03-25 2003-10-03 Mitsubishi Electric Corp 同期型半導体記憶装置
US7423982B2 (en) * 2002-09-09 2008-09-09 Scientific-Atlanta, Inc. Adaptive communication modes
JP4326226B2 (ja) * 2003-01-20 2009-09-02 Ｏｋｉセミコンダクタ株式会社 半導体集積回路
US6754134B1 (en) * 2003-09-25 2004-06-22 International Business Machines Corporation Semiconductor storage device having multiple interrupt feature for continuous burst read and write operation
JP2005339604A (ja) * 2004-05-24 2005-12-08 Nec Electronics Corp 半導体記憶装置
KR100615580B1 (ko) * 2005-07-05 2006-08-25 삼성전자주식회사 반도체 메모리 장치 및 이 장치의 데이터 입출력 방법과이를 구비한 메모리 시스템
TWI318235B (en) * 2005-08-29 2009-12-11 Univ Chung Yuan Christian Liquid crystal composite material
KR100999875B1 (ko) 2008-10-06 2010-12-09 주식회사 하이닉스반도체 버스트길이 제어회로 및 이를 이용한 반도체 메모리 장치
JP4947395B2 (ja) * 2010-01-07 2012-06-06 横河電機株式会社 半導体試験装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US35723A (en) * 1862-06-24 S improvement
KR960003526B1 (ko) * 1992-10-02 1996-03-14 삼성전자주식회사 반도체 메모리장치
US4630230A (en) * 1983-04-25 1986-12-16 Cray Research, Inc. Solid state storage device
JPS60157798A (ja) * 1984-01-26 1985-08-19 Toshiba Corp 半導体メモリ
US4800530A (en) * 1986-08-19 1989-01-24 Kabushiki Kasiha Toshiba Semiconductor memory system with dynamic random access memory cells
KR100214435B1 (ko) * 1990-07-25 1999-08-02 사와무라 시코 동기식 버스트 엑세스 메모리
JPH04247393A (ja) 1991-02-01 1992-09-03 Nec Corp 半導体記憶装置
JP3992757B2 (ja) * 1991-04-23 2007-10-17 テキサス インスツルメンツ インコーポレイテツド マイクロプロセッサと同期するメモリ、及びデータプロセッサ、同期メモリ、周辺装置とシステムクロックを含むシステム
JPH0521753A (ja) 1991-07-09 1993-01-29 Mitsubishi Electric Corp 半導体記憶装置
JPH05182455A (ja) 1991-12-30 1993-07-23 Sony Corp メモリ装置
JPH05234377A (ja) 1992-02-20 1993-09-10 Sanyo Electric Co Ltd 半導体記憶装置
US5594704A (en) * 1992-04-27 1997-01-14 Mitsubishi Denki Kabushiki Kaisha Synchronous semiconductor memory device
US5384745A (en) * 1992-04-27 1995-01-24 Mitsubishi Denki Kabushiki Kaisha Synchronous semiconductor memory device
JP3073610B2 (ja) * 1992-09-22 2000-08-07 株式会社東芝 半導体記憶装置
JPH06259370A (ja) * 1993-03-09 1994-09-16 Hitachi Ltd データ処理システムおよびそれに使用されるプロセッサ
JP3346827B2 (ja) * 1993-05-25 2002-11-18 三菱電機株式会社 同期型半導体記憶装置
AU6988494A (en) * 1993-05-28 1994-12-20 Rambus Inc. Method and apparatus for implementing refresh in a synchronous dram system
JPH07111083A (ja) * 1993-08-20 1995-04-25 Mitsubishi Electric Corp 半導体記憶装置
JP3099931B2 (ja) * 1993-09-29 2000-10-16 株式会社東芝 半導体装置
US5412613A (en) * 1993-12-06 1995-05-02 International Business Machines Corporation Memory device having asymmetrical CAS to data input/output mapping and applications thereof
US5386385A (en) * 1994-01-31 1995-01-31 Texas Instruments Inc. Method and apparatus for preventing invalid operating modes and an application to synchronous memory devices
US5450364A (en) * 1994-01-31 1995-09-12 Texas Instruments Incorporated Method and apparatus for production testing of self-refresh operations and a particular application to synchronous memory devices
US5539696A (en) * 1994-01-31 1996-07-23 Patel; Vipul C. Method and apparatus for writing data in a synchronous memory having column independent sections and a method and apparatus for performing write mask operations
JPH08167285A (ja) * 1994-12-07 1996-06-25 Toshiba Corp 半導体記憶装置
JPH0955482A (ja) * 1995-06-08 1997-02-25 Mitsubishi Electric Corp 半導体記憶装置
JPH09139071A (ja) * 1995-11-14 1997-05-27 Toshiba Corp 半導体記憶装置
JPH09198861A (ja) * 1996-01-16 1997-07-31 Mitsubishi Electric Corp 同期型半導体記憶装置
JPH09288888A (ja) * 1996-04-22 1997-11-04 Mitsubishi Electric Corp 半導体記憶装置
US5717645A (en) * 1997-02-07 1998-02-10 Alliance Semiconductor Corporation Random access memory with fast, compact sensing and selection architecture
JP3825862B2 (ja) * 1997-02-27 2006-09-27 株式会社ルネサステクノロジ 同期型ダイナミック型半導体記憶装置
US5949732A (en) * 1997-09-11 1999-09-07 International Business Machines Corporation Method of structuring a multi-bank DRAM into a hierarchical column select line architecture

Also Published As

Publication number Publication date
US20030031078A1 (en) 2003-02-13
JPH0798981A (ja) 1995-04-11
US6144615A (en) 2000-11-07
US20020059323A1 (en) 2002-05-16
EP0646928A2 (de) 1995-04-05
EP0902433A3 (de) 1999-06-02
EP0646928A3 (de) 1996-04-24
DE69429289T2 (de) 2002-08-14
US6018491A (en) 2000-01-25
US6928028B2 (en) 2005-08-09
US6646955B2 (en) 2003-11-11
US20050057989A1 (en) 2005-03-17
US6816433B2 (en) 2004-11-09
US5715211A (en) 1998-02-03
KR0139874B1 (ko) 1998-08-17
US20030185089A1 (en) 2003-10-02
DE69422120T2 (de) 2000-05-25
EP0902433A2 (de) 1999-03-17
US6487142B2 (en) 2002-11-26
EP0646928B1 (de) 1999-12-15
EP0902433B1 (de) 2001-11-28
DE69429289D1 (de) 2002-01-10
KR950009711A (ko) 1995-04-24
JP3099931B2 (ja) 2000-10-16
US5596541A (en) 1997-01-21
US6377503B1 (en) 2002-04-23

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