EP0651321B1
(de)
*
|
1993-10-29 |
2001-11-14 |
Advanced Micro Devices, Inc. |
Superskalarmikroprozessoren
|
US5574928A
(en)
*
|
1993-10-29 |
1996-11-12 |
Advanced Micro Devices, Inc. |
Mixed integer/floating point processor core for a superscalar microprocessor with a plurality of operand buses for transferring operand segments
|
US5339266A
(en)
*
|
1993-11-29 |
1994-08-16 |
Motorola, Inc. |
Parallel method and apparatus for detecting and completing floating point operations involving special operands
|
EP0685794A1
(de)
*
|
1994-06-01 |
1995-12-06 |
Advanced Micro Devices, Inc. |
System zum Erzeugen von Fliesskomma-Prüfvektoren
|
US5696955A
(en)
*
|
1994-06-01 |
1997-12-09 |
Advanced Micro Devices, Inc. |
Floating point stack and exchange instruction
|
US5632023A
(en)
*
|
1994-06-01 |
1997-05-20 |
Advanced Micro Devices, Inc. |
Superscalar microprocessor including flag operand renaming and forwarding apparatus
|
US5574670A
(en)
*
|
1994-08-24 |
1996-11-12 |
Advanced Micro Devices, Inc. |
Apparatus and method for determining a number of digits leading a particular digit
|
US5550767A
(en)
*
|
1994-10-14 |
1996-08-27 |
Ibm Corporation |
Method and apparatus for detecting underflow and overflow
|
US5583805A
(en)
*
|
1994-12-09 |
1996-12-10 |
International Business Machines Corporation |
Floating-point processor having post-writeback spill stage
|
US5903741A
(en)
*
|
1995-01-25 |
1999-05-11 |
Advanced Micro Devices, Inc. |
Method of allocating a fixed reorder buffer storage line for execution results regardless of a number of concurrently dispatched instructions
|
US5878244A
(en)
*
|
1995-01-25 |
1999-03-02 |
Advanced Micro Devices, Inc. |
Reorder buffer configured to allocate storage capable of storing results corresponding to a maximum number of concurrently receivable instructions regardless of a number of instructions received
|
US6237082B1
(en)
|
1995-01-25 |
2001-05-22 |
Advanced Micro Devices, Inc. |
Reorder buffer configured to allocate storage for instruction results corresponding to predefined maximum number of concurrently receivable instructions independent of a number of instructions received
|
US5901302A
(en)
*
|
1995-01-25 |
1999-05-04 |
Advanced Micro Devices, Inc. |
Superscalar microprocessor having symmetrical, fixed issue positions each configured to execute a particular subset of instructions
|
US5668984A
(en)
*
|
1995-02-27 |
1997-09-16 |
International Business Machines Corporation |
Variable stage load path and method of operation
|
US5646875A
(en)
*
|
1995-02-27 |
1997-07-08 |
International Business Machines Corporation |
Denormalization system and method of operation
|
US5687106A
(en)
*
|
1995-03-31 |
1997-11-11 |
International Business Machines Corporation |
Implementation of binary floating point using hexadecimal floating point unit
|
US5764946A
(en)
*
|
1995-04-12 |
1998-06-09 |
Advanced Micro Devices |
Superscalar microprocessor employing a way prediction unit to predict the way of an instruction fetch address and to concurrently provide a branch prediction address corresponding to the fetch address
|
US5822574A
(en)
*
|
1995-04-12 |
1998-10-13 |
Advanced Micro Devices, Inc. |
Functional unit with a pointer for mispredicted resolution, and a superscalar microprocessor employing the same
|
JPH09507941A
(ja)
*
|
1995-04-18 |
1997-08-12 |
インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン |
multiply−add浮動小数点シーケンスにおけるウエイト・サイクルなしのブロック正規化
|
US5878266A
(en)
*
|
1995-09-26 |
1999-03-02 |
Advanced Micro Devices, Inc. |
Reservation station for a floating point processing unit
|
US5748516A
(en)
*
|
1995-09-26 |
1998-05-05 |
Advanced Micro Devices, Inc. |
Floating point processing unit with forced arithmetic results
|
US5761105A
(en)
*
|
1995-09-26 |
1998-06-02 |
Advanced Micro Devices, Inc. |
Reservation station including addressable constant store for a floating point processing unit
|
US5835744A
(en)
*
|
1995-11-20 |
1998-11-10 |
Advanced Micro Devices, Inc. |
Microprocessor configured to swap operands in order to minimize dependency checking logic
|
US5752259A
(en)
*
|
1996-03-26 |
1998-05-12 |
Advanced Micro Devices, Inc. |
Instruction cache configured to provide instructions to a microprocessor having a clock cycle time less than a cache access time of said instruction cache
|
US5764549A
(en)
*
|
1996-04-29 |
1998-06-09 |
International Business Machines Corporation |
Fast floating point result alignment apparatus
|
US6108769A
(en)
|
1996-05-17 |
2000-08-22 |
Advanced Micro Devices, Inc. |
Dependency table for reducing dependency checking hardware
|
US5918056A
(en)
*
|
1996-05-17 |
1999-06-29 |
Advanced Micro Devices, Inc. |
Segmentation suspend mode for real-time interrupt support
|
US5835511A
(en)
*
|
1996-05-17 |
1998-11-10 |
Advanced Micro Devices, Inc. |
Method and mechanism for checking integrity of byte enable signals
|
US6049863A
(en)
*
|
1996-07-24 |
2000-04-11 |
Advanced Micro Devices, Inc. |
Predecoding technique for indicating locations of opcode bytes in variable byte-length instructions within a superscalar microprocessor
|
US5903740A
(en)
*
|
1996-07-24 |
1999-05-11 |
Advanced Micro Devices, Inc. |
Apparatus and method for retiring instructions in excess of the number of accessible write ports
|
US5915110A
(en)
*
|
1996-07-26 |
1999-06-22 |
Advanced Micro Devices, Inc. |
Branch misprediction recovery in a reorder buffer having a future file
|
US5872943A
(en)
*
|
1996-07-26 |
1999-02-16 |
Advanced Micro Devices, Inc. |
Apparatus for aligning instructions using predecoded shift amounts
|
US5900013A
(en)
*
|
1996-07-26 |
1999-05-04 |
Advanced Micro Devices, Inc. |
Dual comparator scheme for detecting a wrap-around condition and generating a cancel signal for removing wrap-around buffer entries
|
US5872951A
(en)
*
|
1996-07-26 |
1999-02-16 |
Advanced Micro Design, Inc. |
Reorder buffer having a future file for storing speculative instruction execution results
|
US5946468A
(en)
*
|
1996-07-26 |
1999-08-31 |
Advanced Micro Devices, Inc. |
Reorder buffer having an improved future file for storing speculative instruction execution results
|
US5844830A
(en)
*
|
1996-08-07 |
1998-12-01 |
Sun Microsystems, Inc. |
Executing computer instrucrions by circuits having different latencies
|
US5765016A
(en)
*
|
1996-09-12 |
1998-06-09 |
Advanced Micro Devices, Inc. |
Reorder buffer configured to store both speculative and committed register states
|
US5822575A
(en)
*
|
1996-09-12 |
1998-10-13 |
Advanced Micro Devices, Inc. |
Branch prediction storage for storing branch prediction information such that a corresponding tag may be routed with the branch instruction
|
US5794028A
(en)
*
|
1996-10-17 |
1998-08-11 |
Advanced Micro Devices, Inc. |
Shared branch prediction structure
|
US5920710A
(en)
*
|
1996-11-18 |
1999-07-06 |
Advanced Micro Devices, Inc. |
Apparatus and method for modifying status bits in a reorder buffer with a large speculative state
|
US5870579A
(en)
*
|
1996-11-18 |
1999-02-09 |
Advanced Micro Devices, Inc. |
Reorder buffer including a circuit for selecting a designated mask corresponding to an instruction that results in an exception
|
US5978906A
(en)
*
|
1996-11-19 |
1999-11-02 |
Advanced Micro Devices, Inc. |
Branch selectors associated with byte ranges within an instruction cache for rapidly identifying branch predictions
|
US5995749A
(en)
*
|
1996-11-19 |
1999-11-30 |
Advanced Micro Devices, Inc. |
Branch prediction mechanism employing branch selectors to select a branch prediction
|
US5954816A
(en)
*
|
1996-11-19 |
1999-09-21 |
Advanced Micro Devices, Inc. |
Branch selector prediction
|
US6175906B1
(en)
|
1996-12-06 |
2001-01-16 |
Advanced Micro Devices, Inc. |
Mechanism for fast revalidation of virtual tags
|
US5870580A
(en)
*
|
1996-12-13 |
1999-02-09 |
Advanced Micro Devices, Inc. |
Decoupled forwarding reorder buffer configured to allocate storage in chunks for instructions having unresolved dependencies
|
US5881305A
(en)
*
|
1996-12-13 |
1999-03-09 |
Advanced Micro Devices, Inc. |
Register rename stack for a microprocessor
|
US5983321A
(en)
*
|
1997-03-12 |
1999-11-09 |
Advanced Micro Devices, Inc. |
Cache holding register for receiving instruction packets and for providing the instruction packets to a predecode unit and instruction cache
|
US5862065A
(en)
*
|
1997-02-13 |
1999-01-19 |
Advanced Micro Devices, Inc. |
Method and circuit for fast generation of zero flag condition code in a microprocessor-based computer
|
US5768555A
(en)
|
1997-02-20 |
1998-06-16 |
Advanced Micro Devices, Inc. |
Reorder buffer employing last in buffer and last in line bits
|
US6141740A
(en)
*
|
1997-03-03 |
2000-10-31 |
Advanced Micro Devices, Inc. |
Apparatus and method for microcode patching for generating a next address
|
US6233672B1
(en)
|
1997-03-06 |
2001-05-15 |
Advanced Micro Devices, Inc. |
Piping rounding mode bits with floating point instructions to eliminate serialization
|
US5852727A
(en)
*
|
1997-03-10 |
1998-12-22 |
Advanced Micro Devices, Inc. |
Instruction scanning unit for locating instructions via parallel scanning of start and end byte information
|
US5968163A
(en)
|
1997-03-10 |
1999-10-19 |
Advanced Micro Devices, Inc. |
Microcode scan unit for scanning microcode instructions using predecode data
|
US5850532A
(en)
*
|
1997-03-10 |
1998-12-15 |
Advanced Micro Devices, Inc. |
Invalid instruction scan unit for detecting invalid predecode data corresponding to instructions being fetched
|
US5859992A
(en)
*
|
1997-03-12 |
1999-01-12 |
Advanced Micro Devices, Inc. |
Instruction alignment using a dispatch list and a latch list
|
US5930492A
(en)
*
|
1997-03-19 |
1999-07-27 |
Advanced Micro Devices, Inc. |
Rapid pipeline control using a control word and a steering word
|
US5887185A
(en)
*
|
1997-03-19 |
1999-03-23 |
Advanced Micro Devices, Inc. |
Interface for coupling a floating point unit to a reorder buffer
|
US5828873A
(en)
*
|
1997-03-19 |
1998-10-27 |
Advanced Micro Devices, Inc. |
Assembly queue for a floating point unit
|
US5859998A
(en)
*
|
1997-03-19 |
1999-01-12 |
Advanced Micro Devices, Inc. |
Hierarchical microcode implementation of floating point instructions for a microprocessor
|
US5987235A
(en)
*
|
1997-04-04 |
1999-11-16 |
Advanced Micro Devices, Inc. |
Method and apparatus for predecoding variable byte length instructions for fast scanning of instructions
|
US5901076A
(en)
*
|
1997-04-16 |
1999-05-04 |
Advanced Micro Designs, Inc. |
Ripple carry shifter in a floating point arithmetic unit of a microprocessor
|
US5957997A
(en)
*
|
1997-04-25 |
1999-09-28 |
International Business Machines Corporation |
Efficient floating point normalization mechanism
|
US6003128A
(en)
*
|
1997-05-01 |
1999-12-14 |
Advanced Micro Devices, Inc. |
Number of pipeline stages and loop length related counter differential based end-loop prediction
|
US5845101A
(en)
*
|
1997-05-13 |
1998-12-01 |
Advanced Micro Devices, Inc. |
Prefetch buffer for storing instructions prior to placing the instructions in an instruction cache
|
US6122729A
(en)
|
1997-05-13 |
2000-09-19 |
Advanced Micro Devices, Inc. |
Prefetch buffer which stores a pointer indicating an initial predecode position
|
US5872946A
(en)
*
|
1997-06-11 |
1999-02-16 |
Advanced Micro Devices, Inc. |
Instruction alignment unit employing dual instruction queues for high frequency instruction dispatch
|
US6009511A
(en)
*
|
1997-06-11 |
1999-12-28 |
Advanced Micro Devices, Inc. |
Apparatus and method for tagging floating point operands and results for rapid detection of special floating point numbers
|
US5940602A
(en)
*
|
1997-06-11 |
1999-08-17 |
Advanced Micro Devices, Inc. |
Method and apparatus for predecoding variable byte length instructions for scanning of a number of RISC operations
|
US6073230A
(en)
*
|
1997-06-11 |
2000-06-06 |
Advanced Micro Devices, Inc. |
Instruction fetch unit configured to provide sequential way prediction for sequential instruction fetches
|
US5933629A
(en)
*
|
1997-06-12 |
1999-08-03 |
Advanced Micro Devices, Inc. |
Apparatus and method for detecting microbranches early
|
US5898865A
(en)
*
|
1997-06-12 |
1999-04-27 |
Advanced Micro Devices, Inc. |
Apparatus and method for predicting an end of loop for string instructions
|
US5933626A
(en)
*
|
1997-06-12 |
1999-08-03 |
Advanced Micro Devices, Inc. |
Apparatus and method for tracing microprocessor instructions
|
US5983337A
(en)
*
|
1997-06-12 |
1999-11-09 |
Advanced Micro Devices, Inc. |
Apparatus and method for patching an instruction by providing a substitute instruction or instructions from an external memory responsive to detecting an opcode of the instruction
|
US6012125A
(en)
*
|
1997-06-20 |
2000-01-04 |
Advanced Micro Devices, Inc. |
Superscalar microprocessor including a decoded instruction cache configured to receive partially decoded instructions
|
US5978901A
(en)
*
|
1997-08-21 |
1999-11-02 |
Advanced Micro Devices, Inc. |
Floating point and multimedia unit with data type reclassification capability
|
US5903479A
(en)
*
|
1997-09-02 |
1999-05-11 |
International Business Machines Corporation |
Method and system for executing denormalized numbers
|
US5931943A
(en)
*
|
1997-10-21 |
1999-08-03 |
Advanced Micro Devices, Inc. |
Floating point NaN comparison
|
US6032252A
(en)
*
|
1997-10-28 |
2000-02-29 |
Advanced Micro Devices, Inc. |
Apparatus and method for efficient loop control in a superscalar microprocessor
|
US5974542A
(en)
*
|
1997-10-30 |
1999-10-26 |
Advanced Micro Devices, Inc. |
Branch prediction unit which approximates a larger number of branch predictions using a smaller number of branch predictions and an alternate target indication
|
US6230259B1
(en)
|
1997-10-31 |
2001-05-08 |
Advanced Micro Devices, Inc. |
Transparent extended state save
|
US6157996A
(en)
*
|
1997-11-13 |
2000-12-05 |
Advanced Micro Devices, Inc. |
Processor programably configurable to execute enhanced variable byte length instructions including predicated execution, three operand addressing, and increased register space
|
US6199154B1
(en)
|
1997-11-17 |
2001-03-06 |
Advanced Micro Devices, Inc. |
Selecting cache to fetch in multi-level cache system based on fetch address source and pre-fetching additional data to the cache for future access
|
US6079003A
(en)
|
1997-11-20 |
2000-06-20 |
Advanced Micro Devices, Inc. |
Reverse TLB for providing branch target address in a microprocessor having a physically-tagged cache
|
US6154818A
(en)
*
|
1997-11-20 |
2000-11-28 |
Advanced Micro Devices, Inc. |
System and method of controlling access to privilege partitioned address space for a model specific register file
|
US6079005A
(en)
*
|
1997-11-20 |
2000-06-20 |
Advanced Micro Devices, Inc. |
Microprocessor including virtual address branch prediction and current page register to provide page portion of virtual and physical fetch address
|
US6516395B1
(en)
|
1997-11-20 |
2003-02-04 |
Advanced Micro Devices, Inc. |
System and method for controlling access to a privilege-partitioned address space with a fixed set of attributes
|
US5974432A
(en)
*
|
1997-12-05 |
1999-10-26 |
Advanced Micro Devices, Inc. |
On-the-fly one-hot encoding of leading zero count
|
US5870578A
(en)
*
|
1997-12-09 |
1999-02-09 |
Advanced Micro Devices, Inc. |
Workload balancing in a microprocessor for reduced instruction dispatch stalling
|
US6016533A
(en)
*
|
1997-12-16 |
2000-01-18 |
Advanced Micro Devices, Inc. |
Way prediction logic for cache array
|
US6016545A
(en)
*
|
1997-12-16 |
2000-01-18 |
Advanced Micro Devices, Inc. |
Reduced size storage apparatus for storing cache-line-related data in a high frequency microprocessor
|
US6157986A
(en)
*
|
1997-12-16 |
2000-12-05 |
Advanced Micro Devices, Inc. |
Fast linear tag validation unit for use in microprocessor
|
US6112296A
(en)
*
|
1997-12-18 |
2000-08-29 |
Advanced Micro Devices, Inc. |
Floating point stack manipulation using a register map and speculative top of stack values
|
US6112018A
(en)
|
1997-12-18 |
2000-08-29 |
Advanced Micro Devices, Inc. |
Apparatus for exchanging two stack registers
|
US6018798A
(en)
*
|
1997-12-18 |
2000-01-25 |
Advanced Micro Devices, Inc. |
Floating point unit using a central window for storing instructions capable of executing multiple instructions in a single clock cycle
|
US6175908B1
(en)
|
1998-04-30 |
2001-01-16 |
Advanced Micro Devices, Inc. |
Variable byte-length instructions using state of function bit of second byte of plurality of instructions bytes as indicative of whether first byte is a prefix byte
|
US6141745A
(en)
*
|
1998-04-30 |
2000-10-31 |
Advanced Micro Devices, Inc. |
Functional bit identifying a prefix byte via a particular state regardless of type of instruction
|
US6119223A
(en)
*
|
1998-07-31 |
2000-09-12 |
Advanced Micro Devices, Inc. |
Map unit having rapid misprediction recovery
|
US6122656A
(en)
*
|
1998-07-31 |
2000-09-19 |
Advanced Micro Devices, Inc. |
Processor configured to map logical register numbers to physical register numbers using virtual register numbers
|
US6230262B1
(en)
|
1998-07-31 |
2001-05-08 |
Advanced Micro Devices, Inc. |
Processor configured to selectively free physical registers upon retirement of instructions
|
US6442677B1
(en)
|
1999-06-10 |
2002-08-27 |
Advanced Micro Devices, Inc. |
Apparatus and method for superforwarding load operands in a microprocessor
|
US6408379B1
(en)
|
1999-06-10 |
2002-06-18 |
Advanced Micro Devices, Inc. |
Apparatus and method for executing floating-point store instructions in a microprocessor
|
US6487653B1
(en)
*
|
1999-08-25 |
2002-11-26 |
Advanced Micro Devices, Inc. |
Method and apparatus for denormal load handling
|
US6438664B1
(en)
|
1999-10-27 |
2002-08-20 |
Advanced Micro Devices, Inc. |
Microcode patch device and method for patching microcode using match registers and patch routines
|
US6442707B1
(en)
|
1999-10-29 |
2002-08-27 |
Advanced Micro Devices, Inc. |
Alternate fault handler
|
US6363523B1
(en)
*
|
1999-11-12 |
2002-03-26 |
Sun Microsystems, Inc. |
Optimization of N-base typed arithmetic expressions
|
US6981132B2
(en)
|
2000-08-09 |
2005-12-27 |
Advanced Micro Devices, Inc. |
Uniform register addressing using prefix byte
|
US6877084B1
(en)
|
2000-08-09 |
2005-04-05 |
Advanced Micro Devices, Inc. |
Central processing unit (CPU) accessing an extended register set in an extended register mode
|
US7062657B2
(en)
*
|
2000-09-25 |
2006-06-13 |
Broadcom Corporation |
Methods and apparatus for hardware normalization and denormalization
|
US20020078342A1
(en)
*
|
2000-09-25 |
2002-06-20 |
Broadcom Corporation |
E-commerce security processor alignment logic
|
US20020061107A1
(en)
*
|
2000-09-25 |
2002-05-23 |
Tham Terry K. |
Methods and apparatus for implementing a cryptography engine
|
US7080111B2
(en)
*
|
2001-06-04 |
2006-07-18 |
Intel Corporation |
Floating point multiply accumulator
|
US7373369B2
(en)
*
|
2003-06-05 |
2008-05-13 |
International Business Machines Corporation |
Advanced execution of extended floating-point add operations in a narrow dataflow
|
US20050050278A1
(en)
*
|
2003-09-03 |
2005-03-03 |
Advanced Micro Devices, Inc. |
Low power way-predicted cache
|
US7117290B2
(en)
*
|
2003-09-03 |
2006-10-03 |
Advanced Micro Devices, Inc. |
MicroTLB and micro tag for reducing power in a processor
|
TWI258698B
(en)
*
|
2004-04-06 |
2006-07-21 |
Ind Tech Res Inst |
Static floating-point processor suitable for embedded digital signal processing and shift control method thereof
|
US7698353B2
(en)
*
|
2005-09-14 |
2010-04-13 |
Freescale Semiconductor, Inc. |
Floating point normalization and denormalization
|
US7451171B1
(en)
|
2008-03-31 |
2008-11-11 |
International Business Machines Corporation |
Systems, methods and computer program products for hardware assists for microcoded floating point divide and square root
|
US20120084335A1
(en)
*
|
2010-10-03 |
2012-04-05 |
Hung-Ching Chen |
Method and apparatus of processing floating point number
|
US9128531B2
(en)
*
|
2012-02-22 |
2015-09-08 |
Arm Limited |
Operand special case handling for multi-lane processing
|
US10346133B1
(en)
*
|
2017-12-21 |
2019-07-09 |
Qualcomm Incorporated |
System and method of floating point multiply operation processing
|