DE69130693T2 - Eingebaute Selbstprüfung für integrierte Schaltungen - Google Patents

Eingebaute Selbstprüfung für integrierte Schaltungen

Info

Publication number
DE69130693T2
DE69130693T2 DE69130693T DE69130693T DE69130693T2 DE 69130693 T2 DE69130693 T2 DE 69130693T2 DE 69130693 T DE69130693 T DE 69130693T DE 69130693 T DE69130693 T DE 69130693T DE 69130693 T2 DE69130693 T2 DE 69130693T2
Authority
DE
Germany
Prior art keywords
built
self
test
integrated circuits
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69130693T
Other languages
English (en)
Other versions
DE69130693D1 (de
Inventor
Jeffrey Harris Dreibelbis
Erik Leigh Hedberg
John George Petrovick
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE69130693D1 publication Critical patent/DE69130693D1/de
Publication of DE69130693T2 publication Critical patent/DE69130693T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14Implementation of control logic, e.g. test mode decoders
    • G11C29/16Implementation of control logic, e.g. test mode decoders using microprogrammed units, e.g. state machines
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26Functional testing
    • G06F11/27Built-in tests
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44Indication or identification of errors, e.g. for repair
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/10Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38Response verification devices
DE69130693T 1990-08-31 1991-05-07 Eingebaute Selbstprüfung für integrierte Schaltungen Expired - Lifetime DE69130693T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/576,646 US5173906A (en) 1990-08-31 1990-08-31 Built-in self test for integrated circuits

Publications (2)

Publication Number Publication Date
DE69130693D1 DE69130693D1 (de) 1999-02-11
DE69130693T2 true DE69130693T2 (de) 1999-07-22

Family

ID=24305342

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69130693T Expired - Lifetime DE69130693T2 (de) 1990-08-31 1991-05-07 Eingebaute Selbstprüfung für integrierte Schaltungen

Country Status (4)

Country Link
US (1) US5173906A (de)
EP (1) EP0472818B1 (de)
JP (1) JPH06342040A (de)
DE (1) DE69130693T2 (de)

Cited By (2)

* Cited by examiner, † Cited by third party
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DE10158406A1 (de) * 2001-11-29 2003-06-12 Knorr Bremse Systeme Verfahren und Prüfeinrichtung zum Entdecken von Adressierungsfehlern in Steuergeräten
US9159456B2 (en) 2013-11-05 2015-10-13 Kabushiki Kaisha Toshiba Semiconductor device

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US5173906A (en) 1992-12-22
EP0472818B1 (de) 1998-12-30
JPH06342040A (ja) 1994-12-13
EP0472818A2 (de) 1992-03-04
DE69130693D1 (de) 1999-02-11
EP0472818A3 (en) 1992-04-22

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