DE602004031925D1 - Asynchrone system-on-a-chip-verbindung - Google Patents
Asynchrone system-on-a-chip-verbindungInfo
- Publication number
- DE602004031925D1 DE602004031925D1 DE602004031925T DE602004031925T DE602004031925D1 DE 602004031925 D1 DE602004031925 D1 DE 602004031925D1 DE 602004031925 T DE602004031925 T DE 602004031925T DE 602004031925 T DE602004031925 T DE 602004031925T DE 602004031925 D1 DE602004031925 D1 DE 602004031925D1
- Authority
- DE
- Germany
- Prior art keywords
- clock domain
- asynchronous
- synchronous
- converters
- domain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000001360 synchronised effect Effects 0.000 abstract 5
- 230000005540 biological transmission Effects 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
- G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
- H04L7/005—Correction by an elastic buffer
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q3/00—Selecting arrangements
- H04Q3/0004—Selecting arrangements using crossbar selectors in the switching stages
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0038—System on Chip
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5672—Multiplexing, e.g. coding, scrambling
- H04L2012/5674—Synchronisation, timing recovery or alignment
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
- H04L49/101—Packet switching elements characterised by the switching fabric construction using crossbar or matrix
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13034—A/D conversion, code compression/expansion
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13214—Clock signals
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13322—Integrated circuits
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13361—Synchronous systems
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13362—Asynchronous systems
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US44482003P | 2003-02-03 | 2003-02-03 | |
US10/634,597 US7239669B2 (en) | 2002-04-30 | 2003-08-04 | Asynchronous system-on-a-chip interconnect |
PCT/US2004/002216 WO2004070781A2 (en) | 2003-02-03 | 2004-01-26 | Asynchronous system-on-a-chip interconnect |
Publications (1)
Publication Number | Publication Date |
---|---|
DE602004031925D1 true DE602004031925D1 (de) | 2011-05-05 |
Family
ID=32776255
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE602004031925T Expired - Lifetime DE602004031925D1 (de) | 2003-02-03 | 2004-01-26 | Asynchrone system-on-a-chip-verbindung |
Country Status (5)
Country | Link |
---|---|
US (2) | US7239669B2 (de) |
EP (1) | EP1590835B1 (de) |
AT (1) | ATE503329T1 (de) |
DE (1) | DE602004031925D1 (de) |
WO (1) | WO2004070781A2 (de) |
Families Citing this family (77)
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US20060041693A1 (en) * | 2004-05-27 | 2006-02-23 | Stmicroelectronics S.R.L. | Asynchronous decoupler |
US7577847B2 (en) * | 2004-11-03 | 2009-08-18 | Igt | Location and user identification for online gaming |
US7584449B2 (en) * | 2004-11-22 | 2009-09-01 | Fulcrum Microsystems, Inc. | Logic synthesis of multi-level domino asynchronous pipelines |
US7415030B2 (en) * | 2005-02-10 | 2008-08-19 | International Business Machines Corporation | Data processing system, method and interconnect fabric having an address-based launch governor |
EP1859575A1 (de) * | 2005-03-04 | 2007-11-28 | Koninklijke Philips Electronics N.V. | Elektronische einrichtung und verfahren zum arbitrieren gemeinsam benutzter ressourcen |
US7990983B2 (en) * | 2005-03-31 | 2011-08-02 | Intel Corporation | Modular interconnect structure |
FR2884035B1 (fr) * | 2005-04-04 | 2007-06-22 | St Microelectronics Sa | Interfacage de cicrcuits dans un circuit electronique integre |
US7318126B2 (en) * | 2005-04-11 | 2008-01-08 | International Business Machines Corporation | Asynchronous symmetric multiprocessing |
CN100594463C (zh) * | 2005-06-01 | 2010-03-17 | 特克拉科技股份公司 | 为多个电路、集成电路和节点提供定时信号的方法及设备 |
US7769929B1 (en) | 2005-10-28 | 2010-08-03 | Altera Corporation | Design tool selection and implementation of port adapters |
US7779286B1 (en) * | 2005-10-28 | 2010-08-17 | Altera Corporation | Design tool clock domain crossing management |
US7447620B2 (en) * | 2006-02-23 | 2008-11-04 | International Business Machines Corporation | Modeling asynchronous behavior from primary inputs and latches |
WO2007095996A1 (en) * | 2006-02-23 | 2007-08-30 | Mentor Graphics Corp. | Cross-bar switching in an emulation environment |
US20080005402A1 (en) * | 2006-04-25 | 2008-01-03 | Samsung Electronics Co., Ltd. | Gals-based network-on-chip and data transfer method thereof |
US7504851B2 (en) * | 2006-04-27 | 2009-03-17 | Achronix Semiconductor Corporation | Fault tolerant asynchronous circuits |
US7505304B2 (en) * | 2006-04-27 | 2009-03-17 | Achronix Semiconductor Corporation | Fault tolerant asynchronous circuits |
DE102006025133A1 (de) * | 2006-05-30 | 2007-12-06 | Infineon Technologies Ag | Speicher- und Speicherkommunikationssystem |
US8031819B2 (en) * | 2006-10-27 | 2011-10-04 | Hewlett-Packard Development Company, L.P. | Systems and methods for synchronizing an input signal |
US7783808B2 (en) * | 2006-11-08 | 2010-08-24 | Honeywell International Inc. | Embedded self-checking asynchronous pipelined enforcement (escape) |
US7782991B2 (en) * | 2007-01-09 | 2010-08-24 | Freescale Semiconductor, Inc. | Fractionally related multirate signal processor and method |
US9026692B2 (en) | 2007-01-09 | 2015-05-05 | Aeroflex Colorado Springs Inc. | Data throttling circuit and method for a spacewire application |
US7746724B2 (en) * | 2007-01-31 | 2010-06-29 | Qimonda Ag | Asynchronous data transmission |
KR100850270B1 (ko) * | 2007-02-08 | 2008-08-04 | 삼성전자주식회사 | 페일비트 저장부를 갖는 반도체 메모리 장치 |
EP4198751A1 (de) * | 2007-04-12 | 2023-06-21 | Rambus Inc. | Speichersystem mit punkt-zu-punkt-anforderungsverbindung |
US7594047B2 (en) * | 2007-07-09 | 2009-09-22 | Hewlett-Packard Development Company, L.P. | Buffer circuit |
US7912068B2 (en) * | 2007-07-20 | 2011-03-22 | Oracle America, Inc. | Low-latency scheduling in large switches |
EP2026493A1 (de) * | 2007-08-16 | 2009-02-18 | STMicroelectronics S.r.l. | Verfahren und System für mesochrone Kommunikationen in mehreren Taktdomänen und entsprechendes Computerprogrammprodukt |
US7995618B1 (en) * | 2007-10-01 | 2011-08-09 | Teklatech A/S | System and a method of transmitting data from a first device to a second device |
US7882473B2 (en) | 2007-11-27 | 2011-02-01 | International Business Machines Corporation | Sequential equivalence checking for asynchronous verification |
US20110022754A1 (en) * | 2007-12-06 | 2011-01-27 | Technion Research & Development Foundation Ltd | Bus enhanced network on chip |
US7974278B1 (en) | 2007-12-12 | 2011-07-05 | Integrated Device Technology, Inc. | Packet switch with configurable virtual channels |
US8190942B2 (en) * | 2008-07-02 | 2012-05-29 | Cradle Ip, Llc | Method and system for distributing a global timebase within a system-on-chip having multiple clock domains |
US7907625B1 (en) * | 2008-08-04 | 2011-03-15 | Integrated Device Technology, Inc. | Power reduction technique for buffered crossbar switch |
US8122410B2 (en) * | 2008-11-05 | 2012-02-21 | International Business Machines Corporation | Specifying and validating untimed nets |
US8165255B2 (en) * | 2008-12-19 | 2012-04-24 | Freescale Semiconductor, Inc. | Multirate resampling and filtering system and method |
US8230152B2 (en) * | 2009-02-13 | 2012-07-24 | The Regents Of The University Of Michigan | Crossbar circuitry and method of operation of such crossbar circuitry |
US8549207B2 (en) * | 2009-02-13 | 2013-10-01 | The Regents Of The University Of Michigan | Crossbar circuitry for applying an adaptive priority scheme and method of operation of such crossbar circuitry |
US9514074B2 (en) | 2009-02-13 | 2016-12-06 | The Regents Of The University Of Michigan | Single cycle arbitration within an interconnect |
US8255610B2 (en) | 2009-02-13 | 2012-08-28 | The Regents Of The University Of Michigan | Crossbar circuitry for applying a pre-selection prior to arbitration between transmission requests and method of operation of such crossbar circuitry |
US8074193B2 (en) * | 2009-03-11 | 2011-12-06 | Institute of Computer Science (ICS) of the Foundation for Research & Technology Hellas-Foundation for Research and Technology Hellas (FORTH) | Apparatus and method for mixed single-rail and dual-rail combinational logic with completion detection |
US8352774B2 (en) | 2010-06-23 | 2013-01-08 | King Fahd University Of Petroleum And Minerals | Inter-clock domain data transfer FIFO circuit |
US8417867B2 (en) * | 2010-11-17 | 2013-04-09 | Xilinx, Inc. | Multichip module for communications |
EP2650794A1 (de) * | 2010-12-06 | 2013-10-16 | Fujitsu Limited | Informationsverarbeitungssystem und informationsübertragungsverfahren |
US8583850B2 (en) * | 2011-02-14 | 2013-11-12 | Oracle America, Inc. | Micro crossbar switch and on-die data network using the same |
DE102012220488A1 (de) * | 2012-11-09 | 2014-05-15 | Robert Bosch Gmbh | Teilnehmerstation für ein Bussystem und Verfahren zur Verbesserung der Empfangsqualität von Nachrichten bei einer Teilnehmerstation eines Bussystems |
CN103279442B (zh) * | 2013-06-14 | 2017-01-11 | 浪潮电子信息产业股份有限公司 | 一种高速互联总线的报文过滤系统及方法 |
GB2519414B (en) * | 2013-08-28 | 2016-01-06 | Imagination Tech Ltd | Crossing pipelined data between circuitry in different clock domains |
US9367286B2 (en) | 2013-08-28 | 2016-06-14 | Imagination Technologies Limited | Crossing pipelined data between circuitry in different clock domains |
US9325520B2 (en) * | 2013-09-06 | 2016-04-26 | Huawei Technologies Co., Ltd. | System and method for an asynchronous processor with scheduled token passing |
KR102206313B1 (ko) | 2014-02-07 | 2021-01-22 | 삼성전자주식회사 | 시스템 인터커넥트 및 시스템 인터커넥트의 동작 방법 |
US9520180B1 (en) | 2014-03-11 | 2016-12-13 | Hypres, Inc. | System and method for cryogenic hybrid technology computing and memory |
US10073139B2 (en) * | 2014-09-30 | 2018-09-11 | Oracle International Corporation | Cycle deterministic functional testing of a chip with asynchronous clock domains |
CN104636253A (zh) * | 2015-01-13 | 2015-05-20 | 浪潮电子信息产业股份有限公司 | 一种基于亚稳态注入的跨时钟域逻辑asic验证系统及方法 |
US10073939B2 (en) | 2015-11-04 | 2018-09-11 | Chronos Tech Llc | System and method for application specific integrated circuit design |
US9977853B2 (en) | 2015-11-04 | 2018-05-22 | Chronos Tech Llc | Application specific integrated circuit link |
US9977852B2 (en) * | 2015-11-04 | 2018-05-22 | Chronos Tech Llc | Application specific integrated circuit interconnect |
US11550982B2 (en) | 2015-11-04 | 2023-01-10 | Chronos Tech Llc | Application specific integrated circuit interconnect |
US10181939B2 (en) | 2016-07-08 | 2019-01-15 | Chronos Tech Llc | Systems and methods for the design and implementation of an input and output ports for circuit design |
US10331835B2 (en) | 2016-07-08 | 2019-06-25 | Chronos Tech Llc | ASIC design methodology for converting RTL HDL to a light netlist |
US9825636B1 (en) * | 2016-10-20 | 2017-11-21 | Arm Limited | Apparatus and method for reduced latency signal synchronization |
CN107277914B (zh) * | 2017-06-15 | 2018-06-29 | 深圳市晟碟半导体有限公司 | 一种无线mesh网络内设备时间同步控制方法及系统 |
US10637592B2 (en) | 2017-08-04 | 2020-04-28 | Chronos Tech Llc | System and methods for measuring performance of an application specific integrated circuit interconnect |
EP3884558A4 (de) | 2019-01-31 | 2022-08-17 | General Electric Company | Batterieladungs- und entladungsleistungssteuerung in einem stromnetz |
US11128742B2 (en) | 2019-03-08 | 2021-09-21 | Microsemi Storage Solutions, Inc. | Method for adapting a constant bit rate client signal into the path layer of a telecom signal |
US11087057B1 (en) | 2019-03-22 | 2021-08-10 | Chronos Tech Llc | System and method for application specific integrated circuit design related application information including a double nature arc abstraction |
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US10917097B1 (en) | 2019-12-24 | 2021-02-09 | Microsemi Semiconductor Ulc | Circuits and methods for transferring two differentially encoded client clock domains over a third carrier clock domain between integrated circuits |
US11239933B2 (en) | 2020-01-28 | 2022-02-01 | Microsemi Semiconductor Ulc | Systems and methods for transporting constant bit rate client signals over a packet transport network |
US11366647B2 (en) * | 2020-04-30 | 2022-06-21 | Intel Corporation | Automatic compiler dataflow optimization to enable pipelining of loops with local storage requirements |
US11424902B2 (en) | 2020-07-22 | 2022-08-23 | Microchip Technology Inc. | System and method for synchronizing nodes in a network device |
US20220358069A1 (en) * | 2021-05-07 | 2022-11-10 | Chronos Tech Llc | ADVANCED CENTRALIZED CHRONOS NoC |
US11916662B2 (en) | 2021-06-30 | 2024-02-27 | Microchip Technology Inc. | System and method for performing rate adaptation of constant bit rate (CBR) client data with a fixed number of idle blocks for transmission over a metro transport network (MTN) |
US11838111B2 (en) | 2021-06-30 | 2023-12-05 | Microchip Technology Inc. | System and method for performing rate adaptation of constant bit rate (CBR) client data with a variable number of idle blocks for transmission over a metro transport network (MTN) |
US11736065B2 (en) | 2021-10-07 | 2023-08-22 | Microchip Technology Inc. | Method and apparatus for conveying clock-related information from a timing device |
US11799626B2 (en) | 2021-11-23 | 2023-10-24 | Microchip Technology Inc. | Method and apparatus for carrying constant bit rate (CBR) client signals |
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-
2003
- 2003-08-04 US US10/634,597 patent/US7239669B2/en not_active Expired - Fee Related
-
2004
- 2004-01-26 WO PCT/US2004/002216 patent/WO2004070781A2/en active Application Filing
- 2004-01-26 DE DE602004031925T patent/DE602004031925D1/de not_active Expired - Lifetime
- 2004-01-26 EP EP04705329A patent/EP1590835B1/de not_active Expired - Lifetime
- 2004-01-26 AT AT04705329T patent/ATE503329T1/de not_active IP Right Cessation
-
2006
- 2006-06-21 US US11/472,984 patent/US20060239392A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
WO2004070781A3 (en) | 2005-06-09 |
EP1590835A2 (de) | 2005-11-02 |
EP1590835B1 (de) | 2011-03-23 |
WO2004070781A2 (en) | 2004-08-19 |
US20060239392A1 (en) | 2006-10-26 |
ATE503329T1 (de) | 2011-04-15 |
US20040151209A1 (en) | 2004-08-05 |
US7239669B2 (en) | 2007-07-03 |
EP1590835A4 (de) | 2008-10-08 |
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