DE4335690A1 - Architecture of and method for configuring a parallel computer - Google Patents

Description

The invention relates to an architecture for and a method for configuring a parallel computer.

The present patent application describes one Parallel computer architecture and a method of construction and to reconfigure one of the problems before parallel computer dedicated to specific problem areas for the calculation of the problems of this problem area, taking these problems from a variety of coupled discretisable processes exist within the Problem area can be different. The particular their computer architecture allows the end user to Help a new procedure, repeated yourself individual discrete processes in a small digital Circuit and then the entire calculation to configure with these linked processes, with an effort similar to that at Compilation. Because the problem is then directly parallel "in Hardware "is calculated without the intermediate stages of a  Instruction set, problems can be up to a million times faster than the fastest available today Workstations are calculated. For configuration Commercially available chips use whatever the end consumer allows one to be tailored to his problems to determine the most powerful parallel computer.

A novel computer architecture and a prototype of a hardware-programmable parallel (genetics) processor for the investigation of interactive molecular evolution are proposed, which is designed in such a way that it enables the simulation of an interactive molecular genetic processing. The genetics processor reaches the 10 ⁹ generation limit over a period of several computer hours with a population of 10 ⁴ interacting sequences of variable length with an average length of 64 bits. The computer is hardware programmable, using an arrangement of field programmable gate array chips (FPGA) and the associated special properties of the distributed memory. In particular, the building blocks of the 4000 family can be used from XILINX. The shift in simulations from higher computer languages to the hardware level of the computer is advantageous due to the conceptual and practical advantages.

Problem

Many fine-grained parallelizable problems of today science, medicine and business can be achieved with the existing capacity of the current computers not overwhelm be done. A typical example is the combinato rischer optimization, as z. B. in the field of evolutionary biotechnology desired for proteins  becomes. A second example is simulating a lot body systems, such as the investigation of congestion stop in the transport system. The conventional serial von Neumann machine, as used in many modern computations The way in which RISC workstations are implemented is unimportant capable of sequentially using a univer set of commands to emulate such problems. This emulation is limited by the CPU performance of the Processor, in turn, from the finite packaging density (e.g. 1µ mask spacing) on silicon chips is bordered. It is also inefficient because of the univer command set from these machines is not optimal any application problem can be customized.

The difficulty in using parallel rake lies in adapting the architecture and the Basic commands of the specific problem to that of the Calculator: different problems require different ones Parallel computer. In addition, even the Kopp development of several von Neumann machines in the area of Synchronization and data management problems with it brings that both in the manufacture of computers as are also remarkable when programming. Here will described a process that allows to represent a "dedicated" parallel computer for to build each of these problem areas. What is offered here is a new way of making computers, a new computer architecture and a new process for computer programming. The patented tasks position consists of the following:

• 1. To design a family of parallel computers from End users in hardware to their own problem circle can be adjusted.  
• 2. A method for producing such an fit computer without time-consuming chip design, d. H. with chips that are already commercially available, and without difficult synchronization tasks.
• 3. A method of reconfiguring such Calculator. Programming the calculator for a specific problem is said to be directly at the level of Configuring the hardware and not by means of machine language in software.

State of the art 1. Available parallel computer architectures

The following discussion is based on fine-grained parallel computer limited, because only with these enough processes sensors for large performance gains compared to the serial computers are available. So do not apply a whole host of computers like transputer networks, the Intel Hypercube, Kendall Square (Virtual Shared Memory) calculator etc. While such calculator, with up to 1000 processors, time savings up to about a factor Can achieve 100, they do not get beyond that. Development times and costs are extremely high. It remains ben three fine-grained architectures of computers, which on are most comparable to the subject of the invention.

• a) Connection Machines (Thinking Machines Inc.)
  Originally developed as SIMD (Single Instruction Multiple Data) machines, the connection machines allow synchronous processing of up to 65,000 data carriers. A MIMD (Multiple Instruction Multiple Data) connection machine has also recently come onto the market. In both cases and in contrast to the architecture to be patented here, the architecture is based on a classic set of instructions. Although the connection machines are particularly well suited for some fine-grained arithmetic calculations, their architecture cannot be influenced by the user.
• b) Cellular Automata
  A cellular automaton is a collection of identical automatons, each with a finite number of states, which are regularly linked to their neighbors on a grid. A relatively general two-dimensional cellular automaton that can be programmed directly in the hardware could also be built here using the design process. The direct neighborhood is generalized in the new architecture through connecting channels with slipping possibilities. This, and with the help of locally distributed RAM, enables the processing of character strings. This is described in more detail in the basic document.
• c) Furthermore, configurable cell arrangements are be knows how z. B. described in W090 / 11648. Each Cell arrangement is housed on a chip and several such chips are in regular (Matrix) form arranged and connected to each other the. Even the cell layout within the one individual chips are matrix-shaped. Such an arrangement configurable chips are used to e.g. B. solve user-related problems. Each Cell, any group of cells or any chip serves to solve different parts problems of the task to be calculated.

2. Method of manufacturing the parallel computer

Chip design is still associated with considerable effort. A production test modification cycle lasts in the Usually several months. Programmable blocks shorten zen this cycle, but are due to their low packaging density and the still rigid archi architecture of the computer not yet for the entire processor construction has been used. In the patentable here The process, on the other hand, becomes the chip design problem for Parallel computer modularly solved. One over the chip Beyond limits, modular architecture accelerates the Design process and is so flexible that programmers within a few minutes implement custom design for the problem can. Programmable blocks that define a modular design principle and the generation of problem specific chip designs using a conventional len programming language enable the new way.

3. Reconfiguration procedure

A method for reconfiguring FPGAs is e.g. B. offered by XILINX. With a block switch image editor, changes in design locally and internally actively made. Automatic partition, place and Route (PPR) programs determine the embedding of the logic on the FPGA. However, this procedure has two consequences parts to avoid. For parallel computers, where the block diagram is a repeating structure repetitive editing is required operations the power of a programming language to make efficient parallel changes.  

Current research in the field of genetically based functional self-organization requires a considerable amount of data processing in order to simulate populations of interacting chain-encoded (string-encoded) automatons. While the independent molecular selection is well understood as a logical skeleton and this has made it possible, in particular, to develop evolutionary optimization algorithms, the consequences and possibilities that result from interacting functionality for higher organizations have so far largely been unexplored. Numerous attempts have been made, using simple duplication, to understand the essential logic of functional interaction using populations of molecular automata. Both practical and conceptual reasons for a deviation from the software training conventional in this field and for a transition to configurations implemented in the hardware with user-programmable linking fields (field programmable gate arrays = FPGA) should be pointed out here. This requires a rethink in design conception and methodology, but also harbors the prospect of improvements in speed by 10 ⁶ times in populations of up to 10,000 chains, so that part of the flexibility of software training is retained and conceptual simplifications in design are made possible. A simple prototype design will be described below to illustrate the usefulness of this approach and the nature of the conceptual changes it motivates.

The simplest evolutionary models dealt with homogeneous, well mixed populations of constant Size as chemically in a flow mixing reactor  (continuous stirred flow reactor = CSTR) are. The selection is the result of the proportional len dilution to balance the molecular product tion surplus reached. In another theory tical model was attempted, the one needed for evolution elements to the local physical essentials liche and reduce the functional effects of to bring molecular interaction. There was one successive relativization of the role of chance as that Source of diversity on which the selection in the Evo lution, as well as a reassessment of the Be interpretation of spatial effects in evolution. Both developments mentioned are required before a Step towards FPGA technology can be credible.

In a non-interacting Darwinian Evolu there are two occasions when usually chance plays a role: the muta tion at selected locations in the molecular sequences zen and in the selection of molecules in the Popu lation should continue to exist. When interacting There is also a random selection of models successive interaction partner (a bimole kular process that is generally sufficient to bio describe chemical reactions). In the latter case it has proven to be possible with chain-coded Functionality, implicit variations through the below different processes of bimolecular interaction achieve. A dynamic mixing process in an open Vessel is the physical basis for the selection of Molecules and their interactions are sufficient. In the Physics is well known today that simple deter minimalistic non-linear systems chaotic dynamics can produce, and it would in particular be a hard spherical model sufficient to be a local and selective  To represent randomization of attached chains. It would therefore be a purely local deterministic dyna mix rule to describe the evolutionary pre gangs are enough. This would also have the consequence that space heterogeneous phenomena could be created. Did for a wide group of homogeneous, developing, replicating populations states that all cooperative functional inter actions towards more parasitic yields than have highlighted unstable, and the issue of space heterogeneity is therefore for any model investigation critical.

The previous model creation work has become one Large number of small automata interacting in groups in computer languages such as C. The one with the other related requirements regarding appropriate popula tion sizes (<1000) and generation numbers (<1000) for Clarify generic behavior Simulations in conventional computer equipment time complex. Usually the simulation of 1000 chains for 1000 generations with one RISC Workstation several hours of computing time. It exists here a low efficiency in the use of Computer resources. As discussed earlier, seems that floating point operations to simulate Evolu tion are not absolutely necessary. Second are the processors for segmented operations, the byte or include word limits, optimized, not ever but for chains of variable length. Third exist software and financial barriers for effective use of parallel machines. Fourth are the higher programming languages for both serial as well as for parallel machines limits that they have a wider range of interaction  Allow schemes as for genetic processing may be relevant.

The invention has for its object a Vorrich device for calculating fine-grained parallelisable Create problems and a procedure for configuration ren specify such a device in which the User the device within a short ent Configure the development time for the problem to be solved can and calculating the problem with such configured device extremely low computing time needed.

To solve this problem with the invention 2. Device with the features of claims 1 and 2 respectively and a process with the process steps of Claim 3 proposed. The characteristics more advantageous Refinements result from the subclaims. Preferred uses are the subject of the uses claims.

The invention makes sense of the knowledge Ge need a hardware part or so preconfigure that the user quickly and a fold the calculator for a particular problem of a person Configure the number of problems (problem area) optimally can. The computer is therefore designed in terms of hardware to all problems of a given problem area to be able to solve. For those with the computer or the front Direction to solve problems is that they are fine-grained and are parallelizable as well as a variety of interlinked discretisable processes are writable.  

The individual logic is preferably involved circuits around so-called user-specific logic Fields (Field-Programmable-Gate-Arrays - FPGA) that are made up individual logic cells arranged in array form stand. These logic cells are freely programmable, with which the entire array is freely configurable. Multiple logic cells become single logic scarves blocks, the so-called configurable logic blocks or CLB (Configurable Logic Block), together composed.

Furthermore, the synchronous clocking is according to the invention all inputs all logic cells all Logic circuit blocks provided. So that at large processor networks sometimes occurring timing Problem solved. The FPGA have an internal connection structures that allow it to be clock signal applied to the FPGA at the same time on all logic cells.

Another feature of the invention is that the connection pattern between neighboring CLB one Logic circuit (of an FPGA) regularly and with each other that are the same. If several FPGAs are used, so the neighboring CLB connecting connection is set pattern beyond the limits of the FPGA. That is, CLB neighboring FPGA are connected in the same way as the CLB one and the same FPGA.

The invention is based, among other things, on the knowledge that distributed decorrelation in user configured ble logic circuits (namely the FPGA's) for the Large-scale simulation of processes to use the random require elements. Distributed decorrelation means that Use of uncorrelated bits of functionally ge  but separated adjacent digital circuits a chip for generating quasi-random signals any place to simulate stochastic processes lieren. Since these signals are reconfigurable, their selection for the purpose of eliminating statistical requirements (statistical bias) can be optimized.

Furthermore, RAM memories distributed according to the invention with parallel addressing as a shift register between processors used to do the simulation to enable larger collections of objects. The Use of shorter RAM's with heterogeneous addressing allows local insertions and deletions at the String processing. The use of tightly coupled synchronous input-output data streams enables one "once-off design principle" for all application-specific fishing uses of storage. The Memory can be distributed on the FPGA's itself and / or on dedicated memory chips between the FPGA's be distributed.

Finally, connecting all data and Control bits in shift registers for the (bus-wide) serial len non-destructive reading of the current Calculation or simulation possible. Of the Data flow can be done in a simple regular way Practice process with defold pre-setting of the processors be reduced for reading. The state of the process sensors themselves, which only requires a few bits can be recorded in local registers, and before reading out, for later storage or integrations in flip-flop chains for reading and restoring are available. This powerful properties of the readout  through the design rules of synchronous input-off aisle channels possible.

Finally, the invention can also be local Rerouting in the design process for modular Designs to drastically increase the design implemen tion cycles with the same duration of a convention software (editing, compiling, connecting, Running).

With the invention, the interaction bottleneck is ver avoided by having a new hardware design with it continuously fast moving data and purely local interaction is used. Illustra tion a two-dimensional space as well as binary chains used where the genetic sequences are based on naturally both an almost random local mixing, as well as an almost deterministic inter encode active copying functionality without to introduce stochastic processes. Basically colli molecular chains are attached to an array of binary Switching points, the passage of which corresponds to the currently control nearest chain neighbors.

The device according to the invention and the method according to the invention described in more detail.

1. Computer architecture

There is no instruction set. Instead is the calculator in a variety of small processors divided due to the use of in hardware programmable blocks themselves completely reconfigured can be generated. Each such processor is over one limited, but otherwise freely selectable number of bit  wide lines connected to neighboring processors the. The neighborhood is initially one of two dimensional grid. Depending on the application other geometries are also problematic see. Each such processor processes the synchronously Bit streams on its input lines and generates un interrupted synchronous bit streams on its output cables. With each processor, every on is internal gangsbitstrom before further processing in special local shift registers cached that too allow "random access" access. The process tion can range from a relatively long distance depend on incoming bit streams.

The connection structure of input and output lines between processors is also not of fixed in advance, but only one upper superset of those required for the problem area Links. The connection structure between processes sensors within a chip is continued between Processors located on related pages below different chips. For the connection of Processors that are not on the same chip that must not be reconfigurable lines ge be placed. The existing fixed lines would have to all connections to be realized in the problem area Allow patterns between processors. This is possible by programmable modules, as long as one Superset of required connections hard-wired is.

A fraction of the total inputs and outputs becomes additionally on a (e.g. 32 or 64 bit wide) data bus of a serial or only coarse-grained parallel Host computer led. The clock frequency of the DMA (Direct  Memory access) read / write cycle of this host computer determines the frequency of the synchronously clocked parallel calculator. A clock frequency around 25MHz is with the current one Technology quite achievable. A coupling with Graphics processors are for direct visualization too possible.

In the field programmable gate used for the prototype Arrays (FPGAs) must be used to manufacture the architecture Allow initial state of distributed storage. Here is a default circuit for the processors a separate reset switch that activates the Processors converted into simple shift registers. Of the The current state of the calculator can be viewed in the same way to be read. The states of all internal flip-flops (Register) can both at the start of a calculation be determined as well as read in between the.

To demon the suitability of this new architecture is the exact specification in the base document of a one-chip prototype computer that is used for the Evolu area was built, specified. Plans for one Expansion of this calculator by a hundred chips are also possible present in the basic document. Different modular on divisions of a chip into modules of 2 to 12 configurations tion units are also recorded there in order to to show the general validity of the architecture.

2. Operation to build a predetermined problem circle dedicated to this or its hard would be adapted parallel computer

• a) For a problem example, identify the Data streams that the individual processes (processes)  couple. These then form a certain number of bit-wide inputs and outputs. One understands different problem examples for a problem area together and examined whether it was for this problem circle an upper limit or superset of Solving the problems required processes exist. If not, you either have to end the process or after simpler processes in the problems or look for smaller problem areas.
• b) Determine the geometry of the coupling between the individual processes, are typical examples one-, two- or three-dimensional grid or the Hypercube. If there is no geometry, all of them through those specific problem geometries Deletion of connections as sub-geometries hold, then this procedure can be a single Parallel computer for the problem area not deliver.
• c) Design using a block diagram editor one circuit that does the local processes for a certain simpler problem example describes. Let this design (with Using an automatic "Place and Route" pro converts) into an FPGA sub-configuration animals and pack the design in the smallest possible way compact compact form from the figure N des Basic document.
• d) Choose one of the optimal packaging for this Processors. Depending on the processor and Chip sizes are between 16 and 1024 processors possible per chip. Count the inputs and outputs, between the different chips necessary  are about this processor connection structure to implement beyond the chip limit.
• e) Lay conductors on "Printed Circuit Boards" to the superset of those determined in point 2d) Connections for the different problems of the Realize problem area. In addition some clock and control signals to configure who uses chips.
• f) A DMA access is on a data bus of the Host computer connected. The selected On gears should load the chip (see above) and the selected outputs for reading the ver shared memory.
• g) Write interface software to change problems on commands from the FPGA design editor the. For example, here are macros, the equiva lent changes on all processors call, especially useful. The chip limits can also be made transparent so that the Connection structure easy to change in software is.

Explanation of the procedure

FPGAs (field programmable gate arrays) form the building stones of this new design process. This in itself known chips are repeatedly configurable and be stand u. a. from a square grid combinato logic blocks (the multiple gates and memories elements included) and a connecting network of pro programmable lines (interconnect level with pro programmable switch matrices). The presented here  Design concept makes use of a regular one Grid of approximately 100 of these chips. However, the task a working design for just one such chip design usually involves a. complex Timing issues. Even that Equivalent to an efficient automatic compiler for serial problems is not yet conceivable. Farther calls for the problem of communication between processes that run on the different chips every time a separate and difficult treatment.

The two problems of design and communication will be solved according to the invention by the Ver presented here drive. The solution is based on small design ends Circuits made easy through hardware programming design and are as small as that smallest process units of the problems to be solved Problem area. Many such units become symme packed in every chip. Communication takes place about repeating a local pattern from Verbin lines between these units. Architecture the fixed interchip wiring reflects a superset this local structure reflected to various problems allow within the same circle. The whole one units are synchronized and formed in such a way that she constantly all inputs from her neighbors in a loka len can store. That way eliminates the otherwise difficult communication problems.

The solution offered here is very close the ideal solution to address any problem directly to silicon that would be offered if multi- Chip design would be easy. A prototype of one Calculator is for evolution simulations from the inventor already been built.  

3. Reconfiguration procedure

The reconfiguration of parallel computers with the im The architecture mentioned in point 1 is in accordance with the invention comparable to a classic programming task.

• a) Edit
  With the help of a higher computer language such. B. the C language, the systematic naming of network names (the corresponding term for variables in conventional programming) is made. Systematic changes, either in the modules themselves or in their connection structure, can then be carried out efficiently using program-generated design modification commands, which can be summarized in macro files.
• b) Compile
  This command file and the original design file can then be accessed by an optimization routing program (from the FPGA manufacturer) in order to generate a new design file for each of the FPGAs. The user only needs to specify the local changes in the connection structure or logic of a module to create a new overall design. Loadable binary files are automatically generated from the design files for the FPGAs using software from FPGA manufacturers.
• c) loading
  These binary files are sent in parallel or in series to the parallel computer via the bus structure described in point 3.a) above.
• d) reading
  The results can either be read directly from the distributed memory (using a readback pulse initiated by the FPGA manufacturer) or dynamically via data lines that scan the computer structure at crucial points.

The invention is described below with reference to the figures hand of an embodiment of a genetic processor explained in more detail.

Brief description of the figures

Fig. 1 Programmable connection devices.

The illustration shows a corner of a XILINX 4000 LCA Chip (Logic Cell Array) and the available program connectable connections between the CLB (Configurable Logic block) and the 10 blocks (input / output blocks), Decoders and buffers. The high density of the possible Connections in the switching matrices that are a rule forming a moderate grid between the CLB is special striking, but the numerous points also show programmable connection points (Programmable Inter connection points - PIP).

Fig. 2 CLB configuration as logic or memory.

This is a reproduction from the XILINX series XC-4000 data book. The configuration Logic blocks of the XILINX Series 4000 have 2 programming bare function generators for implementing a arbitrary Boolean function with 4 variables. This is implemented using a table lookup scheme not only in the configuration, but also  is also programmable during operation, so that the function generators are also used as RAM memory are cash. The CLB are also part of the configuration tion programmable multiplexers provided ver different connections between the direct and the outputs (by flip-flops) and the radio enable generators. A third function generator gives the CLB further combinatorial features Potential or further potential as combined RAM. The details of the fast transfer logic that the efficient use of the CLB as construction blocks allow for counters and adders or the like are not shown.

Fig. 3 unit structure and IO for the genetics process sor.

This representation relates to the local connection structure for 4 _* 4 units of the genetics processor (164 CLB are shown). The spatial isotropy is preserved by combining 4 rotated units (x1, x2, x3, x4) to form a higher-level repeat unit, which is shown in the dotted right corners. This design fits well in the LCA chip 4003 from XILINX, while the LCA chip 4010 can accommodate 100 = 5 _* 5 _* 4 units (400 CLB). The diagonal connections show the prototype interaction scheme for the shift control.

Fig. 4 Design of the prototype genetics processor unit.

The figure shows a design of a 4-CLB prototype unit with 4 inputs and 2 outputs. The design uses a 2-chain memory (FIFO) with genetic control Information transfer from i1, i2 to o1, o2  via the switch SW1. The switch has four positions on and there is an internal and external tax when switching. An addressing will through 4 such blocks from a single global cyclic address cycle 0000100110101111, where a flip-flop in the controller (CTL) of each block is applied.

Fig. 5A, 5B, 5C and 5D CLB designs for Genetics processor unit.

The CLB unit according to FIG. 4 consists of the blocks KAM, MEM, CTL and SWI. The first two CLBs, namely RAM and MEM ( FIGS. 5A and 5B), serve as two shift registers and the third CLB, namely CTL ( FIG. 5C), controls the function of the fourth CLB, namely SWI ( FIG. 5D), which is a genetic switch for the two bit streams.

Fig. 6 LCA line routing for the genetics processor prototype.

The illustration shows the "wiring" of the LCA prototype design at the time of registration. This wiring is to be compared with FIG. 3. The 4 CLBs shown in FIG. 5, which form the basic functional unit, are arranged as in FIG. 4. This connection scheme is carried out automatically by the XILINX optimization guide according to a semi-automatic procedure for CLB introduction and network naming using the basic 4-CLB macro. The two middle rows and columns of the CLB become less important in this demonstration design to generate the global 1-bit address sequence, the bitstreams with which the units are initially loaded, the logic to disconnect from this load source, and some others Display connection tasks that are not required for a final design are used.

Fig. 7 genetics processor on a XILINX demonstration plate.

The illustration shows the pin connections and their Significance in the event that the 4003 LCA chip with the Genetics processor unit prototype design loaded is. Control dip switches on the demonstration panel the disconnect and switch reset hold process while LED and segmented displays to indicate the binary different representative signals used the two conflicting bit streams and the Zu the genetic switch was at a point on the LCA lock in.

Fig. 8 interface to the host memory as a flow reactor tor.

The figure shows a schematically represented inter face that is achieved by limiting bitstream ver connections to a host bus can be opened. Further Details can be found in the description below. It is also the charge bit current paths through the grid represented from 4005 chips.

Fig. 9 one size and pack at 14 _* 14 CLB LCA (4005).

The unit samples assume that each LCA has an identical format. The (2 _* 2) repetition is therefore necessary to enable alternating I / O directions, which ensures isotropy. For the most complex designs (3 and 5), 4 variants of the basic unit have to be routed.

3: 4 _* 4 _* (2 _* 2) _* 3 = 64 3-CLB units
4: 3 _* 3 _* (2 _* 2) _* 4 = 36 4-CLB units
5: 3 _* 3 _* (2 _* 2) _* 5 = 36 5-CLB units
9: 2 _* 2 _* (2 _* 2) _* 9 = 16 9-CLB units
12: 2 _* 2 _* (2 _* 2) _* 12 = 16 12-CLB units.

Fig. 10 Local address generation with insertion and deletion.

This two-CLB configuration creates a local address se for separate write positioning and is fer ner able to address this in a single bar cycle to delay two or move forward, thereby inserting and deleting in the outgoing bit electricity are possible.

The following description is divided as follows: Section 1 describes the nature of a family represented by currently available FPGA the company's 4000 series of logic cell arrays (LCA) XILINX. In section 2 the prototype used Design described. Section 3 describes the development a sufficiently flexible parallel programming environment for model creation with a fixed number of LCA discussed. Section 4 contains a generic gene tical processor using this methodology poses. Finally, in section 5 the type of Simulation experiments with this type of computer are feasible, as well as the possibility of restructuring rierens discussed a compromise between Popula tion size and computer speed.  

1. The XILINX LCA 4000 series

The logic cell arrangements from XILINX are user-programmable logic fields based on CMOS VLSI technology. The term "programmable" refers to the fact that the lowest order circuit is constructed in a multipotent manner that can be further specified by configuring numerous internal memory cells (e.g. 178096 in the largest currently available LCA, the XC-4010) . These specify a large number of logical elements and their connections: primarily the arrangements of the configurable logic blocks (CLB) and the switching matrixes. In addition, input-output blocks (IOB) and wide detectors enable programmable communication with the external pins of the chip, and programmable connection points (PIP) and tri-state buffers (TBUF) specify the type of connection between the elements mentioned, whereby a variety of additional local and global connection lines (single length lines, double length lines, horizontal and vertical long lines and global lines) is used. In the corners of the chip there are a number of additional special structures, some of which can be used in particular to control the serial programming, the start and the repeat function of the chip. The resources available in part of the LCA are shown in FIG. 1. A serial configuration program (which, as set out in Section 4, is generated by a process related to compiling) can be loaded from a conventional PROM (programmable read-only memory) chip or from a disk via a standard PC or a workstation.

The CLB can be programmed either as logic elements or as KAM (Random Access Memory) or a combination of both, as shown in FIG. 2. As a logical element, the CLB contains two independent function generators (F and G) with 4 inputs and a third function generator (H) with three inputs, the outputs of F and G and a ninth external input. These three function generators are programmable in such a way that any Boolean function of their inputs can be implemented. Each of these three outputs or a tenth input can be connected to the two direct outputs of the CLB or can be routed through one of the two flip-flops (single bit storage) in the CLB, which act as additional external inputs of the CLB with clock, set / reset and enable Controls can be connected. In addition, the CLB is provided with programmable high-speed logic that enables the use of high-speed counters and the like across multiple CLBs. The H function generator can be used as a memory element to control the use of F and G either as separate 16-bit memories (where the 4 inputs act as address lines) or as a combined 32-bit KAM. (As two separate memories, however, the write access for both is controlled by a single write enable signal.) The bits read out can, as explained above, be output both directly and by the flip-flops. This feature is a significant advance in the 4000 series as it enables the potential of programmable dense parallel data processing using distributed memory. The repeat function provides a serial bit sequence with the current states of all flip-flops, including those not mentioned in the IOB. The content is copied when the repeat function is initiated so that normal LCA processing can run in parallel with the repeat function. However, the contents of the CLB designed as KAM are not copied, so that the user must pull down the write release for all KAM whose values are required for the repeat function.

The routing of the user connections, the Ver use of the switching matrix and the specified connection equipment is largely car matically with an optimization code that simulates a Healing involves, but the distribution must be tuned high fan-out signals, including the Clock signals and the aforementioned write enable, limited to the use of global lines the larger one associated with excessive stress To avoid time delays. This routing can also act as a compiler-like function be seen. It should be noted that one LCA chip by the user using a serial bit sequence is reprogrammable to numerous different to implement their logic circuits. The bit sequence is the result of compiling a design File, which in turn is the result of routing the from specifications entered to the user Logic and connections is. There are no additional ones Hardware modifications required, prev the design makes no new demands external facilities such as wire connections to the IO pins of the chip. More details fin in the XILINX part specification information.

2. Design prototype for genetics data processing

Genetic molecular sequences are modeled as binary chains of variable length. First, it should be noted that the sub-sequence 00 is used as a separator to mark the gaps between the chains. The chains are embedded in shift registers, which are embedded in a regular grid throughout the LCA and connected in pairs at a junction arrangement called genetic switches. The data flow of the chains through the shift registers and the switches is constant the clock speed (which is up to 3 _* 10 ⁷ bits / sec). The switches simply control the way in which bits coming from two converging shift registers are distributed to those at the diverging shift registers. The pattern of the data flow in the predetermined switch state is shown in FIG. 3. This is chosen to initially load the shift registers and to maintain spatial symmetry during free switching. In the simple prototype version, either one or both of the incoming bit streams reach the two outgoing streams (copy or swap), and the switch also controls which of the two input streams reaches the outputs. Thus, the switch has 4 states that are controlled by two flip-flops. Changes in the state of the switch only occur when the switch flip-flop timing is enabled. In the prototype design, the release is active when both input streams have a gap between the chains (00 sub-sequence), and the new switch state is then determined by two bits of a third neighboring bit stream (the data input of the flip-flops). If there is a 3 bit match between the current bits in an input stream and those of the third neighbor, the switch is also enabled. The latter enables switching within chains and thus a wide range of recombinant and mutative events, including sharing and joining. It should be noted that in the prototype design, inserting or deleting individual steps in or out of the inside of the chains is not permitted. The part before this design is that it creates a uniform simple framework for mixing, amplifying and local selection.

A quadratic local unit of 4 CLB is sufficient to implement two 34-bit intermediate switch chain segments, the genetic switch and its control. The block design of this unit is shown in Fig. 4. Two CLBs (KAM and MEM) shown in FIGS . 5A and 5B implement two adjacent 2 _* 17-bit shift registers which use the F and G function generators as memory and the flip-flops to store the 17th bit. The 16-bit memory is addressed in a cycle with 16 clock steps, with one bit being read and written per clock step. A 4-bit counter would normally be used for this purpose, however a cycle with 16 different 4-bit addresses can also be achieved by consecutively overlapping 4-bit sub-sequences of a single bit stream and this reduces the number of address signals that are global to be distributed by the chip, from 4 to 1. The sequence used was 0000100110101111 and was distributed via a first global buffer from the corner of the chip to each group of 4 local units, with a flip-flop from each of the 4 units to restore the was used against the current 4-bit address. Once this principle is understood, similar addressing variants can be easily developed. The only difference between the 4 local units, which form the actual LCA repetition unit (with 8 chains and 4 switches) shown in FIG. 3, lies in the orientation of the inputs and the outputs.

The switching CLB (SWI) is shown in Fig. 5D. The two flip-flops have a reset line, which are used to hold the switch in its default position during initialization, and a write enable, which, in addition to the data inputs coming from the third neighboring bit streams referred to above, from the control CLB ( CTL) come here. One of the streams must go through the H function generator to reach its flip-flop. The flip-flops specify the 4 possible states of the switch:
1. SWAP1: 00 i1-o1 and i2-o2
2. SWAP2: 01 i1-o2 and i2-o1
3. COPY1: 10 i1-o1 and i1-o2
4. COPY2: 11 i2-o1 and i2-o2.

The rest of the CLB (the F and H generators) become the Implement the switch used, each Function generator specified an output. The four Inputs of the function generators are in both cases same: the two input bit streams and the two Switch status outputs of the flip-flops.

Finally, the control CLB (CTL) of FIG. 5C uses a function generator to examine for a double gap in the two incoming bit streams (00 and 01) and the others to examine for a two-bit match between the first incoming stream and the neighboring third stream. A flip-flop is used to record the previous state of this latter match and then, together with the outputs of F and G, is fed back for final decision in the logic of H (2 to consecutive matches (ie, a 3-bit match) between the first and the third bit stream or a double gap in streams 1 and 2) so that the write enable signal can enable a change in the switch state. The remaining flip-flop is used for the aforementioned address decoding.

The prototype design was implemented on the smallest chip (4003) of the 4000 series, for which a demonstration board from XILINX was available. This has a 10 _* 10 arrangement of CLB and enables the use of 64 CLB for 16 to 4 groups connected local units (32 34-bit chains and 16 switches), with 2 CLB-wide vertical and horizontal strips in the Center for testing and easy on-chip generation of the global controls remained free (an off-chip solution is suggested for larger designs). The routing of the LCA is shown in Fig. 6. Only a small subset of the 84 pins is required to complete a toroidal geometry of bitstreams for testing the single chip. The details of the connections and control switches used in this demonstration design are shown in FIG. 8.

The final design will require 100 of the large chips (20 _* 20) wired on a printed circuit board (PCB) to reach a population of 10,000 chains with an average length of 64 bits.

The limited population size of this genetics processor can be partially remedied by opening the closed processor bit streams to the main KAM memory of the host computer with a variable bit width. Up to 32 bits (depending on the host bus) can be input and output in parallel in the LCA arrangement in two host bus cycles. A large population of 1 million 64-bit chains (8MB) or more can then be processed by clocking the memory address linearly through the host memory, replacing the bits entered into the LCA with the bits it outputs will. Depending on the residence time of the genetic chains in the LCA, numerous effective population sizes can be achieved by varying the bit width of the interface. A schematic representation of this host interface is shown in Fig. 8.

3. Programming environment for hardware simulation

Usually lie between the design of a scarf device and its implementation order of months. The optimized circuit must be one Chip manufacturing company will be handed over to them by means of a sequence of photolithographic and chemical Steps with a resolution of 1 micron on applies the desired silicon wafer. The cost of one such development cycle are high and only through to cover large quantities of identical chips. This represents the development obstacle for customized Chips. The FPGA has a certain regular and dense design the development cycle mentioned go through and its circuit has memory cells (Flip-flops) whose binary states are via Transisto open and close a large number of Ver bonds between design components (the PIP) and  also enable combinatorial functions, which a group of signals and an output line ver bind (e.g., the F, G and H functions of the series 4000 from XILINX). It follows that the spec cation of the states of these memory cells the same Has effect like running a very large class of circuit designs in hardware, with a ring the achievable gate density by about a factor 10. The circuit design of a 4000 series chip is controlled by several 10,000 memory cells.

Of course, not all connections can do this be specified. The FPGA exhibit a regular Arrangement of dense local connections and a limited number of fast connection lines greater range. It got special attention on the impact of programmable connections on the propagation time and the voltage level of the Binary and tri-state signals set, however read these problems at this level do not differ from that Disconnect users. On the other hand, it's very easy Generate programs in higher computer languages that also don't work. It is therefore an intel intelligent design input interface and an intelligent one Compilers required the bugs in a design limit and test the usefulness of a design. Since that Product competes with conventional chip designs, great value was placed on a design entrance with conven CAE block design process. The block However, design is completely general and needs to be done later the programming restrictions of the LCA are adjusted. The experienced user may have restrictions in this Specify the process, but the packing density depends and the speed (the maximum achievable tact rate) of the design often from a global perspective  from the currently available automatic imple mentoring programs, e.g. B. the one offered by XILINX Escape PPR (Partion place and route).

In line with the concept of FPGA as a rule moderate logic orders were limited to Designs that be a regular repeat unit content. This is due to the symmetry of the chip Problem of optimization on the cell unit this like limited design structure. A hierarchy nested designs that have different smaller ones units to a larger repetition unit combi nated, can also be considered. The XILINX software does not yet support user-defined "hard" macros that apply completely optimized and specific subdesigns enable a chip, however, this is considered imminent provided. With regular orders from Sub designs is a systematic name for networks (Signal lines) required in the subdesign to Dupli cations of labels in internal signals avoid and a systematic programmed connection of sub-design inputs and outputs.

Programs written in C have been developed to the systematic set of network connection commands create the ones you want to implement regular topology, like that of prototype design, required are. There was also a ge in C written program designed to the required Sequence of "soft" macro instructions to generate the required to arrange the subdesigns on the LCA are. Because the XILINX LCA Design Editor (XACT) opened the door Calling command files allows the step from the small sub-designs to regular arrangements  such subdesigns are automated, if such in C programmed command files can be used. A special connection scheme (geometry) can then in the conventional simulation language specified and are automatically transferred to the chip. The problem a further automatic optimization and one such tests of the subdesigns are neglected here, however, it should be said that a maximum of 16-25 CLB as the primitive unit for this class of computers is seen. XILINX delivers very sophisticated Vali dation controls when introducing designs, if desired, with incremental cable routing as well as a Design Rules Checker - DRC), which finds further errors. There is one automatic routine which the maximum delay conditions for signal propagation between flip-flops gives, whereby a determination of the maximum clock speed and further design optimizations possible are. A timing simulation of the design can if desired, also executed in software the, the manufacturing-related delay spec in addition to calculating the signal spread behavior can be used.

The spread of repeating units across the Chip boundaries require the introduction of the geome distribution of the pins in the C program, which the logical connections between the subdesigns the periphery to the IO pins of the chip. This is a "once-off" task for every member of the 4000 family. The physical connections between the chips must be made by a PCB, d. i.e., through hard wiring; however, since the internal connections the subdesign IO and the IO pins of the device pro a large number of parallel ones is sufficient  Connections between corresponding IO pins to the general nature of the repetition of the designs of Maintain units across multiple chips. Because only neighboring chips are interconnected and one minimal fanning out should be delayed be short enough to match the clock speed of the Not restricting computers. It became a C code written to be arranged around a predetermined one Subdesign IO line to find next connection pin and the corresponding XACT connection commands produce.

4. A general genetic switch

Much of the general design strategy has been outlined in the previous sections. In this section, the general character of the approach is to be clarified by presenting the design of a genetic switching unit with separate write addressing (a write head), which is dependent on local bit sequence characteristics (one of the two bit streams running through the unit or an adjacent stream) ) can be moved step by step in relation to the reading address. An arrangement of such elements that are similar to Turing machines permits general editing of the embedded genetic sequences, including insertion and deletion within them. Fig. 9 shows how units of 3, 4, 5, 9 and 12 CLB can be embedded evenly in the 14 _* 14 4005 LCA. Other unit sizes are possible with the 4005 LCA if the restriction on an even number of units per side is relaxed (however, in the final arrangement this would require alternating variants of the design for neighboring LCA to ensure spatial isotropy). In this section, a unit with 9 CLB is presented.

Large parts of the prototype structure that relate to the 4 CLBs mentioned (KAM, MEM, CTL and SWI) are retained, and the new structure is introduced as an extension. The write address must be stored locally (whereby 4 flip-flops and 1 function generator in 2 CLB are sufficient) to generate the 4-bit address selected here. The normal rotating bit sequence of addresses shown above is used. The address at the next clock time can be incremented or decremented from the expected next address by changing the number of clock pulses on the flip-flops from 1 to 2 or 0. The simplest way to advance the address one step beyond the next address is to use a double frequency clock to generate two cycles in this part of the circuit. The enable signal on the flip-flops can be kept at a low level to prevent updating and thus to effect a relative decrementing of the address from the expected next value. However, it is possible to pack this additional function into the two CLBs that are used to generate the local address without using a double frequency clock (which could lead to a limitation of the maximum operating frequency). This is shown in FIG. 10. Address bits 0 and 2 are packed in one CLB and bits 1 and 3 in the other. The schematic representation shows the density with which very complex functionality can be expressed. A two-bit decomposition of the relative address shift signal (the first bit for a decrement or no decrement, the second for an increment or no increment, with decrementing taking precedence because it is associated with flip-flop enable).

The separate read and write addressing of a bit currents during its passage through the second 16- Bit register (in MEM) requires a double clock frequency for separate read and write access to enable. An 8: 4-bit MUX is for alternating Require selection between read and write addresses such. It is readily apparent to those skilled in the art how to provide this MUX in 2 CLB, so here is not discussed in more detail.

A final CLB can be used to determine the Ab dependence of the incrementifer-stationary-decrement-Si gnals from the local and neighboring bit streams generate, as in the control unit (CTL) of the Pro totyps of the genetic switch has happened. Choice wise is a single function generator (H) with three Inputs and a flip-flop sufficient to the half fre deliver clock pulse if this is to improve stability should be required. These could be packed in one of the two MUX-CLB.

The final design of the unit is 9 CLB (KAM, shared R / W MEM, 2 for the write address, 2 for the MUX, CTL, SWI and incrementing / decremes tier control). This shows how a significant new one Insert and delete functionality up to 16 Bit can be included while at the same time relatively small units are retained. The reason Legendary idea of shared addressing can go too far extension of the functionality can be used.

5. Experimental suggestions for the genetics processor

With the very large number to be considered The computer has been ideal for generations suitable, questions of evolutionary stagnation and Punktua tion in time scales that are used with the Evolu history on earth are comparable. In particular especially the difficult transition from independent replicas to complex, functionally integrated components It can be used to examine higher organisms (admittedly in the model constructed here abstract logical genetic world). Furthermore questions of long-term optimization can interact in the systems are examined. First of all, the Mixing properties of the sequence dependent outsourcing in the prototype model and then the population dynamics the purely replicative copy functionality examined before the variation and the selection as a whole prototype. Surrender already here interesting questions about the timescale for optimization and evolutionary stability.

Having in this way the interest in such the level of Giga generations expanded logical Evolutionary processes can now be established other biologically relevant and complex inter action patterns are examined. Other investigations of the numerous alternative genetic interactions schemes used to study functional interaction can be used in evolution shut down. The Darge in the previous section genetic, similar to a Turing switch Switch gives an idea of the complexity level that can be achieved in small subdesigns.

Claims (10)

1. Device for calculating fine-grained parallel problems that can be described as a plurality of interconnected discretizable processes with

• - Several programmable in array form arranged adjacent logic circuits, each having
  • several configurable logic circuit blocks which are composed of regularly arranged logic cells and are freely configurable,
  • several programmable switch matrices for regularly connecting the logic circuit blocks to one another in accordance with the switch matrix programming,
  • a plurality of programmable I / O blocks with I / O connections for regularly connecting the plurality of programmable logic circuits to one another and for connecting at least one of the logic circuits to a host computer,
  • - wherein several logic circuit blocks are each grouped into identical groups, each of which is assigned a certain predetermined number of I / O connections, which depends on the size of the group of logic circuit blocks and is used for regularly connecting groups of logic circuit blocks to one another and for connection two groups of logic circuit blocks of adjacent logic circuits are available,
  • the geometry of the groups of combined logic circuit blocks is the same from group to group,
  • the connection between the groups of logic circuit blocks and the connection between the logic circuit blocks of the groups is the same,
• - The connection between the individual logic circuits is such that the number of connections, which is given to the user due to the type of grouping of logic circuit blocks, is maximum, and the connection of groups of logic circuit block groups of adjacent logic circuits is equal to the connection of the United Groups of logic circuit blocks is one and the same logic circuit, and
• - A clock generator device, which is connected to the logic circuits and their groups of logic circuit blocks and to their logic cells in such a way that the clocking of all logic cells takes place globally and synchronously.

2. Device for calculating fine-grained parallel problems that can be described as a plurality of interlinked discretizable processes with

• - A programmable logic circuit, which has
  • several configurable logic circuit blocks which are composed of regularly arranged logic cells and are freely configurable,
  • several programmable switch matrices for regularly connecting the logic circuit blocks to one another in accordance with the switch matrix programming,
  • at least one programmable I / O block with I / O connections for connecting the logic circuit to a host computer,
  • - wherein several logic circuit blocks are each grouped into identical groups, each of which is assigned a certain number of I / O connections, which is predetermined in advance and is dependent on the size of the group of logic circuit blocks, and which are available for regularly connecting groups of logic circuit blocks to one another ,
  • the geometry of the groups of combined logic circuit blocks is the same from group to group,
  • the connection between the groups of logic circuit blocks and the connection between the logic circuit blocks of the groups is the same,
• - The connection between the individual logic circuits is such that the number of connections, which is given to the user due to the type of grouping of logic circuit blocks, is maximum, and
• - A clock generator device which is connected to the groups of logic circuit blocks and to their logic cells in such a way that the clocking of all logic cells takes place globally and synchronously.

3. A method for configuring a device for calculating fine-grained parallelizable problems, which can be described as a plurality of interlinked discretizable processes, in which

• a predetermined circle of problems to be calculated is represented as a certain geometric arrangement of the same groups of processes, the processes of a problem area being the same or different,
• - the processes and the linking of the processes in the problem area are identified and defined,
• - Individual processes are combined into groups and these groups are implemented in terms of circuitry by combining and connecting several programmable logic cells to form logic circuit blocks of one or more logic circuits and
• - The individual identical groups of logic circuit blocks the connection of the processes of the problem area who connected accordingly, these connections from group to group and within the groups of logic circuit block to logic circuit block are the same.

4. The method according to claim 3, characterized in that multiple programmable logic circuits featured regularly adjacent to each other are seen, the connection pattern between Logic circuit block groups of adjacent logic circuits identical to the connection pattern of the Logic circuit block groups of one and the same Logic circuit is.   5. The method according to claim 3 or 4, characterized records that a connection at least one Logic circuit built up to a host computer becomes. 6. Use of configurable logic circuit Arrays with distributed memories for simulation scientific, business and economist economically and logistically parallelizable fine-grained problems, especially for the simula tion of biotechnological systems, evolving Systems. 7. Use of configurable logic circuit Arrays with distributed memories for calculating Problems of combinatorial optimization esp special of optimal routing. 8. Use of configurable logic circuit Arrays with distributed memories for implementation creation of genetic algorithms, neural Networks or other distributed systems. 9. Use of configurable logic circuit Distributed Storage Arrays to Solve Problems of parallel comparison, Change, sort and / or search for Data strings in databases or the like 10. Use of configurable logic circuit Arrays with distributed storage for development of special digital circuits by Popula dynamic of interactive partial reconfiguration hardware and calculations based on  genetic manipulation of local configuration representative data strings.