DE3851014T2 - Eine Vielzahl an Regeln enthaltendes System mit einer vorausermittelten Inferenz-Strategie. - Google Patents
Eine Vielzahl an Regeln enthaltendes System mit einer vorausermittelten Inferenz-Strategie.Info
- Publication number
- DE3851014T2 DE3851014T2 DE3851014T DE3851014T DE3851014T2 DE 3851014 T2 DE3851014 T2 DE 3851014T2 DE 3851014 T DE3851014 T DE 3851014T DE 3851014 T DE3851014 T DE 3851014T DE 3851014 T2 DE3851014 T2 DE 3851014T2
- Authority
- DE
- Germany
- Prior art keywords
- rules
- large number
- system containing
- inference strategy
- predicted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N5/00—Computing arrangements using knowledge-based models
- G06N5/04—Inference or reasoning models
- G06N5/046—Forward inferencing; Production systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N5/00—Computing arrangements using knowledge-based models
- G06N5/01—Dynamic search techniques; Heuristics; Dynamic trees; Branch-and-bound
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S706/00—Data processing: artificial intelligence
- Y10S706/902—Application using ai with detail of the ai system
- Y10S706/919—Designing, planning, programming, CAD, CASE
- Y10S706/921—Layout, e.g. circuit, construction
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62109046A JPH0652502B2 (ja) | 1987-05-06 | 1987-05-06 | 推論方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3851014D1 DE3851014D1 (de) | 1994-09-15 |
DE3851014T2 true DE3851014T2 (de) | 1995-03-09 |
Family
ID=14500235
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE3851014T Expired - Fee Related DE3851014T2 (de) | 1987-05-06 | 1988-05-03 | Eine Vielzahl an Regeln enthaltendes System mit einer vorausermittelten Inferenz-Strategie. |
Country Status (4)
Country | Link |
---|---|
US (1) | US4937755A (de) |
EP (1) | EP0297248B1 (de) |
JP (1) | JPH0652502B2 (de) |
DE (1) | DE3851014T2 (de) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5151867A (en) * | 1986-09-12 | 1992-09-29 | Digital Equipment Corporation | Method of minimizing sum-of-product cases in a heterogeneous data base environment for circuit synthesis |
US5095441A (en) * | 1986-09-12 | 1992-03-10 | Digital Equipment Corporation | Rule inference and localization during synthesis of logic circuit designs |
US5150308A (en) * | 1986-09-12 | 1992-09-22 | Digital Equipment Corporation | Parameter and rule creation and modification mechanism for use by a procedure for synthesis of logic circuit designs |
US5212650A (en) * | 1986-09-12 | 1993-05-18 | Digital Equipment Corporation | Procedure and data structure for synthesis and transformation of logic circuit designs |
US5249260A (en) * | 1988-08-12 | 1993-09-28 | Hitachi, Ltd. | Data input system |
US5177688A (en) * | 1989-12-01 | 1993-01-05 | Texas Instruments Incorporated | Assembly line balancer |
JPH047743A (ja) * | 1990-04-26 | 1992-01-13 | Toshiba Corp | 推論システム |
JP3049561B2 (ja) * | 1990-05-21 | 2000-06-05 | 東洋通信機株式会社 | プロダクションシステムとプロダクションシステムの変換装置 |
US5263126A (en) * | 1992-09-10 | 1993-11-16 | Chang Hou Mei H | Automatic expert system |
US5720009A (en) * | 1993-08-06 | 1998-02-17 | Digital Equipment Corporation | Method of rule execution in an expert system using equivalence classes to group database objects |
US5510998A (en) * | 1994-06-13 | 1996-04-23 | Cadence Design Systems, Inc. | System and method for generating component models |
US6253351B1 (en) * | 1998-03-24 | 2001-06-26 | Matsushita Electric Industrial Co., Ltd. | Circuit optimization system |
US7216113B1 (en) * | 2000-03-24 | 2007-05-08 | Symyx Technologies, Inc. | Remote Execution of Materials Library Designs |
US6993733B2 (en) * | 2002-04-09 | 2006-01-31 | Atrenta, Inc. | Apparatus and method for handling of multi-level circuit design data |
TW200742396A (en) * | 2006-04-17 | 2007-11-01 | Benq Corp | Method of searching communication addresses |
CN105468363B (zh) * | 2015-11-19 | 2018-06-26 | 浪潮电子信息产业股份有限公司 | 一种增强服务器主板与不同网卡兼容性的方法 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4145735A (en) * | 1977-02-02 | 1979-03-20 | Nippon Steel Corporation | Monitor for priority level of task in information processing system |
JPS58222376A (ja) * | 1982-06-18 | 1983-12-24 | Fujitsu Ltd | テ−ブルサ−チ方式 |
JPS59168545A (ja) * | 1983-03-15 | 1984-09-22 | Fujitsu Ltd | 論理回路変換処理装置 |
JPS6024646A (ja) * | 1983-07-20 | 1985-02-07 | Hitachi Ltd | 適応型推論処理方式 |
JPS60114968A (ja) * | 1983-11-28 | 1985-06-21 | Hitachi Ltd | 推論システム |
US4649515A (en) * | 1984-04-30 | 1987-03-10 | Westinghouse Electric Corp. | Methods and apparatus for system fault diagnosis and control |
US4703435A (en) * | 1984-07-16 | 1987-10-27 | International Business Machines Corporation | Logic Synthesizer |
EP0169576B1 (de) * | 1984-07-27 | 1990-12-19 | Hitachi, Ltd. | Verfahren und System zum Verstehen und Belegen von Schaltungsmustern |
JPS61109148A (ja) * | 1984-11-01 | 1986-05-27 | Agency Of Ind Science & Technol | プロダクシヨン・ル−ルの競合解消方式 |
US4816994A (en) * | 1984-12-04 | 1989-03-28 | Tektronix, Inc. | Rule acquisition for expert systems |
US4635208A (en) * | 1985-01-18 | 1987-01-06 | Hewlett-Packard Company | Computer-aided design of systems |
US4670848A (en) * | 1985-04-10 | 1987-06-02 | Standard Systems Corporation | Artificial intelligence system |
JPH0668756B2 (ja) * | 1985-04-19 | 1994-08-31 | 株式会社日立製作所 | 回路自動変換方法 |
JPS6214227A (ja) * | 1985-07-12 | 1987-01-22 | Hitachi Ltd | 推論過程の制御方式 |
US4748439A (en) * | 1985-08-13 | 1988-05-31 | Fairchild Semiconductor Corporation | Memory apparatus and method for retrieving sequences of symbols including variable elements |
JPS62198930A (ja) * | 1986-02-26 | 1987-09-02 | Matsushita Electric Ind Co Ltd | 推論方法 |
JPS634333A (ja) * | 1986-06-24 | 1988-01-09 | Toshiba Corp | エキスパ−トシステム |
-
1987
- 1987-05-06 JP JP62109046A patent/JPH0652502B2/ja not_active Expired - Lifetime
-
1988
- 1988-04-28 US US07/187,590 patent/US4937755A/en not_active Expired - Fee Related
- 1988-05-03 DE DE3851014T patent/DE3851014T2/de not_active Expired - Fee Related
- 1988-05-03 EP EP88107101A patent/EP0297248B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
DE3851014D1 (de) | 1994-09-15 |
JPH0652502B2 (ja) | 1994-07-06 |
EP0297248A3 (de) | 1992-03-04 |
EP0297248A2 (de) | 1989-01-04 |
JPS63273939A (ja) | 1988-11-11 |
EP0297248B1 (de) | 1994-08-10 |
US4937755A (en) | 1990-06-26 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |