DE3586770D1 - Phasenregelschleife zur mfm-datenaufzeichnung. - Google Patents

Phasenregelschleife zur mfm-datenaufzeichnung.

Info

Publication number: DE3586770D1
Authority: DE; Germany
Prior art keywords: data recording; control loop; phase control; mfm data; mfm
Prior art date: 1984-11-13
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Expired - Fee Related

Application number

DE8585402139T

Other languages

English (en)

Other versions

DE3586770T2 (de

Inventor

Robert Anthony Shaw

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Digital Equipment Corp

Original Assignee

Digital Equipment Corp

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1984-11-13

Filing date

1985-11-06

Publication date

1992-11-26

1985-11-06 Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp

1992-11-26 Application granted granted Critical

1992-11-26 Publication of DE3586770D1 publication Critical patent/DE3586770D1/de

1993-06-03 Publication of DE3586770T2 publication Critical patent/DE3586770T2/de

2005-11-07 Anticipated expiration legal-status Critical

Status Expired - Fee Related legal-status Critical Current

Links

Classifications

- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
- G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code

DE8585402139T 1984-11-13 1985-11-06 Phasenregelschleife zur mfm-datenaufzeichnung. Expired - Fee Related DE3586770T2 (de)

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
US06/670,825 US4633488A (en)	1984-11-13	1984-11-13	Phase-locked loop for MFM data recording

Publications (2)

Publication Number	Publication Date
DE3586770D1 true DE3586770D1 (de)	1992-11-26
DE3586770T2 DE3586770T2 (de)	1993-06-03

Family

ID=24692035

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
DE8585402139T Expired - Fee Related DE3586770T2 (de)	1984-11-13	1985-11-06	Phasenregelschleife zur mfm-datenaufzeichnung.

Country Status (7)

Country	Link
US (1)	US4633488A (de)
EP (1)	EP0182701B1 (de)
JP (1)	JPH0612591B2 (de)
KR (1)	KR940000975B1 (de)
AU (1)	AU574982B2 (de)
CA (1)	CA1255362A (de)
DE (1)	DE3586770T2 (de)

Families Citing this family (50)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US4780844A (en) *	1986-07-18	1988-10-25	Commodore-Amiga, Inc.	Data input circuit with digital phase locked loop
IT1197969B (it) *	1986-11-12	1988-12-21	Honeywell Inf Systems	Circuito ad aggancio di fase
JPS63138506A (ja) *	1986-11-29	1988-06-10	Toshiba Corp	フロツピ−デイスク装置のデ−タ再生回路
US4847876A (en) *	1986-12-31	1989-07-11	Raytheon Company	Timing recovery scheme for burst communication systems
US4787097A (en) *	1987-02-11	1988-11-22	International Business Machines Corporation	NRZ phase-locked loop circuit with associated monitor and recovery circuitry
GB8703769D0 (en) *	1987-02-18	1987-03-25	Thorn Emi Datatech Ltd	Circuit
US4800340A (en) *	1987-04-22	1989-01-24	Silicon System, Ins.	Method and apparatus for generating a data recovery window
US4803445B3 (en) *	1987-04-22	1996-12-31	Silicon Systems Inc	Variable frequency oscillator
US4805198A (en) *	1987-05-19	1989-02-14	Crystal Semiconductor Corporation	Clock multiplier/jitter attenuator
US5150386A (en) *	1987-05-19	1992-09-22	Crystal Semiconductor Corporation	Clock multiplier/jitter attenuator
US4823209A (en) *	1987-11-05	1989-04-18	Magnetic Peripherals Inc.	1,7,2,3 Encoding/decoding employing 3/2 frequency division
US5349544A (en) *	1988-06-15	1994-09-20	Advanced Micro Devices, Inc.	Programmable system synchronizer
US4926447A (en) *	1988-11-18	1990-05-15	Hewlett-Packard Company	Phase locked loop for clock extraction in gigabit rate data communication links
US5077529A (en) *	1989-07-19	1991-12-31	Level One Communications, Inc.	Wide bandwidth digital phase locked loop with reduced low frequency intrinsic jitter
US5062123A (en) *	1989-08-16	1991-10-29	Cincinnati Electronics Corporation	Kalman predictor for providing a relatively noise free indication of the phase of a carrier laden with noise
US5118975A (en) *	1990-03-05	1992-06-02	Thinking Machines Corporation	Digital clock buffer circuit providing controllable delay
JP3140483B2 (ja) *	1991-05-24	2001-03-05	株式会社日立製作所	同期データ取り込み方法および回路
US5216554A (en) *	1991-07-01	1993-06-01	International Business Machines Corporation	Digital phase error estimator
US5126690A (en) *	1991-08-08	1992-06-30	International Business Machines Corporation	Phase locked loop lock detector including loss of lock and gain of lock detectors
US5285483A (en) *	1992-04-07	1994-02-08	Seiko Epson Corporation	Phase synchronization circuit
US5493243A (en) *	1994-01-04	1996-02-20	Level One Communications, Inc.	Digitally controlled first order jitter attentuator using a digital frequency synthesizer
US5418496A (en) *	1994-02-07	1995-05-23	Motorola, Inc.	Serial data clock recovery circuit using dual oscillator circuit
CA2116042C (en) *	1994-02-21	1999-03-23	Alexander F. Tulai	Digital fsk receiver using double zero-crossing
US5438300A (en) *	1994-04-01	1995-08-01	National Semiconductor Corporation	Digital frequency multiplier utilizing digital controlled oscillator
US5553100A (en) *	1994-04-01	1996-09-03	National Semiconductor Corporation	Fully digital data separator and frequency multiplier
US5598443A (en) *	1994-05-23	1997-01-28	At&T Global Information Solutions Company (Aka Ncr Corporation)	Method and apparatus for separating data and clock from a digital data stream
US5532636A (en) *	1995-03-10	1996-07-02	Intel Corporation	Source-switched charge pump circuit
US5744991A (en) *	1995-10-16	1998-04-28	Altera Corporation	System for distributing clocks using a delay lock loop in a programmable logic circuit
KR0154789B1 (ko) *	1995-12-11	1998-12-15	김광호	직류레벨 포획장치가 결합된 위상동기루프
US6249557B1 (en)	1997-03-04	2001-06-19	Level One Communications, Inc.	Apparatus and method for performing timing recovery
US6249555B1 (en)	1997-07-14	2001-06-19	Grass Valley (Us) Inc.	Low jitter digital extraction of data from serial bitstreams
JP3024614B2 (ja) *	1997-10-24	2000-03-21	日本電気株式会社	ばらつき補償技術による半導体集積回路
US6346827B1 (en)	1998-09-09	2002-02-12	Altera Corporation	Programmable logic device input/output circuit configurable as reference voltage input circuit
US6218876B1 (en)	1999-01-08	2001-04-17	Altera Corporation	Phase-locked loop circuitry for programmable logic devices
US6483886B1 (en)	1999-01-08	2002-11-19	Altera Corporation	Phase-locked loop circuitry for programmable logic devices
US6472903B1 (en)	1999-01-08	2002-10-29	Altera Corporation	Programmable logic device input/output architecture with power bus segmentation for multiple I/O standards
US6177844B1 (en)	1999-01-08	2001-01-23	Altera Corporation	Phase-locked loop or delay-locked loop circuitry for programmable logic devices
US6252419B1 (en)	1999-01-08	2001-06-26	Altera Corporation	LVDS interface incorporating phase-locked loop circuitry for use in programmable logic device
US6832173B1 (en)	2002-07-30	2004-12-14	Altera Corporation	Testing circuit and method for phase-locked loop
US7010376B2 (en) *	2002-10-25	2006-03-07	Pulp And Paper Research Institute Of Canada	Diagnostic for poorly tuned control loops
US6867616B1 (en)	2003-06-04	2005-03-15	Altera Corporation	Programmable logic device serial interface having dual-use phase-locked loop circuitry
US7019570B2 (en) *	2003-09-05	2006-03-28	Altera Corporation	Dual-gain loop circuitry for programmable logic device
US6924678B2 (en) *	2003-10-21	2005-08-02	Altera Corporation	Programmable phase-locked loop circuitry for programmable logic device
US7091760B1 (en)	2004-02-25	2006-08-15	Altera Corporation	DLL with adjustable phase shift using processed control signal
US7073629B2 (en) *	2004-02-26	2006-07-11	The Boeing Company	Ladder support apparatus and methods
US7075365B1 (en)	2004-04-22	2006-07-11	Altera Corporation	Configurable clock network for programmable logic device
US7230495B2 (en)	2004-04-28	2007-06-12	Micron Technology, Inc.	Phase-locked loop circuits with reduced lock time
US7436228B1 (en)	2005-12-22	2008-10-14	Altera Corporation	Variable-bandwidth loop filter methods and apparatus
US7728674B1 (en)	2006-05-19	2010-06-01	Altera Corporation	Voltage-controlled oscillator methods and apparatus
US9853807B2 (en) *	2016-04-21	2017-12-26	Taiwan Semiconductor Manufacturing Co., Ltd.	Automatic detection of change in PLL locking trend

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
GB954942A (en) *	1961-02-01	1964-04-08	Potter Instrument Co Inc	Improvements in or relating to high density recording systems
US3794987A (en) *	1972-11-01	1974-02-26	Burroughs Corp	Mfm readout with assymetrical data window
US3950658A (en) *	1974-10-15	1976-04-13	International Business Machines Corporation	Data separator with compensation circuit
US4017803A (en) *	1976-01-29	1977-04-12	Sperry Rand Corporation	Data recovery system resistant to frequency deviations
DE2906200C3 (de) *	1979-02-17	1982-02-11	Philips Patentverwaltung Gmbh, 2000 Hamburg	Synchronisieranordnung
US4357707A (en) *	1979-04-11	1982-11-02	Pertec Computer Corporation	Digital phase lock loop for flexible disk data recovery system
JPS5624829A (en) *	1979-08-08	1981-03-10	Hitachi Ltd	Vfo circuit
JPS576423A (en) *	1980-06-13	1982-01-13	Sanyo Electric Co Ltd	Demodulating circuit of mfm modulation signal
JPS57111813A (en) *	1980-12-29	1982-07-12	Fujitsu Ltd	Data demodulating system
JPS57195311A (en) *	1981-05-26	1982-12-01	Victor Co Of Japan Ltd	Clock regenerating circuit
GB2112235B (en) *	1981-12-02	1986-01-02	Standard Microsyst Smc	Improved floppy disk data separator
JPS58182938A (ja) *	1982-04-21	1983-10-26	Toshiba Corp	Ｐｌｌ形タイミング抽出回路

1984
- 1984-11-13 US US06/670,825 patent/US4633488A/en not_active Expired - Lifetime
1985
- 1985-11-06 EP EP85402139A patent/EP0182701B1/de not_active Expired - Lifetime
- 1985-11-06 DE DE8585402139T patent/DE3586770T2/de not_active Expired - Fee Related
- 1985-11-12 CA CA000495123A patent/CA1255362A/en not_active Expired
- 1985-11-12 KR KR1019850008433A patent/KR940000975B1/ko not_active IP Right Cessation
- 1985-11-12 AU AU49767/85A patent/AU574982B2/en not_active Ceased
- 1985-11-13 JP JP60254611A patent/JPH0612591B2/ja not_active Expired - Lifetime

Also Published As

Publication number	Publication date
JPS61120381A (ja)	1986-06-07
AU574982B2 (en)	1988-07-14
DE3586770T2 (de)	1993-06-03
EP0182701B1 (de)	1992-10-21
JPH0612591B2 (ja)	1994-02-16
CA1255362A (en)	1989-06-06
EP0182701A2 (de)	1986-05-28
KR940000975B1 (ko)	1994-02-07
EP0182701A3 (en)	1988-08-03
KR860004401A (ko)	1986-06-20
AU4976785A (en)	1986-05-22
US4633488A (en)	1986-12-30

Legal Events

Date	Code	Title	Description
1993-11-18	8364	No opposition during term of opposition
2002-11-07	8339	Ceased/non-payment of the annual fee

Publication	Publication Date	Title
DE3586770D1 (de)	1992-11-26	Phasenregelschleife zur mfm-datenaufzeichnung.
DE68917638T2 (de)	1994-12-22	Magneto-optisches Datenaufzeichnungssystem.
DE3679203D1 (de)	1991-06-20	Betriebsdatenaufzeichnungssystem.
DE3778168D1 (de)	1992-05-21	Magnetisches aufzeichnungsmedium.
DE3750413T2 (de)	1995-03-02	gerät zur Wiedergabe einer Datenaufzeichnungsplatte.
DE3784323T2 (de)	1993-07-29	Datenaufzeichnung.
DE3885825D1 (de)	1994-01-05	Magnetische Aufzeichnungsträger.
EP0243821A3 (en)	1989-02-08	A servo control system for a data recording disk file
DE3485278D1 (de)	1992-01-02	System zur informationsaufzeichnung.
DE3773239D1 (de)	1991-10-31	Magnetisches aufzeichnungsmedium.
DE3580555D1 (de)	1990-12-20	Geraet zur wiedergabe von daten von aufzeichnungsplatten.
DE3855647D1 (de)	1996-12-12	Plattendatei zur Aufnahme von Daten mit digitaler Servosteuerung
DE3485596D1 (de)	1992-04-23	Pcm-daten-aufzeichnungssystem.
DE3853640D1 (de)	1995-06-01	Informationsaufzeichnungsmedium.
DE3881314T2 (de)	1993-12-02	Datenaufzeichnungs-Plattendatei mit digitaler Nachlaufregelung.
DE68924635D1 (de)	1995-11-30	Datenaufzeichnungsgerät.
DE68921453T2 (de)	1995-07-13	Informationsaufzeichnungsträger.
DE3580635D1 (de)	1991-01-03	Magnetisches aufzeichnungsmedium.
DE3575357D1 (de)	1990-02-15	Magnetisches aufzeichnungsmedium.
DE3581844D1 (de)	1991-04-04	System zur wiedergabe von digitalen daten.
DE3585243D1 (de)	1992-03-05	Magnetisches aufnahme- oder wiedergabesystem mit zusammengesetztem magnetkopf.
DE3854370D1 (de)	1995-10-05	Datenaufzeichnungsmedium.
DE3880048T2 (de)	1993-11-11	Aufzeichnungsträger mit senkrechter Magnetisierung.
DE3764046D1 (de)	1990-09-06	Informationsaufzeichnungsmethode.
DE3481661D1 (de)	1990-04-19	Magnetisches aufzeichnungsmedium.