DE3586486T2 - Interface-vorrichtung zwischen mindestens einem kanal und mindestens einem bus. - Google Patents

Interface-vorrichtung zwischen mindestens einem kanal und mindestens einem bus.

Info

Publication number
DE3586486T2
DE3586486T2 DE8585630226T DE3586486T DE3586486T2 DE 3586486 T2 DE3586486 T2 DE 3586486T2 DE 8585630226 T DE8585630226 T DE 8585630226T DE 3586486 T DE3586486 T DE 3586486T DE 3586486 T2 DE3586486 T2 DE 3586486T2
Authority
DE
Germany
Prior art keywords
bus
channel
interface device
interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8585630226T
Other languages
English (en)
Other versions
DE3586486D1 (de
Inventor
Bhalchandra Ramchandra Tulpule
Matthew Scott Blaha
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Raytheon Technologies Corp
Original Assignee
United Technologies Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Technologies Corp filed Critical United Technologies Corp
Publication of DE3586486D1 publication Critical patent/DE3586486D1/de
Application granted granted Critical
Publication of DE3586486T2 publication Critical patent/DE3586486T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2002—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant
    • G06F11/2005—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant using redundant communication controllers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2002—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant
    • G06F11/2007—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant using redundant communication media
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
DE8585630226T 1984-12-13 1985-12-13 Interface-vorrichtung zwischen mindestens einem kanal und mindestens einem bus. Expired - Fee Related DE3586486T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/681,172 US4625307A (en) 1984-12-13 1984-12-13 Apparatus for interfacing between at least one channel and at least one bus

Publications (2)

Publication Number Publication Date
DE3586486D1 DE3586486D1 (de) 1992-09-17
DE3586486T2 true DE3586486T2 (de) 1993-03-18

Family

ID=24734140

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585630226T Expired - Fee Related DE3586486T2 (de) 1984-12-13 1985-12-13 Interface-vorrichtung zwischen mindestens einem kanal und mindestens einem bus.

Country Status (3)

Country Link
US (1) US4625307A (de)
EP (1) EP0184976B1 (de)
DE (1) DE3586486T2 (de)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL8500571A (nl) * 1985-03-01 1986-10-01 Hollandse Signaalapparaten Bv Locaal data-communicatienetwerk volgens het multiple-bus-systeem.
US4987530A (en) * 1985-11-15 1991-01-22 Data General Corp. Input/output controller for a data processing system
US5093910A (en) * 1986-10-29 1992-03-03 United Technologies Corporation Serial data transmission between redundant channels
US4878197A (en) * 1987-08-17 1989-10-31 Control Data Corporation Data communication apparatus
US4935894A (en) * 1987-08-31 1990-06-19 Motorola, Inc. Multi-processor, multi-bus system with bus interface comprising FIFO register stocks for receiving and transmitting data and control information
US5012404A (en) * 1988-10-28 1991-04-30 United Technologies Corporation Integrated circuit remote terminal stores interface for communication between CPU and serial bus
US5023891A (en) * 1989-07-25 1991-06-11 Sf2 Corporation Method and circuit for decoding a Manchester code signal
JP2814132B2 (ja) * 1990-03-15 1998-10-22 株式会社日立製作所 マルチチャネル通信処理装置
US6324120B2 (en) 1990-04-18 2001-11-27 Rambus Inc. Memory device having a variable data output length
US6751696B2 (en) 1990-04-18 2004-06-15 Rambus Inc. Memory device having a programmable register
IL96808A (en) 1990-04-18 1996-03-31 Rambus Inc Introductory / Origin Circuit Agreed Using High-Performance Brokerage
US5457786A (en) * 1990-07-03 1995-10-10 Texas Instruments Incorporated Serial data interface with circular buffer
US5136584A (en) * 1990-07-11 1992-08-04 At&T Bell Laboratories Hardware interface to a high-speed multiplexed link
DE4035459C1 (de) * 1990-11-08 1992-05-14 Messerschmitt-Boelkow-Blohm Gmbh, 8012 Ottobrunn, De
US5566301A (en) * 1992-02-11 1996-10-15 Futuretel, Inc. ISDN audiovisual teleservices interface subsystem
WO1993016430A1 (en) * 1992-02-11 1993-08-19 Koz Mark C An isdn audiovisual teleservices interface subsystem
US5414814A (en) * 1992-05-08 1995-05-09 The United States Of America As Represented By The Secretary Of The Navy I/O interface between VME bus and asynchronous serial data computer
US5335326A (en) * 1992-10-01 1994-08-02 Xerox Corporation Multichannel FIFO device channel sequencer
US5617544A (en) * 1994-12-23 1997-04-01 United Technologies Corporation Interface having receive and transmit message label memories for providing communication between a host computer and a bus
FR2737029B1 (fr) * 1995-07-19 1997-09-26 Sextant Avionique Dispositif d'interface entre un calculateur a architecture redondante et un moyen de communication
US6314481B1 (en) * 1999-01-19 2001-11-06 Phoenix Logistics, Inc. Resistance integrated coupler between databus and terminal device having databus windings with high resistance wire with resistance being 1.5 times databus cable nominal characteristic impedance
US6360290B1 (en) 1999-06-23 2002-03-19 United Technologies Corporation Commercial standard digital bus interface circuit
US7684383B1 (en) * 2002-01-30 2010-03-23 3Com Corporation Method and system for dynamic call type detection for circuit and packet switched networks
US7541697B2 (en) * 2005-10-14 2009-06-02 The Boeing Company Systems and methods for lighting control in flight deck devices
KR20100135711A (ko) 2007-12-20 2010-12-27 엔비보 파마슈티칼즈, 인코퍼레이티드 사중치환된 벤젠
CN116016708A (zh) * 2023-02-17 2023-04-25 浙江中控研究院有限公司 一种1553b总线与blvds总线转换方法及装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2714106C3 (de) * 1977-03-30 1982-01-14 Telefonbau Und Normalzeit Gmbh, 6000 Frankfurt Verfahren zum Zwischenspeichern von Informationen in einem FIFO-Speicher
US4259719A (en) * 1979-06-13 1981-03-31 Ford Motor Company Binary input processing in a computer using a stack
US4516239A (en) * 1982-03-15 1985-05-07 At&T Bell Laboratories System, apparatus and method for controlling a multiple access data communications system including variable length data packets and fixed length collision-free voice packets
US4569041A (en) * 1983-03-17 1986-02-04 Nec Corporation Integrated circuit/packet switching system

Also Published As

Publication number Publication date
DE3586486D1 (de) 1992-09-17
EP0184976B1 (de) 1992-08-12
EP0184976A3 (en) 1989-01-25
EP0184976A2 (de) 1986-06-18
US4625307A (en) 1986-11-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee