DE3572244D1 - Stability testing of semiconductor memories - Google Patents
Stability testing of semiconductor memoriesInfo
- Publication number
- DE3572244D1 DE3572244D1 DE8585103736T DE3572244T DE3572244D1 DE 3572244 D1 DE3572244 D1 DE 3572244D1 DE 8585103736 T DE8585103736 T DE 8585103736T DE 3572244 T DE3572244 T DE 3572244T DE 3572244 D1 DE3572244 D1 DE 3572244D1
- Authority
- DE
- Germany
- Prior art keywords
- semiconductor memories
- stability testing
- testing
- stability
- memories
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/025—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in signal lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C29/50016—Marginal testing, e.g. race, voltage or current testing of retention
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP85103736A EP0195839B1 (de) | 1985-03-29 | 1985-03-29 | Stabilitätsprüfung für Halbleiterspeicher |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3572244D1 true DE3572244D1 (en) | 1989-09-14 |
Family
ID=8193407
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8585103736T Expired DE3572244D1 (en) | 1985-03-29 | 1985-03-29 | Stability testing of semiconductor memories |
Country Status (5)
Country | Link |
---|---|
US (1) | US4713814A (de) |
EP (1) | EP0195839B1 (de) |
JP (1) | JPS61224199A (de) |
CA (1) | CA1238124A (de) |
DE (1) | DE3572244D1 (de) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4779043A (en) * | 1987-08-26 | 1988-10-18 | Hewlett-Packard Company | Reversed IC test device and method |
JPH01208795A (ja) * | 1988-02-16 | 1989-08-22 | Toshiba Corp | 半導体記憶装置 |
GB2277822A (en) * | 1993-05-04 | 1994-11-09 | Motorola Inc | A memory system with selectable row power down |
TW389908B (en) * | 1998-01-16 | 2000-05-11 | Winbond Electronics Corp | Patching method capable of reducing the additional leakage current caused by manufacturing defects |
CN108231134B (zh) * | 2018-02-08 | 2021-06-25 | 芯颖科技有限公司 | Ram良率补救方法及装置 |
CN112071357B (zh) * | 2020-08-27 | 2022-08-02 | 南京航天航空大学 | 基于fpga的sram存储器充放电效应测试系统及方法 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3995215A (en) * | 1974-06-26 | 1976-11-30 | International Business Machines Corporation | Test technique for semiconductor memory array |
US4004222A (en) * | 1974-11-20 | 1977-01-18 | Semi | Test system for semiconductor memory cell |
DE2612666C2 (de) * | 1976-03-25 | 1982-11-18 | Ibm Deutschland Gmbh, 7000 Stuttgart | Integrierte, invertierende logische Schaltung |
US4418403A (en) * | 1981-02-02 | 1983-11-29 | Mostek Corporation | Semiconductor memory cell margin test circuit |
US4430735A (en) * | 1981-05-26 | 1984-02-07 | Burroughs Corporation | Apparatus and technique for testing IC memories |
US4503538A (en) * | 1981-09-04 | 1985-03-05 | Robert Bosch Gmbh | Method and system to recognize change in the storage characteristics of a programmable memory |
JPS5853775A (ja) * | 1981-09-26 | 1983-03-30 | Fujitsu Ltd | Icメモリ試験方法 |
US4502140A (en) * | 1983-07-25 | 1985-02-26 | Mostek Corporation | GO/NO GO margin test circuit for semiconductor memory |
US4606025A (en) * | 1983-09-28 | 1986-08-12 | International Business Machines Corp. | Automatically testing a plurality of memory arrays on selected memory array testers |
US4608669A (en) * | 1984-05-18 | 1986-08-26 | International Business Machines Corporation | Self contained array timing |
US4612630A (en) * | 1984-07-27 | 1986-09-16 | Harris Corporation | EEPROM margin testing design |
-
1985
- 1985-03-29 DE DE8585103736T patent/DE3572244D1/de not_active Expired
- 1985-03-29 EP EP85103736A patent/EP0195839B1/de not_active Expired
- 1985-12-04 JP JP60271729A patent/JPS61224199A/ja active Granted
-
1986
- 1986-01-17 CA CA000499842A patent/CA1238124A/en not_active Expired
- 1986-03-13 US US06/839,315 patent/US4713814A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US4713814A (en) | 1987-12-15 |
EP0195839A1 (de) | 1986-10-01 |
CA1238124A (en) | 1988-06-14 |
EP0195839B1 (de) | 1989-08-09 |
JPS61224199A (ja) | 1986-10-04 |
JPH0355919B2 (de) | 1991-08-26 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |