DE3130504A1 - Arrangement for generating cyclically coded information - Google Patents

Abstract

In a circuit arrangement for generating protected information, the data present block by block, after being EXORed, are applied to a flip flop. After that, the data are conducted to the two storage areas of a PROM (3, 4) where they are logically combined in accordance with a particular table. The data blocks of the two PROM areas are then conducted to another EXOR element (6), one data block first being delayed by one clock period in a flip flop (5). After being logically combined in the EXOR element (6), the result is then conducted to the input EXOR element (1). The required residual value formed is picked up once in the one PROM area (3) and once at the delay flip flop (5). <IMAGE>

Description

Arrangement for generating cyclically coded information.

The invention relates to an arrangement for generating cyclically coded Information that is transmitted in blocks and for which a residual value is formed he follows. The arrangement is used for the transmission of secured data.

Error detection plays a role in the transmission of digital information and error correction play a crucial role.

Since a high level of security is required during transmission, the Interference suppression a corresponding coding of the useful information with additional Control and correction options required.

Simple disturbances (e.g. bit errors) are often caused by m-out-of-n codes to recognize. The parity check is used for a purely binary transmission used very often.

A better transmission security is achieved by adding more redundant bits to the actual message achieved. To this Purpose, the information is transferred into a representation that also has certain Certification mark includes. The check characters are intended to facilitate recognition when the message is received and possibly correct the introduced errors.

Higher error protection measures are more cyclical through the use Codes given. These are special parity check codes that use a polynomial notation To be defined. With this CRC procedure (Cyclic Redundancy Check), a transmission block Supplemented on the transmission side by redundant check bits that follow very specific rules can be derived from the transmission block. With the help of those familiar from mathematics Any binary information sequence can be expressed using a polynomial representation. You get thereby a test information from the division of the message polynomial by what is known as a polynomial Generator polynomial. If there is a remainder in this division, were in the transfer Faults occurred, causing individual bits to be changed.

When sending, therefore, the message part with a check character is like this adds that the total expression can be divided without remainder by the generator polynomial. Upon receipt, the total expression is then again divided by the generator polynomial, so that if the result is rust-free, the transmission is considered to be undisturbed.

Since the processing of code words by means of polynomial operations in terms of circuitry is very simple, switching elements can be used, the division or multiplication carry out. Circuits are known (Electronics 1976, Issue 8, page 55 bis 59), which consist of feedback shift registers. These stages are partial Logically linked via gates (via exclusive OR elements). Here are the Check bits delayed compared to the message bits.

The object of the invention is to find a circuit arrangement the simple way of calculating the residual value for a transmitted according to the CRC method Information.

In this way, it can be checked on the receiving side whether the telegram was transmitted without interference.

According to the invention this is achieved in that the to be transferred Information byte serial at which one input of an eight-fold Ex-OR element is pending, that the Ex-OR element is followed by an eight-fold D flip-flop, that the D flip-flop two PROM areas with eight inputs each are assigned. that the PROM area another D flip-flop with eight inputs is connected downstream for the time delay, that the time-delayed outputs of the D flip-flop and the outputs of a PROM area are led to another eight-fold Ex-OR element and are linked here, that the output of the further eight-fold Ex-OR element with the input of the first eightfold Ex-OR element is connected and with the next byte of the Information is linked and that at the end of the transfer the residual value at the output of the one PROM area and the delay D flip-flop is pending.

In addition to the universal one, an advantage of the arrangement according to the invention Use in particular the byte serial processing of the transmission blocks and the optional Programming of generator polynomials. Because the arrangement is advantageous through microprocessors can be controlled (as a peripheral circuit) by simply increasing the write cycle the D flip-flops, the speed of operation can be slowed down or increased. Of the Microprocessor is also relieved by this type of connection, it can be used for additional other tasks ben can be used.

An embodiment of the invention is described below with reference to FIG Drawing explained in more detail.

Data pending byte serial are transferred to an exclusive-OR element via a bus system 1 (Ex-OR). So there are eight bits at the same time on the one (eightfold) Input of the Ex-OR element 1 guided and linked. The Ex-OR element is a D flip-flop 2 downstream, which also has an eight-fold input. The C entrance of the flip-flop causes the zero state to prevail at the beginning of processing. Above the clock input of the flip-flop becomes the speed for the block-by-block input the data is set. With each clock pulse comes from the input via the Ex-OR - "'ied 1 a new data block and is stored in the flip-flop, i.e. the eight memory locations are taken up by the data block.

The D flip-flop 2 is followed by a PROM memory consisting of two PROM areas 3 and 4 controlled in parallel. So it will be eightfold output data simultaneously to the two PROM areas 3 and 4 with their eightfold Given inputs.

Fixed information (tables) is provided in PROM areas 3 and 4 entered, after which the incoming data is linked. In these PROM areas are thus based on a mathematical function through tables stored in the memory the incoming data blocks changed. The output of the PROM area 4 is additional still led to another eight-fold D flip-flop 5. There is a delay here of the incoming data block by one clock period. The output of this flip-flop 5 is just like the output of the PROM area ches 3 to eight times Ex-OR element 6 out, so that here a normal and a delayed by one clock Data block is pending. After linking these two data blocks, the result is to the second (eight-fold) input of the Ex-OR element 1 and here with the linked to the next data block.

At the output of the D flip-flop 5 and the PROM area 3 are each data blocks delayed by one clock period, which represent the residual value. With this residual value, which is attached to the actual information as a test character and which is formed on the sender side, the telegram transmission must be secured, i.e. a telegram can be formed whose polynomial is defined by a certain fixed polynomial value is divisible without remainder. In a receiving point not shown, which is constructed similarly to the arrangement shown above, it is checked whether the received telegram can also be divided completely by a fixed value. if If this is the case, the entire information transfer is deemed to be correct.

Claims (1)

Request for an arrangement for the generation of cyclically coded information, which are transferred in blocks, and in which a residual value is formed, thereby It recognizes that the information to be transmitted is byte serial at the one input an eightfold Ex-OR element (1) is due that the Ex-OR element (1) an eightfold D-flip-flop (2) is connected downstream that the D-flip-flop (2) has two PROM areas (3, 4) each with eight inputs that are assigned to the PROM area (4) for the time delay a D flip-flop (5) with eight inputs is connected downstream that the time-delayed Outputs of the D flip-flop (5) and the outputs of the PROM area (3) to an eightfold Ex-OR element (6) are performed and linked here that the outputs of eight times Ex-OR element (6) connected to the other inputs of the eight-fold Ex-OR element (1) and are linked with the next byte of the information to be transmitted and that at the end of the transfer the residual value at the output of the PROM area (3) and D flip-flop (5) is present.