DE2353097A1 - Reproduction of television picture - involves read out of narrow frequency band picture at multiple of original scanning speed - Google Patents

Abstract

The video signal is stored and repeatedly read out from the store and reproduced. The picture is taken and reproduced at the same frame frequency; video signals obtained by line scanning at a lower frequency are stored and read out at a frequency an integral multiple of the original; it is reproduced a number of times corresponding to the ratio of the reproduction to taking frequency; two stores are provided, in which a line video signals are stored; the scanned line signals are written in one store, while the preceding line, stored in the other store, is read out.

Description

Method and arrangement for recording a television picture with a low bandwidth of the video signal and for flicker-free playback

The invention relates to a method for receiving a TV picture with a small bandwidth of the video signal and for flicker-free playback, in which the recorded video signal is stored and from the memory is read out and played back several times.

Such methods, which are known from the publication "The Image Instruments Electrostore "from Image-Instruments Inc. are known, are used, for example, to generate the video signals a television camera to transmit narrowband and then to be able to reproduce in a certain television standard. Similar ones are also used to convert standards for television signals Procedure.

The present invention is based on the object a method for recording a television picture with a smaller bandwidth of the video signal and for flicker-free Reproduction of this image as well as an arrangement for carrying out this process to create that stand out through Characteristic for simplicity and operational reliability.

According to the invention this object is achieved in that the picture was recorded and played back at the same frame rate and that the video signal obtained by scanning a line at a low line frequency is stored and then read out from the memory and marked with an integer multiple higher

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line frequency is played back as many times as the recording line frequency is included in the display line frequency.

The frame rate is therefore when recording and Play the same. The reduction in bandwidth is achieved by lowering the line frequency. Appropriate is to make the line frequency equal to an integer fraction of the display line frequency during recording choose, because then the memory has such a capacity that it contains the information contained in a line can be saved. The memory contents are then matched at one of the display line frequencies Output speed, i.e. with a flow of information that is opposite to the flow of information when writing is increased by the factor by which the display line frequency is also increased higher than the recording line rate.

So that there is no interruption in playback, contains an arrangement for carrying out the new method two memories that work in alternating buffer mode, i.e. while the recorded video signal is stored in one of them is written, the previously recorded video signal is read from the other. The content of the second memory is output repeatedly, namely as often as the recording line frequency in the playback line frequency is included. Several lines with the same picture content are written one below the other.

The memories are advantageous digital memories, which are preceded by an analog-to-digital converter and a digital-to-analog converter is downstream. The switching device is arranged between the converters and the stores, see above that the converters work in conjunction with both memories.

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The recorded video signals are encrypted and stored with a clock frequency that is equal to or greater than the product of the recording line frequency and the number of picture points per line is. The clock frequency at which the video signals read out from the memory and converted into analog signals is higher, namely by the ratio of Playback to "recording line rate.

Based on the drawing in which an exemplary embodiment is shown is, the invention and further advantages and additions are described in more detail below and explained.

With the arrangement according to Figure 1, this should be done by a camera; KA recorded image on the screen of a viewing device SG, which according to a conventional television standard, e.g. the CCIR standard works to be reproduced. The output signal the camera should 'have a lower bandwidth than that required for video signals according to the television standard is. For this purpose, the camera KA with a "lower Line frequency operated as the display device SG. The line sync pulses are supplied by a clock generator TG. in the Embodiment is the ratio of the "line fre- ' sequences 1: 2. The image or vertical deflection frequencies are the same.

The output signals from the camera KA are sent to an analog-digital converter ADC, which periodically encodes the input signals into digital signals * Every digital signal corresponds to one pixel. The encryption time • of the analog-to-digital converter must therefore not be longer than this how the camera video signals of two pixels still to be resolved are temporally apart. In principle it can any type of analog-to-digital converter can be used, as long as it encrypts quickly enough.

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The output signal of the analog-to-digital converter is sent via several parallel lines, each with one point of the digital value is transmitted to a multiple switch S1, which in the position shown the digital values to a memory SP1. This consists of several shift registers connected in parallel, the number of which is the same the number of digits of the digital value and thus equal to the number of output lines of the analog-digital converter is. The memory SP1 receives the shift clock pulses from the clock generator TG, at whose output A1 shift clock pulses lower frequency and at its output A2 pulses higher frequency occur. The lower frequency is equal to the product of the line frequency of the camera and the number of pixels per line, i.e. the time interval between two pulses is equal to the time interval between the video signals of two pixels still to be resolved. Accordingly, the higher frequency is equal to the product of the Line frequency of the display device and the number of pixels per line. Accordingly, it becomes the digital values of the pixels successively taken over by the analog-digital converter in the memory SP1. The memory SP1 has such a capacity, that he can save all pixels of a line. Does the analog-to-digital converter need ADU for its operation Clock pulses, these can be sent to him from the output A1 of the clock generator TG- must be fed so that it can receive the camera video signals encrypted with the desired resolution.

If the memory SP1 is full, that is after scanning a line, all of them are controlled by the clock generator TG Switches S1, S2 ... S6 switched. The output signals of the analog-to-digital converter ADU then reach a memory SP2, which in the same way as the memory SP1 This memory SP2 now receives the output A1 of the clock generator TG via the switch S3.

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emerging pulses of lower frequency than shift clock pulses. The higher frequency pulses are sent from output A2 via switch S4 as shift clock pulses Memory SP1 supplied. Since switch S5 was closed at the same time, the digital values circulate in memory SP1. At the same time, they are activated via switch S2 fed to a digital-to-analog converter DAU, which controls the display device SG. The implementation must be so fast that every digital value output from the memory SP1 is detected. Since the frequency occurring at the output A2 of the clock generator TG is reduced by the ratio of the line frequency in the display device The digital-to-analog converter must be used to increase the line frequency in the camera DAU work faster than the analog-digital converter ADU by the same factor. Is the line frequency of the viewing device is twice as large as that of the camera, so the digital values from the memories are in each case issued twice, revolving at least once. So while a line is being written into one memory, the other is being written at twice the speed read out. The diagrams shown in FIG. 2 result for the television signals, of which diagram a shows the output signal from camera KA and diagram b represents the output signal of the digital-to-analog converter DAU.

If the camera has scanned the next line, it is Memory SP2 filled, all switches switch back to the position shown, so that now again in the memory SP1 is written, the digital values circulate in the memory SP2 via the switch S6 and via the Switch S2 are output, the memory SP1 via the Switch S3 with the clock frequencies of the lower frequency and the memory SP2 is controlled via the switch S4 with the clock pulses of a higher frequency. The described The cycle is repeated after each scanned by the camera KA Line; the switches S1 ... S6 can be activated with the line sync pulse for the camera can be controlled.

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Claims (5)

- 6 - VPA 9/364/3507 patent claims 1 / Method for recording a television picture with a . low bandwidth of the video signal and for flicker-free playback in which the recorded video signal is stored and read out and played back several times from a memory, characterized in that that the image is recorded and reproduced with the same frame rate and that when scanning a Line with low line frequency obtained video signal stored and then read out from the memory and with a line frequency that is an integral multiple higher than the number of times the recording line frequency in the playback line frequency is included. 2. Arrangement for performing the method according to claim 1, characterized in that two memories (SP1, SP2) are provided, in each of which the video signals of a line can be stored and those with a Switching device (TG-, S1 ... S6) are connected, via which the video signals of the respectively scanned line are written into one memory (SP1 or SP2), while the video signals of the previously scanned line contained in the other memory (SP2 or SP1) are included the display line frequency are output to a display device. 3. Arrangement according to claim 2, characterized in that the memories (SP1, SP2) are digital memories, which have an analog-to-digital converter (ADC) upstream and a digital-to-analog converter (DAU) downstream. 4. Arrangement according to claim 3, characterized in that the recorded video signals with a clock frequency encrypted and stored that - 7- 509817/0652 '■ - 7 -; VPA 9/364/3507 equal to or greater than the product of the recording line frequency and number of pixels per line and with a utn -the ratio of playback to recording frame rate higher clock frequency and read out in analog signals implemented. 5. Arrangement according to claim 4, characterized in that the memories (SP1, SP2) are shift registers that the Switching device (TG, S3, S4) the shift register, into which video signals are written, the lower clock frequency than the shift clock frequency and the shift register, from which the video signals are read, supplies the higher • clock frequency than shift clock frequency, 5098 17/0652 Blank page