DE19882312T1 - Selbstkonfigurierende 1,8- und 3,0-V-Schnittstellenarchitektur an Flash-Speichern - Google Patents

Selbstkonfigurierende 1,8- und 3,0-V-Schnittstellenarchitektur an Flash-Speichern

Info

Publication number: DE19882312T1
Authority: DE; Germany
Prior art keywords: configuring; self; flash memories; interface architecture; architecture
Prior art date: 1997-04-11
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Granted

Application number

DE19882312T

Other languages

English (en)

Other versions

DE19882312B4 (de

Inventor

Robert E Larsen

Harry Q Pon

Sanjay Talreja

Marcus E Landgraf

Ranjeet Alexis

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Micron Technology Inc

Original Assignee

Intel Corp

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1997-04-11

Filing date

1998-04-06

Publication date

2000-03-23

1998-04-06 Application filed by Intel Corp filed Critical Intel Corp

2000-03-23 Publication of DE19882312T1 publication Critical patent/DE19882312T1/de

2010-07-22 Application granted granted Critical

2010-07-22 Publication of DE19882312B4 publication Critical patent/DE19882312B4/de

2018-04-07 Anticipated expiration legal-status Critical

Status Expired - Fee Related legal-status Critical Current

Links

Classifications

- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018585—Coupling arrangements; Interface arrangements using field effect transistors only programmable

Landscapes

Engineering & Computer Science (AREA)
Computer Hardware Design (AREA)
Physics & Mathematics (AREA)
Computing Systems (AREA)
General Engineering & Computer Science (AREA)
Mathematical Physics (AREA)
Power Engineering (AREA)
Logic Circuits (AREA)

DE19882312T 1997-04-11 1998-04-06 Nicht-flüchtiger Speicher mit einer selbstkonfigurierenden 1,8- und 3,0-V-Schnittstellenarchitektur Expired - Fee Related DE19882312B4 (de)

Applications Claiming Priority (3)

Application Number	Priority Date	Filing Date	Title
US08/834,026 US5933026A (en)	1997-04-11	1997-04-11	Self-configuring interface architecture on flash memories
US08/834,026		1997-04-11
PCT/US1998/006847 WO1998047229A1 (en)	1997-04-11	1998-04-06	Self-configuring 1.8 and 3.0 volt interface architecture on flash memories

Publications (2)

Publication Number	Publication Date
DE19882312T1 true DE19882312T1 (de)	2000-03-23
DE19882312B4 DE19882312B4 (de)	2010-07-22

Family

ID=25265912

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
DE19882312T Expired - Fee Related DE19882312B4 (de)	1997-04-11	1998-04-06	Nicht-flüchtiger Speicher mit einer selbstkonfigurierenden 1,8- und 3,0-V-Schnittstellenarchitektur

Country Status (5)

Country	Link
US (1)	US5933026A (de)
KR (1)	KR100387338B1 (de)
AU (1)	AU6888098A (de)
DE (1)	DE19882312B4 (de)
WO (1)	WO1998047229A1 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US6628552B1 (en) *	1997-04-11	2003-09-30	Intel Corporation	Self-configuring input buffer on flash memories
JP3714969B2 (ja) *	1998-03-02	2005-11-09	レクサー・メディア・インコーポレイテッド	改良されたオペレーティングモード検出機能を備えたフラッシュメモリーカード及びユーザフレンドリなインターフェーシングシステム
US6182162B1 (en) *	1998-03-02	2001-01-30	Lexar Media, Inc.	Externally coupled compact flash memory card that configures itself one of a plurality of appropriate operating protocol modes of a host computer
US6157204A (en)	1998-08-05	2000-12-05	Micron Technology, Inc.	Buffer with adjustable slew rate and a method of providing an adjustable slew rate
US6901457B1 (en)	1998-11-04	2005-05-31	Sandisk Corporation	Multiple mode communications system
JP3423243B2 (ja) *	1999-03-26	2003-07-07	三洋電機株式会社	デジタルカメラ
US6467088B1 (en) *	1999-06-30	2002-10-15	Koninklijke Philips Electronics N.V.	Reconfiguration manager for controlling upgrades of electronic devices
US6628142B1 (en) *	2000-08-30	2003-09-30	Micron Technology, Inc.	Enhanced protection for input buffers of low-voltage flash memories
US6323687B1 (en)	2000-11-03	2001-11-27	Fujitsu Limited	Output drivers for integrated-circuit chips with VCCQ supply compensation
WO2003034592A1 (en) *	2001-10-17	2003-04-24	Optillion Ab	Adaptive level binary logic
DE50102690D1 (de) *	2001-10-18	2004-07-29	Pari Gmbh	Inhalationstherapievorrichtung
JP3927788B2 (ja) *	2001-11-01	2007-06-13	株式会社ルネサステクノロジ	半導体装置
US7199603B2 (en) *	2004-07-30	2007-04-03	Microchip Technology Incorporated	Increment/decrement, chip select and selectable write to non-volatile memory using a two signal control protocol for an integrated circuit device
US8143936B2 (en) *	2008-09-12	2012-03-27	Intel Mobile Communications GmbH	Application of control signal and forward body-bias signal to an active device
DE102009041512B4 (de) *	2008-09-12	2014-02-13	Infineon Technologies Ag	Vorspannen eines Transistors außerhalb eines Versorgungsspannungsbereiches
US8549257B2 (en) *	2011-01-10	2013-10-01	Arm Limited	Area efficient arrangement of interface devices within an integrated circuit
US20150048875A1 (en) *	2013-08-19	2015-02-19	Ememory Technology Inc.	High voltage power control system

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
CH625932B (fr) *	1979-05-31		Ebauches Electroniques Sa	Circuit integre apte a reagir a la presence et a la nature d'un circuit recepteur exterieur.
US4617479B1 (en) *	1984-05-03	1993-09-21	Altera Semiconductor Corp.	Programmable logic array device using eprom technology
US4774421A (en) *	1984-05-03	1988-09-27	Altera Corporation	Programmable logic array device using EPROM technology
US5283762A (en) *	1990-05-09	1994-02-01	Mitsubishi Denki Kabushiki Kaisha	Semiconductor device containing voltage converting circuit and operating method thereof
JP2758259B2 (ja) *	1990-09-27	1998-05-28	株式会社東芝	バッファ回路
US5223751A (en) *	1991-10-29	1993-06-29	Vlsi Technology, Inc.	Logic level shifter for 3 volt cmos to 5 volt cmos or ttl
US5298807A (en) *	1991-12-23	1994-03-29	Intel Corporation	Buffer circuitry for transferring signals from TTL circuitry to dual range CMOS circuitry
JP2766920B2 (ja) *	1992-01-07	1998-06-18	三菱電機株式会社	Ｉｃパッケージ及びその実装方法
JPH06209252A (ja) *	1992-09-29	1994-07-26	Siemens Ag	Ｃｍｏｓ入力段
KR0130037B1 (ko) *	1993-12-18	1998-04-06	김광호	동작전압의 변동에 대응 가능한 반도체집적회로의 입력버퍼회로
US5534801A (en) *	1994-01-24	1996-07-09	Advanced Micro Devices, Inc.	Apparatus and method for automatic sense and establishment of 5V and 3.3V operation
JP3410547B2 (ja) *	1994-05-24	2003-05-26	三菱電機株式会社	半導体装置の出力回路
US5477172A (en) *	1994-12-12	1995-12-19	Advanced Micro Devices, Inc.	Configurable input buffer dependent on supply voltage
US5528172A (en) *	1994-12-27	1996-06-18	Honeywell Inc.	Adjustable voltage level shifter
US5568062A (en) *	1995-07-14	1996-10-22	Kaplinsky; Cecil H.	Low noise tri-state output buffer

1997
- 1997-04-11 US US08/834,026 patent/US5933026A/en not_active Expired - Lifetime
1998
- 1998-04-06 AU AU68880/98A patent/AU6888098A/en not_active Abandoned
- 1998-04-06 KR KR10-1999-7009316A patent/KR100387338B1/ko not_active IP Right Cessation
- 1998-04-06 DE DE19882312T patent/DE19882312B4/de not_active Expired - Fee Related
- 1998-04-06 WO PCT/US1998/006847 patent/WO1998047229A1/en not_active Application Discontinuation

Also Published As

Publication number	Publication date
AU6888098A (en)	1998-11-11
US5933026A (en)	1999-08-03
KR100387338B1 (ko)	2003-06-11
WO1998047229A1 (en)	1998-10-22
KR20010006234A (ko)	2001-01-26
DE19882312B4 (de)	2010-07-22

Legal Events

Date	Code	Title	Description
2000-03-23	OP8	Request for examination as to paragraph 44 patent law
2000-04-27	8125	Change of the main classification	Ipc: G11C 7/00
2011-01-20	8364	No opposition during term of opposition
2013-09-17	R082	Change of representative	Representative=s name: ZENZ, HELBER, HOSBACH & PARTNER, DE
2013-11-07	R081	Change of applicant/patentee	Owner name: MICRON TECHNOLOGY, INC., US Free format text: FORMER OWNER: INTEL CORPORATION, SANTA CLARA, US Effective date: 20130917 Owner name: MICRON TECHNOLOGY, INC., BOISE, US Free format text: FORMER OWNER: INTEL CORPORATION, SANTA CLARA, CALIF., US Effective date: 20130917
2013-11-07	R082	Change of representative	Representative=s name: ZENZ, HELBER, HOSBACH & PARTNER, DE Effective date: 20130917
2016-11-01	R119	Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee

Publication	Publication Date	Title
DE69811066D1 (de)	2003-03-06	Datenzusammenfassungsgerät.
TR199800815A3 (tr)	1998-11-23	Sülfonilaminokarbonasitler.
IS4963A (is)	1999-01-29	Setnar 6,5-heteró-bísýklískar afleiður
DE19882312T1 (de)	2000-03-23	Selbstkonfigurierende 1,8- und 3,0-V-Schnittstellenarchitektur an Flash-Speichern
DK1015467T3 (da)	2004-05-03	6,9-brobundne erythromycinderivater
ID23427A (id)	2000-04-20	Organisasi memori komputer
IT1295221B1 (it)	1999-05-04	Dispositivo gommatore.
MA24551A1 (fr)	1998-12-31	W.c.
TR199600656A2 (tr)	1997-03-21	Piperidinilmetiloksazolidinonlar.
IT246285Y1 (it)	2002-04-08	Cerniera.
TR199700219A3 (tr)	1997-10-21	1,25-Dihidroksi-16, 22, 23-Trisdihidro-kolkalsiferol türevleri.
ES1036909Y (es)	1998-05-01	Pupitre infantil.
IT1294675B1 (it)	1999-04-12	Scafo veloce modulare multiplo.
ES1038670Y (es)	1999-01-01	Embarcacion.
ES1037395Y (es)	1998-07-01	Tendedero antilluvia.
IT1291240B1 (it)	1998-12-30	Dispositivo gommatore.
ES1037777Y (es)	1998-11-01	Libreta.
BR9700155B1 (pt)	2011-10-18	plugue.
ES1038970Y (es)	1999-03-01	Secador portatil.
IT242355Y1 (it)	2001-06-14	Radiatore.
ES1038457Y (es)	1999-01-01	Radiador perfeccionado.
ES1036440Y (es)	1998-01-01	Yoyo perfeccionado.
ES1036787Y (es)	1998-04-01	Carterita-neceser.
ES1037763Y (es)	1998-11-01	Iluminaria.
ES1037954Y (es)	1998-11-01	Cotilo semiexpansivo.