DE19848298A1 - Large diameter, high temperature stable, single crystal semiconductor substrate wafer, for IC production, has an anti-stress layer outside the active region to counteract gravity-induced forces - Google Patents

Large diameter, high temperature stable, single crystal semiconductor substrate wafer, for IC production, has an anti-stress layer outside the active region to counteract gravity-induced forces

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DE19848298A1
DE19848298A1 DE19848298A DE19848298A DE19848298A1 DE 19848298 A1 DE19848298 A1 DE 19848298A1 DE 19848298 A DE19848298 A DE 19848298A DE 19848298 A DE19848298 A DE 19848298A DE 19848298 A1 DE19848298 A1 DE 19848298A1
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layer
silicon
semiconductor substrate
bulk material
substrate wafer
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DE19848298A
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DE19848298B4 (en
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Frank Hollaender
Dieter Knoll
Beate Kuck
Armin Fischer
Hans Richter
Bernd Tillack
Joerg Osten
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IHP GmbH
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Institut fur Halbleiterphysik Frankfurt (Oder) GmbH
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Priority to PCT/DE1999/003071 priority patent/WO2000022205A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02579—P-type
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02269—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by thermal evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition

Abstract

A large diameter, high temperature stable, single crystal semiconductor substrate wafer (1) has an anti-stress layer (3) outside the active region to counteract gravity-induced forces. A single crystal semiconductor substrate wafer, of \- 200 mm diameter, has one or more single crystal and/or amorphous anti-stress layers (3) which counteract mechanical forces acting on the bulk material during a high temperature process during device production, layer(s) arranged outside the active regions and dimensioned according to gravity-induced compressive, bending and friction forces resulting from the bulk material and the horizontal lay-out scheme in batch or single wafer processing. An Independent claim is also included for production of the above wafer. Preferred Features: The anti-stress layer is a buried silicon-germanium layer or a back face silicon nitride layer.

Description

Die Erfindung betrifft eine hochtemperaturstabile Halbleitersubstratscheibe großen Durchmessers gemäß Oberbegriff des Patentanspruchs 1 zur Herstellung von monolithischen elektronischen Bauelementen in Batch- oder Einscheibenprozessen wie Tempern, Diffusion, Oxidation und chemische Dampfphasenabscheidung (CVD) und ein Verfahren zur Herstellung derartiger Halbleiteisubstratscheiben.The invention relates to a high temperature stable semiconductor substrate wafer Diameter according to the preamble of claim 1 for the production of monolithic electronic components in batch or single-disc processes such as tempering, diffusion, Oxidation and chemical vapor deposition (CVD) and a process for Manufacture of such semiconductor ice wafer.

Einkristalline Siliziumwafer sind vorzugsweise das Ausgangsmaterial für die Herstellung integrierter Schaltkreise. Mit der Entwicklung neuer Fertigungstechnologien und neuer Schaltkreise geht aus ökonomischen Gründen der Übergang zu immer größeren Waferdurchmessern einher. Dies erfolgt aus Gründen einer höheren Effektivität der Bearbeitungsprozesse und zunehmender Integrationsgrade der Schaltkreise. Dabei strebt die Industrie neben einer maximalen Schaltkreisausbeute auch ein optimales Verhältnis zwischen dem Durchmesser und der Dicke der Wafer an. So hat eine geringfügige Änderung der Dicke eines großflächigen Wafers als Mittel zur Erhöhung seiner mechanischen Stabilität einen wesentlichen Einfluß auf die Anzahl der Wafer, die aus dem Einkristall gewonnen werden können, und damit auf die Kosten. So bewirkt allein der Materialeinsatz pro Wafer beim Übergang von 200 mm Durchmesser und 0,725 mm Dicke auf 300 mm Durchmesser und 0,775 mm Dicke einen Kostenanstieg um mehr als das Vierfache. Deshalb muß sich die Handhabung solcher Wafer in Apparaturen und während technologischer Prozesse von der bisher üblichen erheblich unterscheiden.Single-crystalline silicon wafers are preferably the starting material for production integrated circuits. With the development of new manufacturing technologies and new ones Circuits make the transition to bigger and bigger ones for economic reasons Wafer diameters. This is done for reasons of a higher effectiveness of the Machining processes and increasing levels of integration of the circuits. The strives In addition to maximum circuit yield, industry also an optimal ratio between the diameter and thickness of the wafers. So has a slight change in thickness a large-area wafer as a means of increasing its mechanical stability significant influence on the number of wafers obtained from the single crystal can, and therefore at the expense. The material used per wafer alone in the Transition from 200 mm diameter and 0.725 mm thickness to 300 mm diameter and 0.775 mm thickness a cost increase by more than four times. Therefore, the  Handling such wafers in equipment and during technological processes by the significantly differentiate so far.

Der Stand der Technik ist dadurch gekennzeichnet, daß Siliziumwafer während der Prozessierung in speziellen Magazinen senkrecht stehend angeordnet werden, um unter anderem den deformierenden Einfluß der Gravitationskraft zu verringern. Masse und Empfindlichkeit von Wafern großen Durchmessers erfordern dann wegen der hohen Kosten für entsprechende Prozeßanlagen und für bestimmte Waferprozesse den Übergang zur Einzel- Wafer-Handhabung.The prior art is characterized in that silicon wafers during the Processing in special magazines to be arranged vertically to under other to reduce the deforming influence of gravitational force. Mass and Large diameter wafers then require sensitivity because of the high cost for corresponding process plants and for certain wafer processes the transition to individual Wafer handling.

Mit wachsendem Durchmesser von Siliziumwafern, insbesondere bei Durchmessern ≧200 mm, geht man von einer vertikalen Lagerung der Wafer zu einer horizontalen über, und es kommt zwangsläufig und zunehmend beim Durchlaufen technologischer Prozesse unter dem Einfluß der Gravitationskraft zu einer Durchbiegung der Wafer. Das führt z. B. bei Temperprozessen zur plastischen Deformation und zur Defektbildung in den Wafern, wodurch sich Ausbeute und Qualität von Bauelementen und Schaltkreisen verringern. Aber auch Hochtemperaturprozeßparameter, wie die Oxidationsgeschwindigkeit und das Diffusionsverhalten von Verunreinigungen können durch mechanische Spannungen beeinflußt werden. Ursachen dafür sind zum einen transiente Temperaturinhomogenitäten über der Scheibe während des Aufheizens auf Prozeßtemperatur und Abkühlens von dieser (Ramping) bzw. das Eigengewicht der Scheibe bei horizontaler Auflage im Batch- oder Einscheibenprozeß. Während durch geeignete Einstellung der Ramping-Raten, wie beispielsweise in DD 285 663 AS vorgeschlagen, die Ausbildung von großen, zur Verformung führenden Temperaturgradienten unterdrückt werden kann, ist gegenwärtig kein geeignetes Mittel zur Beherrschung der gravitationsinduzierten Spannungen bekannt. Modifikationen am Scheibensupportdesign des Quarz- oder Siliziumkarbidbootes, wie Erhöhung der Anzahl der Auflagepunkte von drei auf vier oder deren symmetrische Anordnung in verschiedenen radialen Abständen vom Scheibenzentrum, führen nicht zum entsprechenden Erfolg. Insbesondere gilt dies für den Bereich hoher Prozeßtemperaturen von mehr als 900°C.As the diameter of silicon wafers increases, especially with diameters ≧ 200 mm, one goes from a vertical storage of the wafers to a horizontal one, and it inevitably and increasingly comes down to going through technological processes the influence of the gravitational force for a deflection of the wafers. That leads z. B. at Annealing processes for plastic deformation and defect formation in the wafers, which reduces the yield and quality of components and circuits. But also high temperature process parameters such as the oxidation rate and that Diffusion behavior of contaminants can be influenced by mechanical stresses become. The reasons for this are on the one hand transient temperature inhomogeneities above the Disc during heating to process temperature and cooling from it (ramping) or the dead weight of the disc with horizontal support in batch or Single disc process. While by appropriately setting the ramping rates like for example in DD 285 663 AS proposed the training of large, for Deformation leading temperature gradients can currently be suppressed suitable means for controlling the gravitationally induced tensions. Modifications to the disk support design of the quartz or silicon carbide boat, such as  Increase the number of support points from three to four or their symmetrical Arrangement at different radial distances from the center of the disk does not lead to corresponding success. This applies in particular to the area of high process temperatures of more than 900 ° C.

Der Erfindung liegt dabei die Aufgabe zugrunde, eine einkristalline Halbleitersubstratscheibe großen Durchmessers bevorzugt aus Silizium zu schaffen, die einerseits den an moderne Halbleiterbauelemente und ihren Herstellungsprozeß gestellten Anforderungen gerecht wird und andererseits die Aasbildung von entsprechend den aus Bulkmaterialmasse und dem horizontalen Auflageschema in Batch- oder Einscheibenprozessen resultierenden gravitationsinduzierten Druck-, Biege- und Reibkräften unterdrückt und damit eine plastische Scheibenverformung unter Wirkung solcher Kräfte bei der Hochtemperaturbearbeitung im Bauelementeprozeß vermeiden hilft.The invention is based on the object of a single-crystalline semiconductor substrate wafer Large diameter preferred to create silicon, which on the one hand the modern Semiconductor components and their manufacturing process requirements and on the other hand the formation of carrion corresponding to that of bulk material mass and horizontal lay-up scheme resulting in batch or single disc processes suppresses gravitational pressure, bending and frictional forces and thus a plastic one Disc deformation under the action of such forces in high temperature machining in Avoiding component process helps.

Diese Aufgabe wird durch eine hochtemperaturstabile Halbleitersubstratscheibe, bestehend aus konventionellem Bulk- oder Epitaxiewafermaterial und mehreren jedoch mindestens einer Anti-Streß-Schicht, erfindungsgemäß dadurch gelöst, daß die aus der Wafermasse und dem Supportdesign resultierenden gravitationsinduzierten Spannungen in der Halbleitersubstratscheibe mittels filminduzierter Spannungen kompensiert werden, die durch eine oder mehrere einkristalline vergrabene Silizium-Germanium-Schichten oder eine Substratrückseiten-Siliziumnitridschicht oder beides außerhalb des eigentlichen, die Halbleiterbauelemente tragenden aktiven Halbleitermaterialbereiches in an und für sich bekannter Weise mittels chemischer Gasphasenabscheidung oder Molekularstrahlepitaxie eingebracht und entsprechend den wirkenden Gravitationsspannungen dimensioniert werden. This task is accomplished by a high-temperature stable semiconductor substrate wafer of conventional bulk or epitaxial wafer material and several, but at least one Anti-stress layer, according to the invention solved in that the wafer mass and the Support design resulting in gravitational stresses in the Semiconductor substrate wafer can be compensated for by film-induced voltages one or more single-crystal buried silicon germanium layers or one Backside silicon nitride layer or both outside of the actual, the Active semiconductor material area carrying semiconductor components in and of itself known manner by means of chemical vapor deposition or molecular beam epitaxy introduced and dimensioned according to the acting gravitational stresses.  

Gleichzeitig unterstützt die dem bauelementeaktiven Bereich nahe gelegene Silizium- Germanium-Schicht und/oder die Substratrückseiten-Siliziumnitridschicht das Gettern von Schwermetallen aus diesem Bereich und dient damit zusätzlich der Verbesserung der Qualitätsparameter der hochtemperaturstabilen Halbleitersubstratscheibe. Schließlich bildet die harte Siliziumnitridschicht einen wirksamen Schutz gegen die lokale Versetzungsentstehung infolge des prozeßbedingten Zerkratzens der Substratscheibe im Bereich der Scheibenauflagepunkte.At the same time, the silicon close to the device-active area supports Germanium layer and / or the substrate backside silicon nitride layer the gettering of Heavy metals from this area and thus also serves to improve the Quality parameters of the high temperature stable semiconductor substrate wafer. Finally forms the hard silicon nitride layer provides effective protection against the local Dislocation formation due to the process-related scratching of the substrate wafer in the Area of the disc support points.

Die Merkmale der Erfindung gehen außer aus den Ansprüchen auch aus der Beschreibung und den Zeichnungen hervor, wobei die einzelnen Merkmale jeweils für sich allein oder zu mehreren in Form von Unterkombinationen schutzfähige Ausführungen darstellen, für die hier Schutz beansprucht wird. Ausführungsbeispiele der Erfindung sind in den Zeichnungen dargestellt und werden im folgenden näher erläutert.The features of the invention go beyond the claims also from the description and the drawings, the individual features each individually or to represent several protective designs in the form of sub-combinations, for the here Protection is claimed. Embodiments of the invention are in the drawings shown and are explained in more detail below.

Die Zeichnungen zeigenThe drawings show

Fig. 1 Halbleitersubstratscheibe mit Anti-Streß-Schicht aus Silizium-Germanium Fig. 1 semiconductor substrate wafer with anti-stress layer made of silicon germanium

Fig. 2 Halbleitersubstratscheibe mit Anti-Streß-Schicht aus Siliziumnitrid Fig. 2 semiconductor substrate wafer with anti-stress layer made of silicon nitride

Beispiel 1example 1

Auf eine 300 mm (001)-Halbleitersubstratscheibe 1 vom Typ p++-Silizium mit einem spezifischen Widerstand von 7 . . . 10 mΩ cm wird nach einer üblicherweise durchgeführten naßchemischen Reinigung eine epitaktische Schichtfolge einschließlich einer pseudomorphen Silizium-Germanium-Schicht 3 (SiGe-Schicht) aufgebracht. Vorzugsweise wird für die Epitaxie CVD genutzt. Die Erzeugung der epitaktischen Schichtfolge beginnt mit einer Temperung unter Wasserstoff zur Entfernung des natürlichen Siliziumdioxids von der Substratoberfläche. Danach wird eine dünne Silizium-Epitaxieschicht 2 als Pufferschicht abgeschieden. Ihre Dicke beträgt 10 bis 100 nm, als typisch sind 50 nm zu wählen. Anschließend erfolgt die Abscheidung der SiGe-Schicht 3. Als Quellgas für die Herstellung der SiGe-Schicht 3 wird ein entsprechendes Gemisch aus Silan (SiH4) und German (GeH4) verwendet. Die Abscheidung erfolgt bei Temperaturen zwischen 450 und 800°C, typisch sind 550°C. Die Ge-Konzentration in der SiGe-Schicht 3 beträgt 3 . . . 30%. Für einen Wert von 20% wird eine Schichtdicke von 30 . . . 40 nm eingestellt. Nach Abscheidung der SiGe-Schicht 3 wird das Quellgas für Ge abgeschaltetet und eine 1 . . . 3 µm dicke Bor-dotierte Si- Epitaxieschicht 4 mit einem spezifischen Widerstand von 8 . . . 12 Ω cm aufgewachsen. Als Quellgas dient hierzu ein Gemisch aus Silan und Diboran (B2H6).On a 300 mm (001) semiconductor substrate wafer 1 of the p ++ silicon type with a specific resistance of 7. . . 10 mΩ cm, an epitaxial layer sequence including a pseudomorphic silicon-germanium layer 3 (SiGe layer) is applied after a wet chemical cleaning that is usually carried out. CVD is preferably used for the epitaxy. The generation of the epitaxial layer sequence begins with tempering under hydrogen to remove the natural silicon dioxide from the substrate surface. A thin silicon epitaxial layer 2 is then deposited as a buffer layer. Their thickness is 10 to 100 nm, typically 50 nm should be chosen. The SiGe layer 3 is then deposited. An appropriate mixture of silane (SiH 4 ) and German (GeH 4 ) is used as the source gas for the production of the SiGe layer 3 . The separation takes place at temperatures between 450 and 800 ° C, typically 550 ° C. The Ge concentration in the SiGe layer 3 is 3. . . 30%. For a value of 20%, a layer thickness of 30. . . 40 nm set. After the SiGe layer 3 has been deposited, the source gas for Ge is switched off and a 1. . . 3 µm thick boron-doped Si epitaxial layer 4 with a specific resistance of 8. . . Grown 12 Ω cm. A mixture of silane and diborane (B 2 H 6 ) serves as the source gas.

Die erfindungsgemäß im Scheibenvorderbereich versiegelt eingebrachte Anti-Streß-Schicht, bestehend aus einer einkristallinen SiGe-Schicht 3, erzeugt im Epitaxie-Wafer eine kompressive Vorspannung von 0,25 . . . 0,3 MPa und dient der Kompensation bzw. Reduzierung der sich ausbildenden gravitativen Biegespannung im Wafer bei dessen horizontaler Lage auf dem 3-Punkt- oder 4-Punkt-Support im Boot des Einscheiben- oder Batchreaktors, um somit die Substratscheibenvergleitung unter ihrer eigenen Schwerkraft von 1,28 N im Hochtemperaturprozeß vermeiden zu helfen. Gleichzeitig unterstützt die dem bauelementeaktiven Bereich nahegelegene SiGe-Schicht 3 das Gettern von Schwermetallen aus diesem Bereich und dient damit zusätzlich der Verbesserung der Qualitätsparameter der zuletzt aufgebrachten Si-Epitaxieschicht 4. The anti-stress layer, consisting of a single-crystalline SiGe layer 3 , which is sealed in the front pane area according to the invention, produces a compressive pre-tension of 0.25 in the epitaxial wafer. . . 0.3 MPa and is used to compensate or reduce the gravitational bending stress that forms in the wafer when it is horizontally positioned on the 3-point or 4-point support in the boat of the single-disk or batch reactor, in order to allow the substrate wafer to glide under its own gravity of 1.28 N in the high temperature process. At the same time, the SiGe layer 3 close to the component-active area supports the gettering of heavy metals from this area and thus additionally serves to improve the quality parameters of the Si epitaxial layer 4 applied last.

Beispiel 2Example 2

Auf eine 200 mm (001)-Siliziumsubstratscheibe 11 mit einer entsprechend den technologischen bzw. bauelementespezifischen Anforderungen gewählten Dotierung wird nach einer üblicherweise durchgeführten naßchemischen Reinigung auf der Substratvorderseite eine Niedertemperatur-Siliziumdioxid-Schicht (SiO2-Schicht) der Dicke 50 . . . 100 nm als Schutzschicht für den späteren bauelementeaktiven Waferbereich mittels plasmachemischer Abscheidung aufgebracht. Die Abscheidung erfolgt bei Temperaturen ≦500°C, typisch sind 350°C. Als Quellgas für die Herstellung der SiO2-Schicht wird ein entsprechendes Gemisch aus Silan und Lachgas (N2O) verwendet. Anschließend erfolgt eine plasmachemische Abscheidung einer Anti-Streß-Schicht, bestehend aus einer Siliziumnitridschicht 12 (Si3N4-Schicht) auf der Substratscheibenrückseite bei Temperaturen ≦600°C, typisch sind 450°C. Als Quellgas dient hierzu ein Gemisch aus Silan und Ammoniak (NH3). Bei Bedarf kann die vorderseitige SiO2 Schicht, wie in diesem Ausführungsbeispiel letztlich durch Oxidätzen entfernt werden.A low-temperature silicon dioxide (SiO 2 ) layer with a thickness of 50 is applied to a 200 mm (001) silicon substrate wafer 11 with a doping selected in accordance with the technological or component-specific requirements after a wet-chemical cleaning that is usually carried out on the front side of the substrate. . . 100 nm applied as a protective layer for the later component-active wafer area by means of plasma chemical deposition. The separation takes place at temperatures ≦ 500 ° C, typically 350 ° C. An appropriate mixture of silane and nitrous oxide (N 2 O) is used as the source gas for the production of the SiO 2 layer. This is followed by plasma-chemical deposition of an anti-stress layer consisting of a silicon nitride layer 12 (Si 3 N 4 layer) on the back of the substrate wafer at temperatures ≦ 600 ° C, typically 450 ° C. A mixture of silane and ammonia (NH 3 ) serves as the source gas. If required, the front-side SiO 2 layer can, as in this exemplary embodiment, ultimately be removed by oxide etching.

Durch geeignete Wahl der die Plasmaabscheidung charakterisierenden Parameter, wie Plasmaanregungsfrequenz, -leistung und Biasspannung sowie Schichtdicke, lassen sich zur Kompensation der gravitativen Biegespannung in der dem späteren Hochtemperaturprozeß zu unterwerfenden einkristallinen Halbleitersubstratscheibe Vorspannungen bis zu 1 MPa einstellen. Gleichzeitig schützt die Si3N4-Schicht 12 die Substratscheibenoberfläche vor dem Zerkratzen an ihren Auflagepunkten durch Waferflattern infolge der abrupten Temperaturänderungen im Einscheiben-Rapid-Thermal-Prozeß oder beim Batchprozeß während des Einfahrens des Scheibenbootes in den auf 500-600°C vorgeheizten Reaktorraum. By suitable selection of the parameters characterizing the plasma deposition, such as plasma excitation frequency, power and bias voltage as well as layer thickness, prestresses of up to 1 MPa can be set in the single-crystal semiconductor substrate wafer to be subjected to the later high-temperature process to compensate for the gravitational bending stress. At the same time, the Si 3 N 4 layer 12 protects the substrate wafer surface from being scratched at its support points by wafer fluttering as a result of the abrupt temperature changes in the single-disc rapid thermal process or during the batch process while the wafer boat is being retracted into the reactor space preheated to 500-600 ° C .

In der vorliegenden Erfindung wurde anhand konkreter Ausführungsbeispiele eine hochtemperaturstabile Halbleitersubstratscheibe großen Durchmessers und ein Verfahren zu ihrer Herstellung erläutert. Es sei aber vermerkt, daß die vorliegende Erfindung nicht auf die Einzelheiten der Beschreibung in den Ausführungsbeispielen eingeschränkt ist, da im Rahmen der Patentansprüche Änderungen und Abwandlungen beansprucht werden.In the present invention, a high temperature stable semiconductor substrate wafer of large diameter and a method their manufacture explained. However, it should be noted that the present invention is not limited to Details of the description in the exemplary embodiments are limited, since within the scope changes and modifications are claimed.

Claims (6)

1. Hochtemperaturstabile einkristalline Halbleitersubstratscheibe bevorzugt aus Silizium und für einen Durchmesser ≧ 200 mm, bestehend aus konventionellem Bulkmaterial und mehreren jedoch mindestens einer der bei der Herstellung von Halbleiterbauelementen im Hochtemperaturprozeß sich ausbildenden mechanischen Kräften am Bulkmaterial entgegenwirkenden einkristallinen und/oder amorphen Anti- Streß-Schicht, dadurch gekennzeichnet, daß diese Schicht entsprechend den aus Bulkmaterialmasse und dem horizontalen Auflageschema in Batch- oder Einscheibenprozessen resultierenden gravitationsinduzierten Druck-, Biege- und Reibkräften dimensioniert und außerhalb des eigentlichen, die Halbleiterbauelemente tragenden aktiven Halbleitermaterialbereiches angeordnet ist.1. High-temperature stable single-crystalline semiconductor substrate wafer preferably made of silicon and for a diameter ≧ 200 mm, consisting of conventional bulk material and several but at least one of the mechanical forces on the bulk material that counteract in the manufacture of semiconductor components in the high-temperature process, counteracting single-crystal and / or amorphous anti-stress layer , characterized in that this layer is dimensioned according to the gravitationally induced pressure, bending and friction forces resulting from bulk material mass and the horizontal support scheme in batch or single-disc processes and is arranged outside the actual active semiconductor material area carrying the semiconductor components. 2. Halbleitersubstratscheibe nach Anspruch 1, dadurch gekennzeichnet, daß mehrere jedoch mindestens eine aus einem Gemisch von Silizium und Germanium bestehende Anti-Streß-Schicht pseudomorph auf das Bulkmaterial epitaktisch aufgewachsen ist, daß beim Vorhandensein mehrerer pseudomorpher Schichten diese durch einkristalline Bereiche aus substrateigenem oder diesem gleichzustellenden Material voneinander getrennt sind und daß durch einen abschließenden, zur Aufnahme der herzustellenden Halbleiterbauelemente vorgesehenen Bereich die Silizium-Germanium-Schicht (3) mit dem obengenannten Material eingesiegelt ist. 2. Semiconductor substrate wafer according to claim 1, characterized in that several, however, at least one anti-stress layer consisting of a mixture of silicon and germanium has been epitaxially grown on the bulk material in such a way that, in the presence of several pseudomorphic layers, these are formed by single-crystalline regions of substrate-like or this the same material to be provided are separated from each other and that the silicon-germanium layer ( 3 ) is sealed with the above-mentioned material by a final area provided for receiving the semiconductor components to be produced. 3. Halbleitersubstratscheibe nach Anspruch 1, dadurch gekennzeichnet, daß die Anti- Streß-Schicht aus einer auf der Bulkmaterialrückseite abgeschiedenen Siliziumnitridschicht (12) oder einer Schichtkombination aus Siliziumdioxid und Siliziumnitrid besteht.3. Semiconductor substrate wafer according to claim 1, characterized in that the anti-stress layer consists of a deposited on the bulk material backside silicon nitride layer ( 12 ) or a layer combination of silicon dioxide and silicon nitride. 4. Verfahren zur Herstellung einer Halbleitersubstratscheibe nach den Ansprüchen 1 bis 3, dadurch gekennzeichnet, daß die Anti-Streß-Schicht entsprechend den aus Bulkmaterialmasse und dem horizontalen Auflageschema in Batch- oder Einscheibenprozessen resultierenden gravitationsinduzierten Druck-, Biege- und Reibkräften dimensioniert, in einem Niedertemperaturschritt bei vorzugsweise 300°C bis 800°C mittels chemischer Gasphasenabscheidung oder Molekularstrahlepitaxie erzeugt und außerhalb des eigentlichen, die Halbleiterbauelemente tragenden aktiven Halbleitermaterialbereiches angeordnet wird.4. A method for producing a semiconductor substrate wafer according to claims 1 to 3, characterized in that the anti-stress layer according to the Bulk material mass and the horizontal support scheme in batch or Single-disc processes resulting in gravitational pressure, bending and Dimensioned friction forces, in a low temperature step at preferably 300 ° C. up to 800 ° C using chemical vapor deposition or molecular beam epitaxy generated and outside the actual, the semiconductor components carrying active Semiconductor material area is arranged. 5. Verfahren nach Anspruch 4, dadurch gekennzeichnet, daß mehrere jedoch mindestens eine aus einem Gemisch von Silizium und Germanium bestehende Anti-Streß-Schicht pseudomorph auf das Bulkmaterial epitaktisch aufgewachsen wird, daß beim Vorhandensein mehrerer pseudomorpher Schichten diese durch einkristalline Bereiche aus substrateigenem oder diesem gleichzustellenden Material voneinander getrennt werden und daß durch einen abschließenden, zur Aufnahme der herzustellenden Halbleiterbauelemente vorgesehenen Bereich die Silizium-Germanium-Schicht (3) mit dem obengenannten Material eingesiegelt wird. 5. The method according to claim 4, characterized in that several, however, at least one anti-stress layer consisting of a mixture of silicon and germanium is pseudomorphically grown epitaxially on the bulk material such that, in the presence of several pseudomorphic layers, these are formed by single-crystalline regions of substrate-like or this the same material to be provided are separated from each other and that the silicon-germanium layer ( 3 ) is sealed with the above-mentioned material by a final area provided for receiving the semiconductor components to be produced. 6. Verfahren nach Anspruch 4, dadurch gekennzeichnet, daß auf der Bulkmaterialrückseite eine Anti-Streß-Schicht, bestehend aus einer Siliziumnitridschicht (12) oder einer Schichtkombination aus Siliziumdioxid und Siliziumnitrid abgeschieden wird.6. The method according to claim 4, characterized in that an anti-stress layer consisting of a silicon nitride layer ( 12 ) or a layer combination of silicon dioxide and silicon nitride is deposited on the bulk material back.
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