DE19819405B4 - Implementation of a reversible embedded wavelet system - Google Patents

Abstract

System with:
A buffer;
A wavelet transform unit having an input connected to the buffer to perform a reversible wavelet transform on pixels stored in the buffer and to produce coefficients at an output;
An encoder connected to the wavelet transformation unit to encode bit planes of wavelet-transformed pixels from the wavelet transformation unit and bit planes of wavelet-transformed pixels stored in the buffer.

Description

The The present invention relates to the field of data compression and decompression systems; In particular, the present invention relates Invention a method and apparatus for lossless and lossy coding and decoding of data in compression / decompression systems.

The Data compression is an extremely useful tool for large amounts of data to save and transfer. For example, the time required to take a picture, such as e.g. a facsimile transmission of a Document, to transfer, drastically reduced when compression is used to the Reduce the number of bits needed to create the image.

The WO88 / 04117 A1 relates to a method for transmitting digitized sound signals, wherein for transmitting sound signals by means of Quadrature mirror filtering the sound signal through a variety of spectral Subband signals are digitized, the quantization the samples in the subbands is controlled so that the quantization noise levels of individual subband signals approximately the same distances to the listening threshold resulting from individual subband signals of human hearing have, wherein the distances the quantization noise level of the subband signals with respect to resulting listening threshold by the difference between that required for coding Overall information flow and the total information flow available for coding be determined.

The ISO / IEC11172-3: 1993, C.1.5.3 - C.1.5.4.4.8 refers to the MPEG1 audio standard, and specifically to the layer III of this audio standard, using a possible Layer III coding method which is a psychoacoustic model, a polyphase filter bank and an MDCT used.

Lots There are various data compression techniques in the state of Technology. Compression techniques can in two big ones Categories are split, lossy coding and lossless Coding. Lossy coding includes coding used for Loss of information leads so that there is no Guarantee for there is a perfect reconstruction of original data. The goal A lossy compression is that changes to the original Data is done in such a way that it does not objectionable or detectable. For lossless compression the entire information is maintained or maintained and the data is compressed in a way that is perfect Reconstruction allows.

at lossless compression becomes input symbols or intensity data converts to codewords issue. The input may contain the following data: image data, Audio data, one-dimensional data (e.g., data that is spatial or change over time), two-dimensional data (e.g., data that is in two spatial Change directions (or a spatial Dimension and a temporal dimension)), or multidimensional / multispectral Dates. If the compression succeeds, the codewords will pass through less bits represented than the number of bits that are required for the uncoded ones Input symbols (or intensity data) were necessary. Lossless coding techniques include lexical Procedure ("dictionary methods ") of coding (e.g., Lempel-Ziv), run-length coding, aufzählendes Encoding ("enumerative coding ") and entropy coding. For lossless image compression, the compression is based on predictions or contexts plus coding. The JPEG standard for facsimile compression (ISO / IEC 11544) and DPCM (Differential Pulse Code Modulation or "Differential Pulse Code Modulation "- an option in the JPEG standard (SIO / IEC 10918)) for images with continuous tint provide examples of a lossless compression of images. In the lossy Compression will be input symbols or intensity data before conversion to output codewords quantized. Quantization is meant to have relevant characteristics while maintaining the data unimportant characteristics are eliminated. Use before quantization lossy systems often a transformation to provide an energy compaction. JPEG provides an example for a lossy coding method for image data.

Recent developments in image signal processing continue to focus on the need for efficient and effective forms of data compression coding. Various forms of transformation or pyramidal signal processing have been proposed, including multi-resolution pyramidal processing and wavelet pyramidal processing. These forms are also referred to as subband processing and hierarchical processing. Wavelet pyramidal processing of image data represents a specific type of multi-resolution pyramid processing, which may use Quadrature Mirror Filters (QMFs) to produce subband decompositions of an original image. It is noteworthy that other types of non-QMF wavelets exist. For more information regarding wavelet processing, see Antonini, M., et al. "Image Coding Using Wavelet Transform", IEEE Transactions on Image Processing, Vol. 1, No. 2, April 1992; Shapiro, J. "Embedded Hierarchical Image Coding Using Zerotrees of Wavelet Coefficients," Proc. IEEE Data Compression Conference, pages 214-223, 1993. With regard to information on reversible transformations, Said, A. and Pearlman, W. "Reversible Image Compression via Multiresolution Representation and Predictive Coding", Dept. of Electrical, Computer and Systems Engineering, Renssealaer Polytechnic Institute, Troy, NY 1993.

A Compression needed often a lot of time and is memory intensive. It is desirable the compression faster and / or with a reduced memory perform, if it is possible is. Some applications have never used compression because either the quality not guaranteed could not, or the compression rate was not high enough Data rate was not controllable. However, the use of compression desirable, to the amount of information that is transmitted and / or stored.

digital Copiers, printers, scanners and multifunctional machines greatly improved with frame storage. A compressed one Frame storage reduces storage and thus costs the for frame storage is required for these products. however will save many frame stores with random stores Access (RAMs) implemented or realized. A RAM is fast but generally expensive. Hard disks can also be used as storage are and will generally be considered cheap (or generally as less expensive than the RAM). That's why it would be every system manufacturer as an advantage in creating a less expensive system watch a hard drive for the purposes such as Frame memory to use instead of a RAM.

One Problem with using hard drives for time-sensitive applications is that difficult is to access information from a hard drive so fast directly how to access the same information from a RAM. As well Many hard drives use compression when they have information Save on the disk to increase the amount of information that can be stored on the hard disk. The time necessary is to perform the compression, can also be sensitive to using hard drives when time sensitive Deter applications. Both the slow speed, the Use of hard drives inherent is, as well as the use of compression makes use of hard drives in time-sensitive applications to a difficult one Implementation topic.

The The present invention provides a fast lossy / lossless Compression ready. The present invention provides system implementations This involves the use of low-cost hard disk technology instead of an expensive RAM allowed. Next presented the present Invention a rate adjustment or a speed adjustment for one Hard drive ready and provides compression to the hard drive at bandwidths of other parts of the system implementation, e.g. a printing press or image forming device. The present invention also provides the use of a RAM where the time for compression and decompression is not much slower is considered the RAM speed. In this way leads the The present invention provides a speed adaptation to a RAM by.

One Method and apparatus for performing compression and / or a decompression will be described. In one embodiment comprises the present invention is a system having a buffer, a wavelet transform unit and an encoder. The wavelet transformation unit has a Input connected to the buffer to a wavelet transform with pixels, stored in it and coefficients at an output to create. The encoder is to a wavelet transform unit connected to encode the transformed pixels from received in the buffer.

at The following description discloses further features. there can different features of different embodiments with each other be combined.

1A shows context dependency relationships. Children ("children") are on their parents or parents ("Parents") conditioned.

2A shows an order that resembles a grid order.

2 B Figure 4 shows an alternate embodiment of an order described herein as a short fringe order.

2C shows an alternative short seam order.

3A to 3H show the result of each application of the transistor transform filter for a four-level transform on a wavelet tree of the present invention.

4A Figure 13 is a block diagram of one embodiment of a forward / inverse filter unit for use in the implementation of the one-dimensional filters.

4B FIG. 12 is a block diagram of one embodiment of a first level forward transform according to the present invention. FIG.

5 Figure 10 is a block diagram of one embodiment of a complete forward transform according to the present invention.

6 is a timing diagram as to when coefficients are spent.

7A to 7H show the results (outputs) of each one-dimensional filter operation for the TT transformation.

8th Figure 10 is a block diagram of a 10-tap forward / inverse filter unit.

9 FIG. 12 is a block diagram of one embodiment of the overlap unit for the forward / inverse filters of FIG 8th ,

10 shows the order of the code stream and the order within a coding unit.

11 shows the bit depth of various coefficients in a two-level TS transform and a TT transform decomposition from an input image with b bits per pixel.

12 FIG. 12 is one embodiment of the frequency band multiplier used for coefficient alignment in the present invention. FIG.

13A shows a coefficient, which is divided into the most important data and less important data.

13B shows the lossless case where no data is deleted or deleted.

13C FIG. 12 shows the case where a bit-plane of data has been cleared (ie, Q = 2) since deleting a bit-plane corresponds to dividing by 2.

14 Fig. 10 is a flowchart showing an embodiment of the operation of the compression / decompression system.

15 shows an embodiment where 6 bits are used for each tree.

16 shows a flowchart for coding the most important part.

17 Figure 10 is a block diagram of one embodiment of the formatter and context model used during the most important data encoding run.

18 shows an embodiment of a first bit plane unit.

19 FIG. 10 is a flowchart illustrating an embodiment of the coding processing of a LIC bit plane. FIG shows.

20 Figure 12 is a block diagram of one embodiment of the predictive and contextual model for less important data.

21 Figure 10 is a block diagram of one embodiment of the context model that provides conditioning for header bits.

22 shows the memory usage for one embodiment of the context model with conditioning of all neighbors and parents.

23 Figure 4 is a block diagram of one embodiment of the sign bit context model.

24 shows an embodiment of parallel coding for the LIC.

25 Fig. 10 is a block diagram of one embodiment of a front end of a printer.

26 Figure 10 is a block diagram of one embodiment of the rear end of the printer.

27 Figure 12 is a block diagram of an alternative embodiment of the rear end of the printer.

28 Figure 10 is a block diagram of one embodiment of an integrated circuit (IC) chip that includes printer compression / decompression.

29 shows the basic timing of the system during printing.

30 Figure 1 shows one possible embodiment of how pixel data is organized.

31 shows a band buffer of a page.

32 FIG. 12 is a timing diagram of encoding that illustrates current memory access requirements. FIG.

33 Figure 4 illustrates how circular addressing can be used to handle the writing of data larger than the read data.

34 shows an encoder and decoder pair.

35 shows an embodiment of a binary context model.

36 shows an alternative embodiment of a binary context model.

37 shows the neighborhood coefficients for each coefficient of a coding unit.

38 shows a pyramidal orientation based on MSE alignment.

39 shows an MSE alignment of wavelet coefficients.

It become a method and apparatus for compression and decompression described. In the following description will be numerous details set forth as e.g. Delay types, Bitrates, filter types, etc. For however, it will be apparent to those skilled in the art that the present invention without these specific details can be practiced. In other make become well-known structures and devices in block diagram form shown, rather than in detail, to disguise the to avoid the present invention.

Some portions of the detailed descriptions that follow are presented in terms of algorithms and symbolic representations of operations with data bits within a computer memory. These algorithmic descriptions and representations represent the means used by those skilled in the data processing arts to effectively convey the substance of their work to others skilled in the art convey. An algorithm here and in general means a self-consistent sequence of steps leading to a desired result. The steps are those that require physical manipulations of physical quantities. Usually, but not necessarily, these quantities take the form of electrical and magnetic signals that can be stored, transferred, combined, compared, and otherwise manipulated. It has been found to be convenient, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, and the like.

you but should not forget that all these and similar Terme corresponding physical quantities are assigned and only appropriate names represent those quantities were awarded. Unless otherwise stated, how it turns out from the following discussion, one will realize that throughout in the present invention, the discussions, the terms, such as e.g. "Processing" or "calculating" or "calculating" or "determining" or "displaying" or the like, on the effect and on the processing of a computer system or a similar one electronic calculation device that manipulates data and transformed as physical (electronic) quantities within the registers and memory of the computer system are displayed, into other data that is similar to physical quantities within the memories or registers or other such information storage, transmission or display devices saved or registered.

The The present invention also relates to an apparatus for carrying out the operations to perform in it. This Apparatus can be specially designed for the required purposes can be constructed or it can be a general purpose computer which is selectively activated by a computer program or is reconfigured, which is stored in the computer. Such a thing Computer program can be stored in a computer-readable storage medium be such as in any kind of disk including floppy disk, optical disk, CD-ROMs and magneto-optical disk, read-only memory (ROMs), memory with random access (RAMs), EPROMs, EEPROMs, magnetic or optical cards or any type of medium for storage electronic instructions is suitable, each memory device can be connected to a computer system bus. The algorithms and advertisements presented herein are not inherent any particular computer or apparatus in relation.

Various general purpose devices can be used with programs that are in accordance with the teachings herein or it may prove appropriate, more specialized Set up apparatuses to carry out the required process steps. The required structure for A variety of these machines will become apparent from the following description result. additionally The present invention will not be described with reference to any certain programming language described. It will be appreciated that a variety of Programming languages can be used to implement the teachings of the invention, as described herein.

The following terms are used in the following description. A definition for these different terms was included. The definitions are not in principle a description of the prior art, but are intended to facilitate the understanding of the teachings of the present invention. ABS coding: ("ABS coding) A method of parallel entropy coding that uses simple codes (eg, run codes) for bit generation and probability estimation based on codewords used (eg, table likelihood estimation). In one embodiment, the ABS encoding also includes a method of multiplexing and demultiplexing streams from different encoders. Alignment: ("alignment") The degree of displacement of the transform coefficients in one frequency band with respect to the other frequency bands. arithmetic coding: ("arithmetic coding") Shannon / Elias finite precision arithmetic, not necessarily a binary entropy coder. B-coding: ("B-coding") A binary entropy coder that uses a finite state machine (FSM) for compression. Unlike Huffman coding, the use of the finite state machine results in good binary symbol handling and is useful for a range of input probabilities. binary entropy coder: ("binary entroyp coder") A noise-free encoder that works on binary (yes / no) decisions, often referred to as the most probable symbol (mps) and the least probable symbol (lps) , Binary style: ("binary-style") Encoding style with edge-fill or edge-fill Gray encoding of the pixels and a specific context model. Binary style context model: ("binary-style context model") A context model for bi-level and bi-level and bounded-level image data. Bit significance: ("bit-significance") A number representation, similar to sign and magnitude, with head bits followed by the sign bit, followed by tail bits, if any. Embedding encodes in bit-level order with respect to this representation. child-based order: ("child-based order") A scanning order by a two-dimensional image. It is similar to raster ordering except that the scanning works on two-by-two blocks Consider sampling a "parent" frequency band in raster order Each coefficient will have four children Children are ordered to the end of the line from top left, top right, left bottom and bottom right, followed by the next parent and the next set of four children, etc. Then processing returns to the next two lines and ends in the second line No lines are skipped, a child-based order is also referred to as a 2x2 block order. Coefficient: ("coefficient") Components after the transformation. Components: ("components") Components of the picture. The components form the pixels. For example, the red, green, and blue bands represent component bands. Each individual pixel is formed from a red, green, and blue component. Components and component bands may contain any type of information that has a spatial mapping on the image. Context model: ("context model") Causally available information relative to the currently-to-be-coded bit representing historically learned information about the current bit, allowing for conditional probability estimation for entropy coding. For binary images, one possible context for a pixel is the previous two pixels in the same row and three pixels from the previous row. Decomposition level: ("decomposition level") Place in the wavelet decomposition pyramid. This is directly related to the resolution. efficient transformation: ("efficient transform") Transformation that achieves the best energy compression in the coefficients, while the minimum number of bits is used to represent those coefficients. embedded context model: ("embedded context model") A context model that separates the context bins and results in levels of importance in such a way that effective lossy compression is obtained if the more important values are preserved. embedded with ordering: ("embedded with ordering") A special case of embedded context models, where there is no explicit tagging of importance, but rather the compressed data is ordered so that the most important data is in front. embedded quantization: ("embedded quantization") Quantization implemented by the code stream. For example, if the importance levels are placed in order, from the most important to least important, quantization is performed by simply cutting off the code stream. The same functionality results in tags or markers, markers, pointers or pointers, or other signaling. Multiple quantizations can be performed on a decoded image, but only embedded quantization can be performed at encode time. Entropy coder: ("entropy code") A device that encodes or decodes a current bit based on a probability estimate. An entropy coder may also be referred to herein as a multicontext binary entropy coder. The context of the current bit is some chosen configuration of "nearby" bits and allows a probability estimate for the best representation of the current bit (or more bits). In one embodiment, an entropy coder may include a binary coder, a parallel run-length coder, or a Huffman coder. Entry point: ("entry point") A point in the coded data starting with a known coding state. The encoder can start encoding at this point without decoding the previous data. In most cases, this requires the context and binary entropy coder to be reset to an initial state. The coded data for each coding unit starts at an entry point. Fixed length: ("fixed-length") A system that converts a specific block of data into a specific block of compressed data, such as BTC (block clipping) and certain forms of VQ (vector quantization). Fixed-length codes are for fixed rates and fixed-size applications, but Rate Distortion performance (see, eg, Anneal K. Jain, "Fundamentals of Digital Image Processing", Prentice Hall, 1989) is often poor compared to Variable rate systems. Fixed rate: ("fixed-rate") An application or system that maintains a certain pixel rate and has a narrow bandwidth channel. In one embodiment, to achieve this goal, local average compression is achieved rather than global average compression. For example, MPEG requires a fixed rate. Fixed size: ("fixed-size") An application or system that includes a buffer of limited size. In one embodiment, to achieve this goal, global average compression is achieved, eg, a print buffer. (The application can be a fixed-rate, a fixed-size application, or an application with both.) Frequency band: ("frequency band") Each frequency describes a set of coefficients resulting from the same sequence of filter operations. header bits: A bit significance representation, the head bits represent the Be ("head bits") Tragbits of the most significant or most significant up to and including the first bit is not equal to zero. Huffman encoder: ("Huffman Coder") In general, a fixed-length code that generates an integer number of bits for each symbol. Importance levels: ("importance levels") A unit of encoded data that corresponds to the embedded data before it compresses an entire bit-level. The importance level includes all appropriate bit planes from the different coefficient frequency bands. LPS (Least Probable Symbol): ("LPS (Least Probable Symbol")) The result of a binary decision with less than 50% probability. If two results are equally likely, it is unimportant what will be referred to as MPS or LPS as long as both the encoder and the decoder perform the same designation. lossless / noise-free / reversible coding: ("lossless / noiseless / reversible coding") Compressing data in a way that allows a perfect reconstruction of the original data. lossy coding: (lossy coding) Coding data that does not guarantee a perfect reconstruction of the original data. The changes to the original data may be made in such a manner that they are not visually objectionable or detectable. Often a fixed rate is possible. MPS (Most Probable Symbol): ("MPS (Most Probable Symbol)" The result or result of a binary decision with more than 50% probability. overlapped transformation: ("overlapped transform") A transformation where a single source point contributes to multiple coefficients of the same frequency. Examples are many wavelets and the overlapped orthogonal transform (LOT). Parent coefficient: ("parent coefficient") The coefficient or pixel in the next higher pyramidal level that covers the same image space as the current coefficient or pixel. For example, the parent for the 1SC coefficients are the 2SD coefficients that are the parent for the 3SD coefficients in Figure 1A. Probability Estimator / Module: ("Probability Estimation Machine / Module") Part of a coding system that tracks the likelihood within a context or records its lane. Progressive pixel depth: ("progressive pixel depth") A code stream ordered with deeper bit planes of data at full image resolution. progressive pyramidal: ("progressive pyramidal") A sequence of resolutions where each lower resolution is a linear factor of 2 in each dimension (a factor of 4 in area). Q-coder: ("Q-coder") A binary arithmetic coder where additions for multiplications have been substituted and probabilities have been limited to discrete values and probability estimates are updated as bits are output. Grid order: ("raster order") A scanning order by a two-dimensional image. It starts in the upper left corner, moves from left to right, then returns to the left side of the next line, finally ending in the lower right corner. No lines are skipped. reversible transformation: ("reversible transform") In one embodiment, a reversible transformation is an efficient transformation implemented with integer arithmetic whose compressed results can be reconstructed to the original values. Tail bits (or tail): ("tail-bits (or tail)") A bit significance representation, the tail bits represent magnitude bits that are less significant than the non-zero most significant bits. Tile data segment: ("tile data segment") Section of the code stream that completely describes a coding unit. "Tile" can be understood as a block or group. TS-transform: Two-Six transform ( "Two-Six" transformation) ( "TS-transform") a specific reversible wavelet filter pair with a 2-tap low-pass analysis and a 6-tap high pass analysis filter. The synthesis filters represent quadrature mirrors of the analysis filters. TT transformation: ("TT-transform") Two-Ten Transform, a specific reversible wavelet filter pair with a 2-tap low-pass analysis and a 10-tap high pass analysis filter. The synthesis filters ("Synthesis" filters) are quadrature mirrors of the analysis filters. combined lossless / lossy :( "unified lossless / lossy") The same compression system provides a code stream capable of lossless or lossy reconstruction. In one embodiment of the present invention, this code stream is capable of both without making adjustments to or giving commands to the encoder. Wavelet filter: ("wavelet filters") The high and low pass synthesis and analysis filters used in the wavelet transform. Wavelet transformation: ("wavelet transform") A transformation with both "frequency" and "time (or space)" domain constraints. In one embodiment, it represents a transformation that includes a high pass filter and a low pass filter. The resulting coefficients are decimated by two (critically filtered) and the filters are applied to the low-pass coefficients. Wavelet trees: ("wavelet trees") The coefficients and the pixels related to a single coefficient in the SS portion of the highest level wavelet decomposition. The number of coefficients represents a function of the number of levels. Figure 1A shows the coefficients contained in a wavelet tree. The span of a wavelet tree depends on the number of decomposition levels. For example, with a decomposition level, a wavelet tree spans four pixels, with two levels it spans 16 and so on. Table 1 below shows the number of pixels that are affected by a wavelet tree for different levels. In two dimensions, each wavelet tree includes three subtrees, called SD, DD, and DS.

Table 1 Span of a wavelet tree for different levels of decompression

The The present invention provides a compression / decompression system ready with a coding section and a decoding section. Of the Coding section is for the coding of the input data responsible for compressed data to produce while the decoding section for decoding previously coded data is responsible for one reconstructed version of the original To generate input data. The input data can be a variety of data types include, e.g. Image data (still images or video images), audio data etc. In one embodiment is the data digital signal data; however, are Digitized analog data, text data formats and other formats possible. The source of the data for the coding section and / or the decoding section may be a memory or be a channel.

at of the present invention Elements of the coding section and / or the decoding section implemented or realized in hardware or software, such as. those used in a computer system. The The present invention provides a lossless compression / decompression system The present invention may also be configured to perform lossy compression / decompression.

The System of the present invention uses fast lossy / lossless Compression by reversible wavelets, which is more accurate below is described. The system may include a printer, e.g. a laser printer contain. In one embodiment The printer uses a reasonably priced hard disk to create a save the edited page, which greatly reduces the amount of expensive Memory with random access (RAM) is reduced. The compression is used to the limited Bandwidth of the hard disk or storage device to the larger bandwidth, needed by the printing press will adapt. The coding technology of the present invention Fulfills the high-speed, real-time requirements of the printing press, while the present invention either an excellent lossless or provides lossy compression, as evidenced by the image characteristics and the discontinuous nature of the hard drive are required.

The The following detailed description provides a general overview of the Reversible wavelet compression, a compressed full-screen storage application, a Color laser printers and embodiments of a printer chip. The reconditioning machine of the printer is used a hard disk to save. Because the hard drive is slower As the printing press, the compression is used to rate matching make. An ad list technology can also be used be around during the to reduce the processing required storage. A processing machine, based on an ad list, allows the compression system to bands of the picture independently handle. It is noteworthy that, although the present invention is described in terms of a printer system, the present Invention is applicable to other systems, the compression and / or Decompression subsystems included as parts thereof.

As well herein is an embedded unified lossless / lossy compression system described. The embedded characteristic of the system allows the quality through the transmission rate the disc or disc is determined. For slightly compressed pictures (e.g., most documents with text and / or line drawing) achieves lossless compression. For more difficult to compress Images (e.g., documents with noisy natural images and / or halftones) achieves high quality lossy compression.

For a description of a system or systems that provide both lossless compression as well as lossy high quality compression of color images support, is assigned to U.S. Patent Application Serial No. 08 / 642,518, filed 3. May 1996, entitled "Compression and Decompression with Wavelet Style and Binary Style Including Quantization by Device Dependent Parser, "and U.S. Patent Application No. 08 / 436,662 on May 8, 1995, entitled "Method and Apparatus for Reversible Color Conversion ".

Reversible wavelets

The The present invention uses compression by reversible Wavelets.

Wavelet decomposition

The present invention leads at the beginning a decomposition of an image (in the form of image data) or another data signal by using reversible wavelets become. In the present invention, a reversible wavelet transform includes a Implementation of an exact reconstruction system in integer arithmetic, so that a signal with integer coefficients lossless can be recovered. An efficient reversible transformation is one with a transformation matrix, whose determinant is 1 (or almost 1).

By the use of reversible wavelets is the present invention capable of a lossless compression with finite precision arithmetic provide. The results obtained by the application of the reversible Wavelet transformation to be generated on the image data are one Set of coefficients.

The reversibe wavelet transformation of the present invention can be implemented by using a set of filters. In one embodiment the filters are a 2-tap low pass filter and a 6-tap high pass filter, to implement a transformation, referred to herein as a TS transformation or 2,6 transformation. In another embodiment the filters are a 2-tap low pass filter and a 10-tap high pass filter, to implement a transformation, referred to herein as a TT transformation or 2,10 transformation. These filters can be implemented only by adding and subtracting operations (plus hardware-wired Bit shift).

The TT transformation has at least one advantage and at least a disadvantage compared to the TS transformation. An advantage is that they give better compression provides as the TS transformation. The disadvantage of TT transformation is that the longer 10-tap filter a higher Hardware required.

Two-dimensional Wavelet decomposition

By using low-pass and high-pass filters in the present invention, a multi-resolution decomposition is performed. The number of levels of decomposition is variable and may be any number; however, the current number of decomposition levels is equal to 2 to 8 levels. The maximum number of levels is log _{2 of} the maximum length or width of the input.

The most general way to transform with two-dimensional Perform data, such as e.g. a picture lies in it, the one-dimensional filter separately to apply, i. along the lines and then along the columns. The first level of decomposition leads to four different coefficient bands, referred to herein as SS, DS, SD and DD are called. The letters refer to smooth (S for "Smooth") and Detail (D) filters, defined above, the respective low (L for "low") and high (H for "high") pass filters correspond. Consequently, the SS band consists of coefficients from the smooth filters both in the row direction and in the column direction.

each Frequency subband in a wavelet decomposition can be further decomposed become. The most common practice is to use only the SS frequency subband continue to disassemble. It can be a further decomposition of the SS frequency subband in each decomposition level when each is generated. A Such multiple decomposition is called pyramidal decomposition. The terms SS, SD, DS, DD and the decomposition level number denote any decomposition.

Remarkable is that neither with the TS or TT transform of the present invention the pyramidal decomposition does not increase the coefficient size.

If the reversible wavelet transform is recursively applied to an image The first level of decomposition works at the finest detail or the finest resolution. At a first decomposition level, the image becomes four sub-images (e.g., subbands) disassembled. Each subband represents a band of spatial frequencies. The first level subbands are called 1SS, 1SD, 1DS and 1DD. The process of decomposition of the original image a subsampling with two in both horizontal and vertical dimensions, So that the subbands first levels 1SS, 1SD, 1DS and 1DD each a quarter as many Have coefficients such as the input pixels (or coefficients) of the picture.

The Subband 1SS contains simultaneously low frequency horizontal and low frequency vertical information. Typically, a big one Part of the forming energy concentrated in this subband (to term of energy see above mentioned Book by Anneal K. Jain op. Cit., See in particular the terms "energy compaction" and "energy conservation"). The subband 1SD contains a low frequency horizontal and a high frequency vertical information (e.g., horizontal edge information or "edge" information). The Subband 1DS contains high-frequency horizontal information and low-frequency vertical information (e.g., vertical edge information). The subband 1DD contains a High-frequency horizontal information and high-frequency vertical information (e.g., structural or diagonal edge information).

each the successive second, third and fourth lower decomposition levels is done by decomposing the lower frequency SS subband of the previous one Generated levels. This subband 1SS of the first level is decomposed, around subbands 2SS, 2SD, 2DS and 2DD of moderately detailed to generate second levels. In similar Way, the subband 2SS is decomposed to roughly detailed sub-bands 3SS, 3SD, 3DS and 3DD of the third level. Likewise, that will Sub-band SS, decomposed to rough detailed sub-bands 4SS, 4SD, 4DS and 4DD of the third level. Due to subsampling at two, every second level sub-band becomes one-sixteenth of Size of the original Image. Each sample or value (e.g., pixel) represents this Level a moderate detail in the original picture or a moderately detailed Playback of the original image in the same place. In similar Way is every third level subband 1/64 the size of the original image. each Pixel at this level corresponds to a relatively rough detail in the original picture or a coarse grained detailed reproduction of the original image in the same place. Likewise every fourth level sub-band 1/256 the size of the original image.

There the decomposed images are physically smaller due to undersampling are as the original image, the same memory, which can be stored The original image used to be all disassembled subbands save. In other words, the original image and the disassembled subbands 1SS and 2SS eliminated or deleted and not stored in a three-level decomposition.

Even though only four subband decomposition levels are described, may additional Levels in agreement be developed with the requirements of a particular system. Likewise with other transformations, e.g. a DCT or linearly spaced Sub-bands, different parent-child relationships.

Remarkable is that one pyramidal decomposition does not decompose the coefficient size with the wavelet filters of the present invention.

at other embodiments can other subbands additionally to be split up to the SS as well.

Tree structure of the wavelets

It gives a natural and useful Tree structure for Wavelet coefficients in a pyramidal decomposition. A result The subband decomposition is a single SS frequency subband that corresponds to the last level of a decomposition. On the other hand There are as many SD, DS and DD bands as the number of levels. The tree structure places the parent of a coefficient in one Frequency band so tight that it turns on Coefficient in a same frequency band at a lower resolution and with the same spatial location in relationship.

In the present invention, each tree comprises the SS coefficients and three subtrees, viz the DS, SD, and DD subtrees. The processing of the present invention is typically performed on three subtrees. The root of each tree is a pure smoothing coefficient. For a two-dimensional signal, such as a picture, there are three subtrees, each with four children. The tree is hierarchically not limited to two-dimensional signals. For example, with a one-dimensional signal, each sub-tree has a child. Higher dimensions result from the one-dimensional and two-dimensional case.

Of the Process one Multiresolution decomposition can be performed using a filter system. Regarding a two-dimensional two-level transformation, implemented using one-dimensional exemplary filters See, for example, U.S. Patent Application No. 08 / 498,695, filed June 30 1995, entitled "Method and Apparatus for Compression Using Reversible Wavelet Transforms and to Embedded Codestream "and U.S. Patent Application No. 08 / 498,036, filed June 30, 1995, titled "Reversible Wavelet Transform and Embedded Codestream Manipulation ".

Perform the Forward wavelet transform

at According to the present invention, the wavelet transform is two 1D operations, first horizontal, then vertical. at an embodiment introduces Hardware part goes through the horizontal operation while another goes through the vertical ones Performs operations.

The Number of levels determines the number of iterations. At a embodiment a four-level decomposition is performed by the TT transformation used in both the horizontal and vertical directions becomes. In another embodiment The four-level decomposition is performed by using four DS transformations be used instead.

The Transformation of the present invention is in terms of calculation very efficient. In one embodiment assigns the present invention, the calculations by the Transformation performed are the amount of both on-chip memory (On-Chip Memory) as well as one not on a chip Memory (Official Communication Chip Memory) and the required bandwidth to reduce.

Calculation orders or Sequences of calculation and data flow for the transformation

As has been described above, in the present invention, the Base unit for calculating the transformation of the wavelet tree Let's take a four-level transformation On, each wavelet tree represents a 16x16 block of pixels. A 16x16 block of pixels (all four components for CMYK images) is input to the transformation of the present invention and all sorts of things Calculations to generate coefficients are performed. (The Inverse is similar a 16x16 block of coefficients for each component is entered and all sorts of things Calculations are performed.) Since the present invention uses an overlapped transformation, the information is stored by previous, neighboring trees and used in the calculations. The boundary between the current wavelet tree and the previous adjacent information is referred to herein as a hem called. The information that is saved about a hem, to carry out the transformation of the present invention is detailed below.

Order of Wavelet trees

The Order of wavelet trees to calculate the transformation is important because in certain applications (e.g., printing) encoding units of the present invention have a large width and a low altitude exhibit. In one embodiment contains each coding unit 4096x256 pixels.

In the following discussion, each of the encoding units contains 4096x256 pixels. However, it is noteworthy that the ordering described below is applicable to encoding units of other sizes. 2A shows an order that resembles a grid order. This order is referred to herein as a long-tail transformation order. If you take reference 2A For example, the thick lines indicate the amount of data that is preserved across the seams and indicate how much memory is needed to compute the transformation. This data is proportional to a wavelet tree for the horizontal transformation, but to the width of the image (4096 in this example) for the vertical transformation. The amount of memory for the data may require the use of external memory. However, because of the closeness of the raster order during the inverse transform, the data of transformation (for example, to a printer in a printer application) as soon as a horizontal row of wavelet trees needs to be converted to pixels.

2 B FIG. 12 shows an alternative embodiment of an order, referred to herein as a short seam order. The memory for the seams is proportional to the height of the encoding unit (256 in this example) for the horizontal transformation and a wavelet tree for the vertical transformation. This significantly reduces the amount of memory required, making storage on-chip (on-chip storage) feasible.

2C shows an alternative short seam order. At the expense of memory proportional to another wavelet tree, the number of consecutive pixels processed in raster order is increased. These alternative or similar alternatives may allow more efficient use of a fast page mode or RAM for the accelerated data output or an EDO RAM in the band buffer with little overhead in the seam memory. Efficiency is gained by the fact that most of the memory is desired or optimized for access to adjacent memory locations. Therefore, any increase in the use of adjacent memory accesses due to the sear sequence results in more efficient memory usage.

calculation for one Wavelet tree

The following equations lay both the TS transformation as well the TT transformation firmly. For an input x (n) will be the output of the low pass filter, the smooth signal s (n), and the high-pass filter, the detailed signal d (n), calculated as in the following equation is shown.

wobei p(n) wie folgt berechnet wird: p(n) = d(n) – t(n). The inverse transformation is shown in the following equation.

where p (n) is calculated as follows: p (n) = d (n) -t (n).

The TS transformation and the TT transformation differ in the definition of t (n). For the TS transformation:

For the TT transformation, the following applies:

Remarkable is that at the following discussion means the notation ⌊.⌋ to round down or cut down and is sometimes used as ground function designated.

The TS transformation

The effect of using the six-tap filter and a two-tap filter at even intervals is that three pieces of information must be stored. The six-tap filter requires two delays. The two-tap filter requires a delay so that its result can be centered with respect to the result of the six-tap filter. In particular, two s (•) values and a d (•) value or a partial result from the d (•) calculation are stored. A storage of these values is identical regardless of whether or not a particular filter operation crosses a seam or not.

3A to 3H show the result of each application of the TS transform filter for a four-level transform on a wavelet tree of the present invention. In these figures, the output of the low-pass filter is referred to as "s" for "smooth". The output of the high pass filter is referred to as "d" for detail. The "B" denotes an intermediate value used to calculate a "d"; it is an x (2n) - x (2n + 1) value. The "B" values are used during the forward transformation; for inverse transformation, a "d" value that is not used for any calculations is stored in its place. The notation "sd" indicates that a coefficient is the result of first a horizontal low-pass filter and then a vertical high-pass filter. The meanings of "ds", "dd", "ss", "dB" and "sB" are similar. The bold or bold rectangle corresponds to the 256 input pixels. The shaded "s", "ds" and "ss" values are calculated with a previous wavelet tree and used for use in the current wavelet tree.

Regarding the forward transformation represent the "ss" coefficients of the previous level the inputs to the levels 2, 3 and 4 of the transformation. The "sd", "ds" and "dd" coefficients are done so they can be issued when they are calculated. The inverse transformation performs all calculations in a respect of the levels (the fourth level first, then the third, second and third finally that first) and re vertical (first) and horizontal (second) order. Within one pass of the transformation is the flow of forward and inversely identical, but the calculation is different.

TS transform hardware

4A Fig. 10 is a block diagram of one embodiment of a forward / inverse filter unit for use in the implementation of the one-dimensional filters. Only memory and calculation units are shown, hardware wired shifts are not shown. If you take reference 4A so handles a filter unit 4000 both forward and inverse transformation. Alternative embodiments may be used to separate units for forward and inverse transformation. For the forward transform, inputs of size "n" are used and the "s" and "d" outputs are generated. For inverse transformation, the "s" and "d" inputs are used and the other outputs are generated.

The adder 4001 is connected to receive n-bit inputs and to add them together to produce an output x (2n + 2) + x (2n + 3). The adder 4002 subtracts one n-bit input from the other and outputs the quantity x (2n + 2) -x (2n + 3). The outputs of the adders 4001 and 4002 are connected to one input of the multiplexer (each abbreviated to "mux") 4003 and 4004 respectively connected. The other inputs to the multiplexers 4003 and 4004 are connected to receive the s and d inputs, respectively. In one embodiment, the s input is n bits while the d input is greater than n bits.

The output of the multiplexers 4003 and 4004 is controlled by a forward / inverse control signal indicating whether the filter is in forward or reverse mode. In either the forward or inverse mode, the output of the multiplexer is 4003 equal to s (n + 1). On the other side is the output of the multiplexer 4004 equal to p (n + 1) in the forward mode and d (n + 1) in the inverse mode.

The outputs from the multiplexers 4003 and 4004 together with a feedback of an s (n) output from the multiplexer 4006 become the inputs of the register file 4005 coupled. The register file 4005 contains the entries for each component for the length of a wavelet tree. The data is typically passed through the register file 4005 through enough. Based on the spatial location, the inputs become the register 4005 delayed to the exit. An address entry controls the outputs of the register file 4005 , In one embodiment, the register file includes 4005 two memory banks with one port per bank and is used in a ping-pong style, with back and forth access between the two memory banks.

The output of the multiplexer 4003 also represents the s output of the filter unit.

The outputs of the register file 4005 are with the inputs of the multiplexer 4006 together with the externally buffered data at a hem buffer in 4020 connected. The edition 4006A includes s (n-1), what a twice delayed version of the output from the multiplexer 4003 is. The edition 4006B includes s (n), which is a delayed version of s (n + 1). The edition 4006C includes p (n) for the forward mode and d (n) for the inverse mode. The multiplexer 4006 is also controlled to externally buffer hem data at the hem buffer output 4021 provide.

The edition 4006C is with an input of adders 4008 and 4009 connected. The other input of adders 4008 and 4009 is the output of the multiplexer 4015 , The multiplexer 4015 handles the boundary conditions or boundary conditions. On a border there is the multiplexer 4015 like the zero hardwired to one of its inputs. The hard-wired zero can be changed to use other values in some embodiments. In a non-boundary condition, the multiplexer outputs 4015 t (n) from the adder 4007 which is connected to add s (n + 1) to an input to s (n-1) to another input by subtracting s (n-1) from s (n + 1).

The adder 4008 adds the output 4006C from the multiplexer 4006 to the output from the multiplexer 4015 to generate the d output of the filter unit.

The adder 4009 subtracts the output from 4006C from the multiplexer 4006 from the output from the multiplexer 4015 , The output of the adder 4009 becomes s (n) on the output 4006B of the multiplexer 4006 through the adder 4010 is added to produce an n-bit output of the filter unit. The edition 4009 is also of s (n) of the output 4006B from the multiplexer 4006 through the adder 4011 which outputs the other n-bit output of the filter unit in the inverse direction.

For seams that are longer than a wavelet tree, seam data may reside in on-chip static RAM (SRAM) or external memory instead of a register file 4005 get saved. The multiplexer 4006 provides access to and from this additional hem memory.

The largest hardware effort or the most hardware costs of the filter unit 4000 are on the register file 4005 due. The total amount of memory needed depends on the number of filter units. In one embodiment, a total of 60 locations are needed to store three values (s, s, d or ss, ss, sd). If more filter units are used, the required amount of memory is smaller. Therefore, the hardware costs or the hardware costs for the use of multiple filter units are low.

A fast inverse transformation allows lower latency between the end of decoding and start of the file output operation, such as e.g. To Print. This reduces the memory needed for decompression needed and allows larger encoding units. A fast forward transformation allows it that the Filter discontinuities in the data or data bursts can handle, if a larger bandwidth available is what makes it possible, that the Transformation provides more data to the contextual model, if one Looking ahead, the text model allows you to quickly access the data to process. If the forward transformation not with the contextual model during of coding, a disc bandwidth or Disk bandwidth during of coding, which wastes time until the beginning of printing delayed. Likewise the control and the data flow through the use of multiple filters can be simplified.

4B Figure 10 is a block diagram of one embodiment of a first level forward transform according to the present invention. If you take reference 4B so lead two filter units 401 and 402 , such as those in 4A are shown, the first level of transformation through. The filter unit 401 performs a level 1 horizontal transformation while the filter unit 402 performs a level 1 vertical transformation. In one embodiment, the first level of the transformation operates on 2x2 blocks of the input. Four registers 403 to 406 work as delay units to filter unit outputs 401 to delay. This is called a child-based order. The registry 403 receives the S output of the filter unit 401 while the registers 404 and 405 receive the d output. The output of the register 404 is at the input of the register 406 connected. The issues of the registers 403 and 406 are to the inputs of the multiplexer 407 whereas the s output of the filter unit 401 and the output of the register 405 to the inputs of the multiplexer 408 are connected. Two multiplexers 407 and 408 select inputs for the filter unit 402 from those of the delayed coefficient output from the filter unit 401 out.

The filter unit 401 works consecutively on two vertically adjacent pairs of inputs. This produces four coefficients, with the correct delay being set by the registers 403 to 406 for each component is provided in the filter unit 402 be entered. Three of these four results can be output immediately, the "ss" output is processed further.

The forward transmission according to the first level works on groups of four pixels which are in 2x2 groupings. For discussion purposes, the first row or row should contain pixels a and b, while the second row should contain pixels c and d. The operation of the first-level-four-transformation in 4B is as follows. During the first cycle, the horizontal transformation is applied to the a and b pixels passing through the filter unit 401 are processed. The filter unit 401 produces the S _from what's in the register 403 stored, and D _from what is in the register 404 and 405 is stored. In the next cycle, pixels c and d pass through the filter unit 401 processed to perform the horizontal transformation. As a result of application of the filter unit 401 S _cd that is in the register 403 is stored, and D _cd in the registers 404 and 405 is stored, generated. In this cycle, S are subtracted _from the register 403 and S _cd from the register 405 through the filter unit 402 which performs a vertical pass of the transformation and generates SS and SD. Also during the second cycle, the value D _ab moves _from the register 404 to the register 406 , In the next cycle, the value D is removed _from the register 406 and D _cd of 405 through the filter unit 402 which generates the outputs DS and DD. In the same cycle processed filter unit 401 the a and b pixels from the next 2x2 block.

5 Figure 10 is a block diagram of one embodiment of a forward transform according to the present invention. If you take reference 5 , so does the level 1 transformation 502 the level 1 transformation by. In one embodiment, the level 1 transformation comprises the level 1 transformation of 4B , The filter unit 505 , handles the levels 2, 3 and 4 of the transformation. A store 503 stores "ss" coefficients until sufficient coefficients are available to perform the transformation. The number of coefficients to be stored is shown in Table 2 below. (Each digit stores a coefficient for each component.)

Table 2 - "ss" delay memory

The order unit 504 multiplexes the correct entries in the filter unit 505 , The input buffer 501 and the output buffer 506 may be required to tune between the transfer order needed by the transform and the order needed by the band buffer or the context model.

For inverse transformation, the data flow is reversed, with the level 4 inverse transform followed by the level 3, level 2, and level 1 transforms in an order. The output of the level 2 transform becomes the level 1 transform first level transform hardware 502 entered. Likewise, vertical filtering is performed before horizontal filtering. Since the horizontal and vertical filtering are identical except that one direction requires access to additional memories for the seams, inversion of the data flow can be performed with a small amount of multiplexing. Prior to the inverse transform, the two-byte coefficients must be converted from the embedded form with two signaling bits to normal two's complement numbers.

The elements that are in 4B and 5 can also be used for the TT transformations.

Transformations timing

The transformation timing of the forward transformation of 5 based on the timing of the individual filter units. The first filter unit, the filter unit 401 calculated horizontal level 1 transformations, while the second filter unit, the filter unit 402 calculated vertical level 1 transformations. The third filter unit, the filter unit 505 , calculates transformations for levels 2 to 4 or she is idle.

In one embodiment, the third filter unit calculates ( 505 ) when not idle, horizontal transforms during even clock cycles and vertical transforms during odd clock cycles. The timing for inverse transformation is similar (but vice versa).

at The following example shows 2x2 blocks within a wavelet tree processed in the transposed a raster order. Remarkable is that one low input / output (I / O) buffering might be required to support a fast page mode / EDO DRAM if 2x2 blocks within a Wavelet tree instead be processed in raster order.

6 is a timing chart for the case when coefficients are output. The following timing or timing applies to each pixel. There are four components per pixel.

Since it is more common for a person skilled in the art to read so-called pseudo codes in the English language, the pseudo code reproduced above in German is again reproduced in English:

TT transform

7A to 7H show the results (outputs) of each one-dimensional filter operation of the TT transformation. A rectangle displays coefficients in a single wavelet tree that corresponds to the input pixels currently being processed. Shading indicates coefficients stored by the previous tree. The values labeled "B" represent intermediate results that are stored (and the difference between adjacent samples or represent values). The TT transformation is similar to the TS transformation, but requires more memory.

8th Figure 10 is a block diagram of a 10-tap forward / inverse filter unit. It is noteworthy that hardware wired shifts and round offsets are not shown so as not to obscure the present invention. It is noteworthy that the multiplexer 806 in 8th also can be used for mirroring ("mirroring") at transformation limits. For an implementation of the mirroring, it is also necessary that the "d" input 0 be made and the s (n + 2) input of the overlap unit be multiplexed.

If you take reference 8th so are the adders 801 and 802 connected to receive the 2 n-bit inputs during the forward pass of the filter unit. The adder 801 adds the 2-n-bit inputs and outputs a value equal to one input of the multiplexer 803 connected is. The adder 802 subtracts one input from the other, giving its output to one input of the multiplexer 804 generated. The multiplexers 803 and 804 are also connected to receive the s and d inputs respectively for the inverse-mode operation of the filter unit. The outputs of the multiplexer 803 represent an n-bit input equal to s (n + 2) while the output of the multiplexer 804 corresponds to an n + 1-bit input which is p (n + 2) for the forward pass and d (n + 2) for the inverse pass.

Both outputs of the multiplexer 803 and 804 are with the inputs of the memory 805 connected. Likewise are with the inputs of the memory 805 expenditure 806A and 806D connected to F by the multiplexer 806 be issued. The memory 805 delays the inputs to its outputs based on the spatial location. In one embodiment, the memory comprises 805 a register file or SRAM connected in a ping-pong fashion with two banks or one port per bank. An address is connected to an input of the memory to control the outputs necessary for the multiplexer 806 be generated. In one embodiment, the address stores 16 or 28 Digits per component.

The issues of the store 805 are connected to the inputs of the multiplexer 806 along with the external buffer data supplied by the hem buffer 820 be received, connected. The edition 806A of the multiplexer 806 includes s (n + 1), which is a once-delayed version of s (n + 2) at the output from the multiplexer 803 is. The exit 806B of the multiplexer 806 includes s (n), which is a twice delayed version of the output of the multiplexer 803 is. The exit 806C of the multiplexer 806 includes p (n) for the forward pass, which is a twice delayed version of the output of the multiplexer 806 is, and d (n) in the inverse pass, which is a twice delayed version of the output of the multiplexer 804 is. The exit 806D includes s (n-2), which is a four-time delayed version of the output of the multiplexer 803 is. The exit 806E of the multiplexer 806 includes s (n-1), which is delayed three times from the output of the multiplexer 803 is. Ultimately, the output includes 806F t (n + 1) in the forward pass, which is a once-delayed version of the output of the multiplexer 804 is, and d (n + 1) for the inverse pass, which is a once delayed version of the output of the multiplexer 804 is.

The overlap unit 807 is connected to the output of the multiplexer 803 along with the issues 806A , D and E from the multiplexer 806 to recieve. In response to these inputs, the overlap unit generates 807 t (n). An embodiment of the overlapping unit is shown in FIG 9 described.

The output of the overlap unit 807 , t (n), is one input of the adders 808 and 809 connected. The adder 808 adds t (n) to the output 806C of the multiplexer 806 to generate the D output of the filter unit. The adder 809 subtracts the output 806C of the multiplexer 806 from t (n). The output of the adder 809 is with one input from each of the adders 810 and 811 connected. The adder 810 adds the output of the adder 809 with the exit 806B of the multiplexer 806 to produce one of the n-bit outputs of the filter when operating as an inverse filter unit. The adder 811 subtracts the output of the adder 809 from the exit 806B of the multiplexer 806 to generate the other output of the filter unit when operating as an inverse filter.

9 FIG. 12 is a block diagram of one embodiment of the overlap unit for the forward / inverse filter of FIG 8th , If you take reference 9 Thus, the overlap unit comprises adders 901 to 906 , Multiplier 907 to 909 and a divider 910 , The multipliers and dividers may be hardware-wired shifters.

The overlap unit of 9 calculates t (n) for the TT transformation described above. If you take reference 9 so is the adder 901 connected to receive the s (n + 2) input and to subtract it from the s (n - 2) input, and generates an output which is applied to one input of the s adder 903 is coupled. The adder 902 is connected to receive the s (n - 1) input and to subtract it from the s (n + 1) input. The output of the adder 902 is at the input of the multiplier 907 and multiplier 908 connected. The multiplier 907 multiplies its input by 2. In one embodiment, the multiplication is performed by shifting the bits to the left position. The output of the multiplier 907 is at the other input of the adder 903 connected.

The multiplier 908 multiplies the output of the adder 902 16. In one embodiment, the multiplication is performed by shifting the bits sent by the adder 902 are output, to the left four bit positions. The output of the multiplexer 908 is to an input of the adder 905 connected. The output of the adder 903 is to an input of the adder 904 connected and also to the input of the multiplexer 909 ,

The multiplier 909 multiplies the output of the adder 903 with 2. In one embodiment, this multiplication is performed by shifting the bits sent by the adder 903 are output to the left bit position. The output of the multiplier 909 is with the other input of the adder 904 connected. The output of the adder 904 is with the other input of the adder 905 connected. The output of the adder 905 is to an input of the adder 906 connected, adding them to 32, which is a hardware-wired input. The output of the adder 906 is at the start of the divider 910 connected. The divider 910 divides the input by 64. In one embodiment, this division is accomplished by shifting the bits of the input to the right six bit positions. The output of the divider 910 includes the t (n) output. It is noteworthy that the 9 shows each output with the current value on the lines.

Remarkable is that both in reversible TS transformation as well as TT transformation, similar to the s-transform, the low-pass filter is implemented like this that the Span of the input signal x (n) is the same as that of the output signal s (n). This means, there is no growth in the smooth output. If the input signal b bits is deep, then amounts to the smooth or smoothed Output as well b bits. For example, if the signal is an 8-bit image is, the output of the low-pass filter as well 8 bits. This is an important property for a pyramidal System where the smooth output is further decompressed by e.g. successively applying the low-pass filter. In prior art systems, the span of the output signal is greater than those of the input signal, whereby successive or successive Applications of the filter are difficult. Likewise, there is no systemic Error due to rounding in integer implementations of the Transformation, so that all Error in a lossy system due to quantization can be controlled or controlled. In addition, the low pass filter just two taps on, making it a non-overlapping filter. This property is for the hardware implementation important.

embedded Organize

at According to the present invention, the coefficients serving as a Result of the wavelet decomposition can be generated, entropy-coded. In the present invention, the coefficients initially undergo an embedded one Order in which the coefficients are in a visually significant Ordered order, or more generally with respect to the same Error metric (e.g., distortion metric). Error or distortion metrics include e.g. a top mistake or middle one squared error or mean square error (MSE). In addition, can a sorting performed be of relevance to a bit significance space location the database query and one direction (vertical, horizontal, diagonal, etc.) to give preference.

The Ordering the data is done to generate the embedded quantization of the code stream. at Two ordering systems are used in the present invention: a first for ordering the coefficients and a second for ordering the binary Values within a coefficient. The order of the present Invention generates a bitstream which is subsequently provided with a binary entropy coder is encoded.

Bit-significance representation

Most transform coefficients represent signed numbers, even if the original components are unsigned (each coefficient output by at least one detail filter is signed). In one embodiment, the embedded order used for binary values within a coefficient is a bit-level bit-plane order. The Ko Efficiencies are expressed in a bit significance representation before encoding. The bit significance is a sign magnitude representation where the sign bit, rather than being the most significant bit (MSB), is encoded with the first non-zero magnitude bit. That is, the sign bit follows the first nonzero bit, rather than preceding all magnitude bits. Likewise, the sign bit is considered to be in the same bit-plane as the most significant magnitude non-zero magnitude bit.

The bit significance format represents a number using three sets of bits: head, tail, and sign. The header bits are all zero bits from the MSB up to and including the first nonzero magnitude bit. The bit plane in which the first non-zero magnitude bit occurs determines the significance of the coefficient. The set of tail bits includes the magnitude bits after the first non-zero magnitude bit up to the LSB. The sign bit simply denotes the sign, where 0 can represent a positive sign and 1 a negative sign. A number, such as ± 1 ⁿ , with a zero bit as the MSB has only one header. A zero coefficient has no tail or sign bits. Table 3 shows all possible values for forming bit coefficients ranging from -7 to 8.

Table 3 - Bit significance representation for 4-bit values

In Table 3 contains the bit significance representation shown in each column one or two bits. In the case of two bits, the first bit is the first 1-bit and is followed by the sign bit.

In the case where the values are non-negative integers, as occurs, for example, with respect to the intensity of the pixels, the order that can be used is bit plane order or bit plane order (eg, from most significant to least significant bit level). The embodiments where negative integer integer numbers are also allowed, the embedded order of the sign bit is the same as the first non-zero bit of the integer value of the integer. Therefore, the sign bit is ignored until a nonzero bit is encoded. For example, if you use a sign magnitude notation, the 16 bit number is -7:
1000000000000111

On At a bit-plane basis, the first twelve decisions will be "insignificant" or zero. The first 1-bit occurs at the thirteenth decision. When next the sign bit ("negative") is coded. After this the sign bit is encoded, the tail bits are processed. The fifteenth and sixteenth decision is "1".

There the coefficients of the highest order Bite level must be encoded to the least significant bit plane, the number the bitplanes in the data. At the present The invention accomplishes this by setting an upper bound on the values of the coefficient values which are calculated from the data or from the depth of the image and the filter coefficients. If e.g. the upper limit is 149, then there are eight significant bits or eight bit planes. For acceleration the software can not use a bit-plane encoder. In an alternative embodiment a bit plane is only coded if a coefficient is a binary number becomes significant.

coefficients orientation

The The present invention sets coefficients before bid-plane coding against each other. This is because the coefficients in different Frequency sub-bands represent different frequencies that are similar to the FFT or the DCT. By the alignment of the coefficients controls the present invention the quantization. The less heavily quantized coefficients will be heading towards the earlier bit levels aligned (e.g., shifted to the left). Thus, these coefficients, if the stream is cut off, they have more bits that they than the more heavily quantized coefficients.

at an embodiment be the coefficients for the best rate distortion efficiency in terms of SNR ("Signal to Noise Ratio "or" signal-to-noise ratio ") or MSE are many possible Orientations or arrangements including one that is almost in terms of the statistical error metrics, such as MSE, is. alternative could the orientation is a psychovisual quantization of the coefficient data allow. The orientation has a significant influence on the Evolution of image quality (or in other words on the rate-distortion curve), but she has one negligible influence the final compression ratio of lossless system. Other orientations may be specific coefficient quantization, a region of interest fidelity or resolution-progressive alignment ("resolution progressive alignment ").

The Alignment can be signaled in the header of the compressed data his or she can be for a particular application (i.e., the system has only one Orientation). The orientation of the different sizes Coefficients are known to both the encoder and the decoder and has no influence on the efficiency of the entropy coder.

The bit depths of the various coefficients in a two-level TS transform and a TT transform decomposition from a b-bit per pixel input image are in 11 shown. The 12 FIG. 10 illustrates one embodiment of the multiplier for the frequency band used for coefficient alignment in the present invention. To align the coefficients, the 1-DD coefficient size is used as a reference, and shifts are made with respect to that size. A shift of n represents a multiplication by 2 ⁿ .

at an embodiment the coefficients are relative to the amount of the largest coefficient, to create an alignment of all coefficients in the image. The aligned coefficients are then handled in bit planes, are called the importance levels, and of the most significant one Importance level at the lowest significant importance level. The sign becomes the last bit of each coefficient coded. The sign bit is where the last header bit is inside, regardless of the level of importance of the last header bit inside is. It is important that the alignment simply controls the order in which the bits to the entropy encoder be sent. Indeed becomes a padding, Move, save or encode extra zero bits not performed.

table 4 shows an embodiment alignment numbers for aligning coefficients.

Table 4 - Coefficient orientation

The Alignment of coefficients of different size is both the encoder as well as the decoder known and has no influence on the Efficiency of the entropy coder.

Remarkable is that the Encoding units of the same record have different orientations can.

Arrange the Code stream and the context model

10 shows the ordering of the code stream and the ordering within a coding unit. If you take reference 10 , so follow the header 1001 the coding units 1002 in the order from the top band to the bottom. (The header or header 1001 is optional for applications designed for a single or unique image type.) Each encoding unit contains key data 1003 , less important data 1004 and least importantly data 1005 ,

The Context model determines both the order in which the data and the conditioning required for the specific bits of the Data is used. The ordering is considered first. The arranging the data regarding of the highest Levels have already been described above. The data is divided into "main data", what herein interchangeable as the most important part Batzen is called (MIC or "Most Important Chunk"), which is lossy in the transformation order is coded, and "less important data", herein interchangeable as the least important part or least significant chunks (LIC), and in an embedded unified lossless / lossy one Way is encoded.

The Order in which the coefficients are processed during each bit level be, running from the low resolution to the high resolution (from low frequency to high frequency). The coefficient subband coder running within each bit level from the high level (low resolution, low frequency) too the low level (high resolution, high frequency). Within each frequency subband the coding takes place in a defined order or sequence. In one embodiment can the order be a grid order, a 2x2 block order, a serpentine order, a peano-order ( "Peano scan order ") etc. act.

In the case of a four-level decomposition, where the code stream of the 3 is used, the order is as follows:
4-SS, 4-DS, 4-SD, 4-DD, 3-DS, 3-SD, 3-DD, 2-DS, 2-SD, 2-DD, 1-DS, 1-SD, 1 DD

A execution of the context model used in the present invention will be described below. This model uses bits within a coding unit based on the spatial and spectral dependence the coefficients. The available binary Values of adjacent coefficients and parent coefficients can be used to create contexts. The contexts are however for the decoding ability and in small numbers for efficient adaptation causally.

The The present invention provides a context model for the bitstream to be modeled by the coefficients in the embedded Bit significance order for the binary Entropiekodierer is generated.

37 shows the neighborhood coefficients for each coefficient of a coding unit. If you take reference 37 , the neighborhood coefficients are given obvious geographical names (eg N = north, NE = northeast, NW = northwest, W = west, E = east, SE = southeast, etc.). Are a coefficient, such as P in 37 Given a current bit-plane, the context model can use any information from the entire coding unit before the given bit-plane. The parent coefficient of the present coefficient is also used for this context model.

The header bits are the most compressible data. Therefore, a large amount of context or conditioning is used to improve compression. Rather than that the neighborhood or Parent coefficient values are used to determine the context for the present bit of the present coefficient, the information is used on two signaling bits associated with 13A are described. This information may be stored in memory or calculated dynamically from the neighborhood or parent coefficient.

To implement embedding for storage on a disc

A embodiment the embedding scheme for the present invention is based on the fact that when starting with the encoding of data, the entire tape buffer memory is full of data, so it no extra available Space in the tape for use as memory. The present Invention writes some of the less important data into the memory, The later to be embedded. In the present invention, the Data to be embedded in the memory, and this are the less important dates. The more important data becomes direct coded. The least important data include a certain amount Number of least significant bits.

at an embodiment a part of each coefficient is returned to the memory for later coding written, the head bits and the tail bits must be known, as well well, as you know, whether the sign bit is okay or the order or sequence processed according to was used to ensure correct coding. In one embodiment if two or more signaling bits (e.g., 3, 4, 5, etc.) are used, to display the header, tail and sign bit information.

at an embodiment, where 8-bit memory locations are used, two signaling bits show the Header, tail and sign bit information. the usage of two signaling bits allows the least important six importance levels back are written to the memory with two signaling bits. One Signaling bit indicates whether the most significant bit or most significant bits of the six importance levels a header or a Tail bit is. If the first signaling bit indicates that it is on Is the head bit, then the second signaling bit is the sign for the Coefficients. On the other hand, if the first signaling Bit indicates that most Bit of data, that back written to the memory is a tail bit, then that is second bit signaling a free signaling bit that an additional Tail information, such as whether the most important tail bit the first tail bit or a later one Tail bit is.

13A shows a coefficient in the main data 1301 called MIC and less important data 1302 , which are referred to as LIC, is divided. In one embodiment, the MIC comprises the six higher-order bits of each coefficient, while the LIC comprises the six lower-order bits. The most important data 1301 are sent to the context model to be coded immediately in a coefficient order. No buffering in external memory is required for this data. The less important data 1302 are written in memory (eg RAM) to be encoded later and embedded in this order. In addition, the two signaling bits in the data are written to memory. The signaling bit 1303 indicates whether the most significant bit in the data written to the memory is a header. The signaling bit 1304 indicates the sign for the coefficient or shows if the tail bit is included in the data or not. It is noteworthy that the signaling bits work in a concatenated manner with the less important data 1302 can be stored in memory or other memory location associated with the memory, the less important data 1302 so that the signaling bits associated with each section of a coefficient can be identified.

Examples in Table 5 show the use of two signaling bits. The columns of the body of Table 5 are intended to deal with the data types in the 13A align. The sign bits are denoted by "S", the tail bits are denoted by "T", the bits to be ignored are designated by "x", the value of the tail one bit is denoted by "h" or "t". In Table 5, h = 0 and t = 1 for the signaling bits. In an alternative embodiment, the conventions may be reversed. In one embodiment, a sign bit in Table 5 indicates 0 with a positive sign, while a sign bit in Table 5 indicates 1 with a negative sign. An opposite assignment can be used. It is noteworthy that the sign bit is always held with the first "on" bit, so that it can be coded for embedding at the same time.

Table 5

In Table 5 above denotes "T" the corresponding one Bit in the coefficient and can be either 0 or 1.

at an embodiment be while of decoding, when the most important data is decoded, they written in memory, and at the same time are the right ones two signaling bits written to the memory to the memory for the Save less important data to initialize. (Dependent on Of the orientation of the coefficients may be some of the most important Data in the second byte will also be stored.) With this Initialization requires decoding less important data with one bit level at a time just reading and then writing one byte (or less in some embodiments) per coefficient. When the coefficients are read, entered into the inverse transformation they are converted into a normal numeric form (e.g., two's complement form).

In addition to having "most important data" and "less important data", one can also omit or delete or quantize data during encoding. Coefficients are quantized by a quantization scaling factor 2 ^Q-1 . (The quantization of the coefficients is described in the JPEG standard.) In the present invention, the quantization represents a power of 2, since division is accomplished by omitting bit-planes. For example, Q = 1 represents a division by 1, and thus the coefficients do not change while Q = 2 represents a division by 2, which means that a bit plane has been eliminated. These divisions can be implemented by using shifts (eg a shift by one bit position for Q = 2). 13B and 13C show the format of the most important and less important data when considering both quantization alignment and coefficient alignment for different subbands.

13B shows the lossless case where no data is omitted or deleted. Following the convention of JPEG, it is called a quantization Q = 1 because the current coefficient is divided by 1 (lossless). The most important data is displayed without cross-hatching, while the least important data is cross-hatched.

13C Fig. 12 shows the case where a bit plane with data has been deleted (ie Q = 2) because the omission of a bit plane is equal to a division by 2. The omitted bit plane is shown in black.

It is noteworthy that in addition to what is in the 13B and C, the most important data also contains the SS coefficients. Although the coefficients for 8-bit data are shown, the use of a reversible color space would require 9-bit data, increasing the size of the chrominance coefficients by one bit.

In the present invention, the sign bit context model includes encoding the sign after the last header bit. There are three contexts for the sign, depending on whether the N-Ko efficiently positive, negative or the sign is not yet coded. Alternatively, a sign may be used for the sign, or the sign may always be encoded as 50%.

Order or order the coding for Wavelet coefficients

One embodiment of ordering coding for wavelet coefficients is summarized in the following pseudo-code:

If the main data being encoded will be the first bit plane in the less important data that does not consist entirely of zero overhead bits, for each Coefficients determined. this makes possible it's the encoder and decoder, over to ignore entire bitplanes of less important data. This is especially useful for coding units of black and white data, where all information in the K coefficients and the CMY coefficients are all zero are. A non-coding the bit planes individually helps a compression ratio, in particular, if R2 (7) is the longest run length code is that is available. (See U.S. Patent Nos. 5,381,145 and 5,583,500 for a description of the "R2" code.) However, if the four parallel coding cores work synchronously with components, the processing speed through the component with the most of the bit planes to be coded; Cores, the other components are assigned during unencoded bite levels idle.

A flowchart showing an embodiment of the operation of the above pseudo-code is shown in FIG 14 shown. If you take reference 14 Thus, the context model begins with the coding of the most significant part (MIC) (processing block 1401 ). After encoding the MIC, the processing logic encodes the position of the first LIC bit plane with data (processing block 1402 ), where LIC stands for the least important chunk or part. This applies to the entire coding unit. Either 0, 1, 2, 3, 4, 5, or 6 bit-planes will contain data if there are six bit-planes in the LIC. Then, the processing logic sets a current LIC bitplane variable to the first LIC bitplane with data (processing block 1403 ).

Next, a test determines whether all LIC bit planes have been encoded with data (processing block 1404 ). If so, the process ends; if not, the processing logic encodes a LIC bit plane (processing block 1405 ) and sets the current LIC bitplane variable to the next LIC bitplane (processing block 1406 ). Thereafter, the processing jumps to the processing block 1404 back.

Arrange the Coding for the most important data

An embodiment of the order for coding the most important data is as follows:

The most important data are processed for a wavelet tree or with one wavelet tree at a time. They are not embedded for re-iterating. An MIC lookahead determines bit-planes that are all zero-header bits for all non-SS coefficients in the wavelet tree. In one embodiment, a 4-bit number is sufficient to match the first bit-plane identify to individually encode. In an alternative embodiment, disclosed in U.S. Pat 15 is shown, one bit is used to indicate that all non-SS coefficients 1501 the second decomposition (hatched area) are zero, and another bit to indicate that all non-SS coefficients 1503 the first decomposition are zero. These two bits are used in addition to the four bits used to specify the first bit-plane.

at an alternative embodiment can a tree-predator ("tree lookahead "), where the SS coefficients are coded, and then for the whole Tree encodes the first bitplane with non-zero overhead bits.

Around a context re-entry delay to take into account if conditioning for SS and first bit-plane encoding can be used Encoding / decoding the bits of the SS coefficient (which is 9 bits if a reversible color space is used) and the predictor value be alternated. If conditioning is not used, then no alternation required.

• • Eine M-ary-Operation, um den Wert und das Vorzeichen eines Koeffizienten zu bestimmen. (Insgesamt: 2 Zyklen pro Koeffizient)
• • Eine adaptive Kodierungsentscheidung wird verwendet, um "±1/nicht ±1" zu entscheiden. Ein zweiter Zyklus wird verwendet, um das Vorzeichen mit dem Betrag gleich 1 und das Vorzeichen und den Wert für die Beträge größer als 1 zu bekommen. (Insgesamt: 3 Zyklen pro Koeffizient)
• • In ähnlicher Weise kann "±1/nicht ±1", "±2,3/nicht ±2,3" usw. für insgesamt 4 Zyklen pro Koeffizient durchgeführt werden.
• • Das folgende Verfahren:
  
  

As previously discussed, the contextual model of the present invention uses a predictor. An embodiment of the prediction or foresight can be used for the most important data, ie the most important parts (MIC). In one embodiment, as in 15 6 bits are used for each tree: 4 for a maximum bitplane, 1 for level 0 all zero, 1 for level 1 all zero. If the maximum bit-level is zero, then the two extra bits become redundant, but this is not important. Otherwise, an adaptive coding decision is used to decide "isolated zero / not zero". For non-zero coefficients, they can be further specified by the following:

• • An M-ary operation to determine the value and sign of a coefficient. (Total: 2 cycles per coefficient)
• • An adaptive coding decision is used to decide "± 1 / not ± 1". A second cycle is used to get the sign with the amount equal to 1 and the sign and the value for the amounts greater than 1. (Total: 3 cycles per coefficient)
• • Similarly, "± 1 / not ± 1", "± 2.3 / not ± 2.3", etc. can be performed for a total of 4 cycles per coefficient.
• • The following procedure:
  
  

Remarkable is that "specifying" a bit or of bits may be adaptive coding, coding with 50% probability or simply encoding bits to the encoded data stream.

If all or most of the bit-planes are to be coded individually can some levels of transformation due to unused bit planes to have an orientation - unused Bitplanes are never encoded. There are a number of options for handling a bit-to-context delay for the header and tail bits. One method is to do three coefficients alternately. One DD, an SD and a DS. The sign bit for non-zero coefficients can be coded at the end of the coefficient - since all the most important data always lossless, an exact following of the first "on" bit is not necessary.

An embodiment of a flowchart showing the pseudo-code for coding the most important part is shown in FIG 16 shown. If you take reference 16 Thus, the process begins with the process logic setting the current tree to the first tree (processing block 1601 ). Then, the processing logic encodes the SS coefficient (processing block 1602 ). After encoding the SS coefficient, the processing logic encodes the position of the first bit plane with data in the MIC of the tree (Processing block 1603 ) or performs the MIC Predictor.

Then the processing logic tests whether the MIC of the whole tree is zero (processing block 1604 ). If the MIC of the whole tree is zero, processing proceeds to the processing block 1614 continue; otherwise the processing goes to the processing block 1605 where the processing logic sets the current coefficient to the first non-SS coefficients in the tree.

After setting the current coefficient to the first non-SS coefficient in the tree, the processing logic sets the current bit-plane to the first bit-plane with data (processing block 1606 ). Then, the processing logic encodes one bit of the current coefficient in the current bit plane (processing block 1607 ). Thereafter, the processing logic tests whether all bit-planes have been coded (processing block 1608 ). If all bit planes have been coded, the processing logic sets the current bit plane to the next bit plane (processing block 1609 ) and goes to the processing block 1607 above. If all bit-planes have been encoded, the processing logic tests whether the current coefficient is zero (processing block 1610 ). If the current coefficient is not zero, the processing logic encodes the sign bit (processing block 1611 ) and the processing goes to the processing block 1613 above. If the current coefficient is zero, then the processing logic goes to the processing block 1613 above.

At the processing block 1613 the processing logic tests whether all coefficients in the tree have been coded. If all the coefficients in the tree have not been encoded, then the processing logic sets the current coefficient to the nearest coefficient in the tree (processing block 1612 ) and the processing goes to the processing block 1606 above. If all the coefficients in the tree have been encoded then the processing logic tests if all trees have been encoded (processing block 1614 ). If all trees have been encoded, processing ends; otherwise the processing goes to the processing block 1615 across where the processing logic sets the current tree to the next tree and processing goes to the processing block 1602 above.

17 Figure 10 is a block diagram of one embodiment of the formatter and a context model used during the most important data encoding run. If you take reference 17 so is a barrel shifter ("barrel" slider) 1701 to receive the magnitude of the coefficient and a quantization level used during encoding to prevent the most important data from exceeding the minimum disk bandwidth, thereby ensuring lossless decompression. Thus, the quantization level controls the barrel slide 1701 , In one embodiment, the barrel pusher shifts 1701 the magnitude bits around 0, 1, 2, or 3 to support quantizations 1, 2, 4, or 8. In an alternative embodiment, a lower or higher number of quantizations is supported, such as only two quantizations.

The issue of the tons slider 1701 includes the six lower-level bit-planes, which are the less important data, and the remainder of the higher-order bits, which are the most important data. In an alternative embodiment, a simple separation mechanism is used to generate these two outputs.

Both issues of the barrel slider 1701 become the first bitplane unit 1702 which determines which bit-planes have data in them. The first bit level unit 1702 is used to find the bit plane with the first "on" bit for the whole coding unit (see 10 ) for use when processing the less important data. Another bit level unit 1706 is connected to the main data by a barrel slider 1701 be issued, as well to receive. The first bit level unit 1706 is used for each tree as the more important data is processed. An embodiment of the first bit plane unit will be described below with reference to FIG 18 described.

The barrel slider 1701 is also to the comparison unit 1703 and 1704 which make two comparisons with the most important data to produce the two-bit signaling information for the less important data. The comparison unit 1703 determines if the most important data is 0, thereby indicating whether a tail bit has already occurred (ie, whether the encoding is still in the tail). The output of the comparison unit 1703 is the tail-a-bit. A comparison unit 1704 determines if the most important data is equal to 1. If the most important data is 1, then the output from the above table 5 is 0. The output of a comparison unit 1704 is connected to one input of the multiplexer (MUX) 1705 connected. The other input to the multiplexer 1705 is connected to receive the sign bit. A selection input from the multiplexer 1705 is through the output of a comparison unit 1703 controlled so that, if the output of the comparison unit 1703 indicates that the bit is a tail bit, then the output of the multiplexer 1705 a "first tail" bit 1304 is. However, if the output of the comparison unit 1703 indicates that the bit is the header, then becomes the multiplexer 1705 controlled to output the sign.

In one embodiment, the comparison units 1703 and 1704 can be implemented by using simple bit comparators.

A store 1707 is connected to the sign bit, the main data coming from the barrel slider 1701 and the output of the bit-plane unit 1706 to recieve. The memory 1707 is used to delay coefficients so that parent and neighborhood information is available for conditioning. The organization of the store 1707 will be discussed below.

Context models (CM) 1710 - 1712 Provide conditioning for the sign, head, tail, and other bits. Each of these context models is described below.

18 shows an embodiment of a bit-plane unit. If you take reference 18 , so the first bit plane unit comprises 1800 an OR gate 1801 , which is connected to a coefficient and a feedback from the output of a register 1802 to recieve. The output of an OR gate 1801 is at the entrance of a register 1802 connected. The registry 1802 is controlled by a start of a Tree / Encoder Reset Display. The output of the register 1802 is at a priority encoder 1803 connected. The output of the priority encoder 1803 is the output of a first bit plane unit 1800 ,

When starting the register 1802 deleted. Every bit of a register 1802 is ORed with each bit of the input coefficient, with the OR gate 1801 is used. For each bit of the coefficient that is 0, the value of the register remains 1802 its current value, which is output to the priority encoder. For each bit of the coefficient that is a 1 (eg, the first one), the output of the OR gate 1801 to the register 1802 1, resulting in the priority encoder 1803 is issued. The priority encoder 1803 then locates the first 1, which is the first bit plane of the coefficient that has a 1.

Order or order the processing for less important data

Each bit-level for the least important data is processed as follows:

One embodiment of the processing of encoding a LIC bitplane is shown in the flowchart of FIG 19 shown. The processing of encoding a LIC bit plane begins with the processing logic determining the current tree to the first tree (processing block 1901 ). Then, the processing logic sets the current coefficient to the first non-SS coefficient in the tree (processing block 1902 ). After setting the current coefficient to the first non-SS coefficient in the tree, the processing logic tests whether encoding is at the start of a foresight interval (processing block 1903 ). If the coding process is at the start of a predictive interval, the processing logic performs foresight (processing 1904 ) and the processing proceeds to the processing block 1905 continued. If the coding process is not at the start of a predictive interval, the processing logic goes directly to the processing block 1905 over and determines whether foresight is active.

If look ahead is active, processing proceeds to the processing block 1909 where the processing logic determines if all coefficients in the tree are encoded. If all the coefficients in the tree are encoded, processing proceeds to the processing block 1913 continue; otherwise, the processing logic sets the current coefficient to the nearest coefficient in the tree after the look-ahead interval (processing block 1910 ) and the processing goes to the processing block 1903 above.

If foresight is not active, the processing logic encodes the header or tail bit (processing block 1906 ) and then tests to see if the first non-zero bit has been received (processing block 1907 ). If the first non-zero bit has not been received, processing proceeds to the processing block 1911 continued. If the first non-zero bit has been received, processing proceeds to the processing block 1908 where the processing logic encodes the sign bit and processing then passes to the processing block 1911 above.

At the processing block 1911 the processing logic determines if all the coefficients in the tree have been encoded. If all the coefficients in the tree have not been encoded, the processing logic sets the current coefficient to the nearest coefficient in the tree (processing block 1912 ) and goes to the processing block 1903 above. If all coefficients in the tree have been encoded, processing transfers to the processing block 1913 over where the processing logic tests if all trees have been encoded. If all trees have not been encoded, the processing logic sets the current tree to the next tree (processing block 1914 ) and the processing proceeds at the processing block 1902 continued. If all trees have been encoded, processing ends.

The Processing a wavelet tree at a time may not matter but because the transformation causes data in that order or Order can be read and written, it may be appropriate. If the data is processed by wavelet trees can be adapted to a bit-to-context delay be alternated by alternating DD, SD and DS coefficients (Alternate between subtrees). Otherwise, a subband can be encoded at one time. regardless the chosen one Order becomes unused header / tail bits due to alignment different subbands never coded and do not require idle or unproductive cycles.

20 Figure 13 is a block diagram of an embodiment of the predictor and counter models for less important data. In one embodiment, the most important data and the less important data use the same context models (CM) that provide conditioning for the sign, head and tail bits.

If you take reference 20 , so are contextual models 2001 to 2003 connected to the input data. A sign context model 2001 is connected to receive the tail-a-bit, a sign / first-tail bit signal and the data. The header contextual model 2002 is connected to receive the tail-a-bit and the data. The tail bit context model 2003 is connected to receive the tail-a-bit, a sign / first-tail bit signal and the data. In response to their inputs, each context model generates 2001 to 2003 a context. The mentioned "first tail bit" may also be referred to as "first tail bit".

The contexts created by the contextual models 2001 to 2003 are generated, to the inputs of the multiplexer 2004 connected. The multiplexer 2004 is controlled by the preceding bits and the bit significance representation itself. The head context model 2002 is used until a 1-bit is seen at the data input. The sign context model 2001 is used if the last bit was the first 1-bit of the head. After that, the tail context model becomes 2003 used.

The output of the multiplexer 2004 is to the "= head?" unit 2005 and the first-in / first-out (FIFO) buffer 2006 connected. The "= head?" Unit 2005 tests whether the current context is a header bit context with zero headers in the neighborhood and parent. If all contexts are in the header, clear a signal from the "= head?" Unit 2005 the FIFO 2006 ,

The contexts and results are in the FIFO 2006 or buffered in the memory for the Predictor interval. At the end of the interval, if necessary, a predictor's decision and / or individual decisions are encoded. If the coefficients are processed with a wavelet tree at a time, the FIFO foreseeing may be a single FIFO used for all subbands, or multiple FIFOs may be used, one for each subband.

Remarkable is, if appropriate, to reduce the multiplexing, the most important data predicting could also use. However, it can be somewhat redundant, both anticipation and a first bit level for to use every tree.

If a core assigned to a component encodes a sign bit, cores assigned to any other components that do not match a sign bit at the same bit level become co-efficient to be inactive, idle or unproductive. Therefore, up to four clock cycles can be used for sign bits if each core encodes a sign bit at a different bit-level. In one embodiment, there are up to six head or tail bits per coefficient.

One potential Timing problem is that the most important part or chunk compressed sufficiently well, so that the disc or plate during the decoding of a portion of the data is idle or unproductive. if it there is sufficient memory bandwidth for the band buffer A foresight can be used to get the most important data fast to process. Then can the less important data get a head start or a head start. Likewise would be it's good if the disk has a burst transfer rate or a discontinuous transmission rate would have, the higher would be considered the maximum sustained rate. Hard drives usually have a significant buffer on and maybe a pre-reading in this buffer the useless or eliminate unproductive time.

Condition part of the contextual model

The Conditioning, which is used in the context model depends on the hardware costs or the hardware costs compared to the Compression compromises. Therefore, in the following sections Many conditioning options are presented by Designers can be considered.

context model for SS coefficients

at an embodiment of the context model, SS coefficients are not encoded. As she only 1/256 of the original Make data leads their coding only for a small profit. If you are coding required is, can they by a Gray coding, conditioning on the previous bit in the same coefficient and / or to a corresponding bit in the previous coefficient be handled.

context model for first bit level information

The four bits of the first bit plane information for the first one Bite level for The most important data of each wavelet tree can be similar to the SS coefficients be treated. They increase the size of the original data only at 1/512. In one embodiment can they are uncoded on their small size compared to the original one Data remain or undergo a Gray coding or other conditioning.

Similarly, if six bits according to 15 can be treated as SS coefficients.

context model for head bits

21 Figure 10 is a block diagram for one embodiment of the context model providing header bit conditioning. If you take reference 21 so contains the context model 2100 Shift registers similar to those found in a bit-level context model. An important difference is that instead of using previous coefficient bits from the current bit-plane, conditioning is based on tail-on information that uses all previous bit-planes and the previously encoded information in the current bit-plane. Likewise, some bits for identifying the coded bit plane or group of coded bit planes and the subband or group of coded subbands are generated from the level of importance and subband bucketing (guess-like).

If you take reference 21 Thus, the context model includes two inputs, the current level of significance 2110 and the coefficients from memory 2111 , The current significance level 2110 is with the inputs to the tail-an-information-bit-generator (s) block 2101 and the importance level and subband storage area formation blocks 2102 The memory formed in particular contains data for an application and the process of the storage area formation is also referred to as a "bucketing" block and can also be understood as a variable assignment. The coefficients from the memory are also used with the block 2101 and the register 2103 to 2106 connected.

The block 2101 takes the coefficients and determines if there is a bit or not. Determined in one embodiment 2101 as well, from where that is one bit. The output of the block 2101 make one or two Bits that are based on the tail-on information. In one embodiment, the tail information establishes a relationship as to whether or not the first non-zero magnitude bit has been observed (eg, whether the first "one bit" has been observed) and, if so, how many Bitebenen this is about ago. Table 6 describes the tail information bits.

Table 6 - Definition of tail information

From For the 2-bit tail information, a 1-bit "tail-on" value is synthesized to indicate whether the tail information is zero or not. In one embodiment the tail information and tail-a-bits are updated, immediately after the coefficient has been coded. At a another embodiment an update occurs later to allow parallel context generation.

In addition, the two bits are used to indicate that the importance level is coding has been. The first two bit planes use the value 0, the second two 1, the third two 2 and the remaining bit planes 3. In addition there it's a run length encoding the bits that are all zero-head bits.

The 10 bits of context for the header bits contain the 2 bits of information, each from the parent and the west coefficient, 1 bit of information each from the north, east, southwest and South coefficients and 2 bits of the importance level information.

at an embodiment the tail information is not used for some or all frequency bands. this makes possible it, that one Frequency band is decoded without first decoding its parent.

In one embodiment, the assignment of the bit-planes of each frequency band to the importance levels uses an alignment. Parental tail information determination uses a second alignment that uses fewer bit planes of the parent than has actually been encoded. This allows some bit-planes of a frequency band to be decoded without decoding the corresponding bit-planes of the parent at the same level of nullity (see 38 ). For example, an image may be encoded with a pyramidal orientation, but the parent tail information is based on MSE alignment (see 39 ). This allows the decode to decode a pyramidal orientation, to simulate MSE alignment, or to simulate any alignment between pyramidal and MSE.

If you take reference 21 so are the outputs of the block 2101 with the inputs of the registers 2103 to 2106 coupled. The registers 2103 to 2106 accumulate the neighborhood data. For example, the upper / left shift registers maintain bits during the line that is just above the current coefficient. The current shift register contains the bits of the current line of coefficients, while the lower / right shift register 2105 contains the lines of the line just below the shift register. Finally, the parent keeps register 2106 the parent data upright. The outputs of the shift registers form the context.

The output of the importance level and the bucketing block 2102 can also be used for a context. This would be part of the context if the subbands and different levels are to be coded to the same context. If so, the output is from the block 2102 with the outputs of the registers 2103 to 2106 connected to form the context. If not, the context includes only the outputs of the registers 2103 to 2106 ,

Likewise, the output is from the context model 2100 one bit.

One Coding can be done be alternated by alternating between DD, SD and DS coefficients, around the bit-to-context delay to allow use of data from the current bit-plane (where between subtrees is alternated).

It is noteworthy that the memory is needed to store coefficients needed for conditioning (see 17 ). The memory usage for one embodiment of the context model with conditioning of all neighbors and parents is in 22 shown. A short hem-transformation order is assumed. (An external memory can be used to support a long seam transformation order, which would require both additional memory space and additional bandwidth.) Conditioning high-level parenting is particularly expensive. The level 4 DD coefficient for a given tree is not calculated up to 16 trees later than most of the level 1 DD coefficients for that tree. Likewise, storing whole coefficients to be encoded later (unshaded in 22 ) much more than just storing tail information for later use in conditioning (crosshatched in FIG 22 ). Conditioning only the "West" information, which is the same tree, and the parent generated without data from "West" trees would significantly reduce the amount of memory required. If a parent or West information was not available, copying the information from the north or east is useful.

context model for sign bits

The Context model that provides conditioning for sign bits is easy. If the sign of the above pixels is known, then it for used the conditioning. If the sign bit for the above Pixel is unknown then the uncoded bit (R2 (0)) is used. Alternatively, no coding (R2 (0)) can be used for all sign bits become.

23 Figure 4 is a block diagram of one embodiment of the sign bit context model. If you take reference 23 , so receives a multiplexer 2301 a north sign bit 2303 and a 0-bit 2304 (wired) and is by a north tail-a-bit 2302 controlled to the north sign bit 2303 if the north tail is a bit 2302 a 1 is; otherwise there is the multiplexer 2301 a 0 off. Thus, the north pixel provides the north tail-a-bit 2302 and the north sign bit 2303 to provide a context for the pixel south of the north pixel.

context model for tail bits

It will not be conditioned for Tail bits used. In one embodiment, a fixed probability state used and no probability update is used. Table 7 shows three options for Codes for tail bits to be used. The second option, which uses R2 (1) and R2 (0), is a good choice.

Table 7 - Probability states (codes) used for tail bits

In one embodiment, the code according to a golden ratio ("Golden Ratio" code) that is good for probabilities of M ≅ 60%, L ≅ 40% is as follows: input codeword MMM 00 MML 110 ML 01 LM 10 SS 111

Kontextbin Summary

The minimal number of context bins used in the system could are as follows. SS, first bit level for each tree, sign and Tail bits are all not encoded (the code used is R2 (0)). Although not a PEM state or a bit for a most likely Symbol (MPS) or an MPS bit, it must be a Give logic to select the R2 (0) code.

Therefore is the hardware cost depending of how this counted becomes, null, or a context bin. Adaptive coding should be for header bits be used. For less important data is because one bit level encodes at a time does not matter, conditioning the bit-plane. For the most important Data may be the first bit level for sufficiently reduce the number of bit planes for each wavelet tree, so that conditioning the Bite level is not important. It is less clear what the usefulness the conditioning of the subband represents, but this will too be ignored in this minimal context example. The tail-a-bits of these three neighbors and one parent could be for a total of four bits (16 context bins) be used. An additional Context bin can for a forerunner or for a foresight can be used. (It may be appropriate map the two head context bins together to make room for anticipation to do so that the Memory size always is still a power of 2)

With four cores (which requires a fourfold replication of contexts power) and two context memory banks per core would the minimum number of context bins to use between 128 and 144, depending on of it, like "not coded "contexts counted and whether two header context bins are mapped together or be matched by picture.

• • Für SS (9-Bit) und eine erste Bitebene (4 Bit) verwende 4 Kontextbins pro Bit, für insgesamt 52 Kontextbins (dies könnte in Bänke aufgeteilt werden, sie müssen nicht dupliziert werden).
• • Schwanzbits werden nicht kodiert, aber sowohl R2(0) und R2(1) werden verwendet. In Abhängigkeit davon, wie sie gezählt werden, kostet dies 0,1 oder 2 Kontextbins.
• • Zwei adaptive Kontexte und ein "Kein-Kode"-Kontext werden für die Vorzeichenbits verwendet.
• • Die Kopfbits können 8 Bits von Nachbarn/Elternteil und 2 Bits für Unterband-/Bitebenen-Information verwenden (1024 Kontextbins).
• • Ein Kontext wird für Vorhersehen verwendet.

A system with a lush conditioning scope is as follows:

• • For SS (9-bit) and a first bit-level (4 bits) use 4 context bins per bit, for a total of 52 context bins (this could be split into banks, they do not have to be duplicated).
• • tail bits are not encoded, but both R2 (0) and R2 (1) are used. Depending on how they are counted, this costs 0.1 or 2 context bins.
• • Two adaptive contexts and a "no-code" context are used for the sign bits.
• The header bits can use 8 bits of neighbor / parent and 2 bits for subband / bitplane information (1024 context bins).
• • A context is used for predicting.

A alternative embodiment including a contextual model an embodiment a sign / amount unit, the input coefficients in a Signed / Amount converted, is in the US patent application No. 08 / 498,695, filed June 30, 1995, entitled "Method and Apparatus for Compression Using Reversible Wavelet Transforms and Embedded Codestream "and the US patent application No. 08 / 498,036, filed June 30, 1995, entitled "Reversible Wavelet Transform and Embedded Codestream Manipulation "and also in the US patent application No. 08 / 642,518, filed May 3, 1996, entitled "Compression and Decompression with Wavelet Style and Binary Style Including Quantization by Device Dependent Parser ", and the U.S. Patent Application No. 08 / 632,248, filed May 3, 1996, entitled "Compression / Decompression Using Reversible Embedded Wavelets ".

The Context model provides contexts for Entropy coding of the data. In one embodiment, entropy encoding is performed by the present invention is performed by binary entropy coders. One single encoder can be used to provide a single output code stream to create. Alternatively you can multiple (physical or virtual) encoders are used to generate multiple (physical or virtual) data streams.

M-ary encoding for LIC

24 shows the use of M-ary encodings for the LIC. The use of M-ary for reduced coding works as a forerunner (as shown). First, the state of the next eight Coefficients examined. If there is anything in the header, entropy coding is performed on the header bits so that all header bits, one per cycle, are entropy encoded until all header bits are encoded at the eight coefficients. If you take reference 24 Thus, the header bits, which are 1, are encoded in the first and third cycles, while the header bits, which are 0, are encoded in the second and fourth cycles. Once the head bits are entropy coded, the sign and tail bits are coded in the same cycle. For example, in 24 all sign and tail bits following a header bit that is 1 are encoded in the fifth cycle. In this way, the total number of cycles is reduced.

A printing system application of the present invention

25 Fig. 10 is a block diagram of one embodiment of the front end of a printer. If you take reference 25 Thus, a renderer receives data in the form of a page description language (PDL) or a display list. The dresser 2501 may include raster image processing. For each position (eg every point or spot) the conditioner determines 2501 its color (eg black and white, 8-bit RGB values, 8-bit CMYK values depending on the application). The edition of the conditioner 2501 represents a set of pixels that are formatted in bands and in a tape buffer (memory) 2503 are stored.

In an alternative embodiment, data of a page description language (PDL), such as Adobe PostScript ^® or Microsoft ^® Windows GDI, treated to a display list or in a display list. The display list or display list is used to generate bands of pixels. In this embodiment, it is assumed that the pixels represent continuous tonal values, and any halftone processing or dithering required by the printing press is performed after decompression.

In the present invention, the memory allocated to the band buffer 2503 is used as well as working space used for compression (without increasing the required memory). This dual use will be described in more detail below.

The compressor 2504 compresses each band of pixels. If the input of the compressor 2504 Halftone or dithered pixels, the compressor would 2504 Still working, but the compression achieved would probably be bad with wavelet processes. A binary context model can be used with halftone or dither pixels. The compressor 2504 writes the compressed data to the disc 2505 , The disc or plate 2505 can be a hard disk. In an alternative embodiment, the disk may be the same 2505 a random access memory (RAM), a flash memory, an optical disk, any type of memory device, or any type of communication channel.

26 Figure 10 is a block diagram of one embodiment of the rear end of the printer. If you take reference 26 so includes the back end of the printer 2500 a decompressor 2602 to the disk or disk 2505 , a band buffer (memory) 2603 and a printing press 2604 connected. The decompressor 2602 reads compressed data from the hard disk 2505 and decompress it. The decompressed data is stored in the tape buffer (memory) 2603 stored in the form of pixels. In the band buffer 2603 it can be the same memory as the tape buffer 2503 act as a working space for the compressor 2504 to work. The decompressor 2602 holds the tape buffer 2603 sufficiently full, so that the pixels to the printing press 2604 can be sent in real time.

27 FIG. 12 illustrates an alternative embodiment that includes an optional enhancement. If you take reference 27 , so pixels run from the decompressor 2602 to the tape buffer 2603 about a block of improvement 2705 while some other information, which is the information that is not yet pixels (sub-coefficients), goes directly to the band buffer 2603 is sent. A block of improvement 2705 can perform such functions by interpolation, smoothing, error diffusion, halftoning and / or jitter processing.

The required bandwidth between the decompressor 2602 and the tape buffer 2603 allows the decompressor 2602 First, the transform coefficients to the band buffer 2603 to write on the tape buffer 2603 to get certain coefficients and perform the inverse transform with such coefficients and then back to the band buffer 2603 to write. It is noteworthy that the band buffer 2603 as a working memory can be small. For example, if a full page image is 64 megabytes and a tape buffer 2603 16 megabytes, it would still be considered a small memory.

In one embodiment, 400 dpi 32-bit / pixel (four 8-bit components, CMYK) A4 images require about 8 pages / minute data rate of about 8 Mbytes / s from the band buffer 2603 to the printing press or to the printer 2604 , The transfer rate of an exemplary hard disk is about 2 Mbytes per second (eg 1.7-3.5 Mbytes / s). Therefore, a typical compression rate of about 4: 1 is required to reduce the bandwidth of the disk 2601 to adapt to the bandwidth of the printer. In one embodiment, the compressor is 2504 in the 25 and the decompressor 2602 in the 26 or 27 contained in a single integrated circuit chip.

28 Figure 12 is a block diagram of one embodiment of an integrated circuit (IC) chip that includes printer compression / decompression. If you take reference 28 so is the pixel data interface 2801 connected to the band buffer (not shown). The pixel data interface or the pixel data interface 2801 is connected to the band buffer (not shown). The pixel data interface 2801 generates addresses for reading and writing the pixels from and to the band buffer, respectively. An optional reversible color space 2802 can be included to perform a reversible color space conversion. The coefficient data interface 2804 generates addresses for reading and writing coefficients and correctly assembles two byte coefficients. The coefficient data interface 2804 handles together with the pixel data interface 2801 any line buffers or coefficient buffers required in external memory. The coefficient data interface 2804 and the use of a reversible color space will be discussed in more detail below.

Remarkable is that the Double arrows imply that the Data flows in both directions can. For example, when compressing the data, the data moves from left to right through the various components of the IC chip. On the other hand, when the data is compressed, the data generally from right to left.

When the data is encoded, the pixel data from the pixel data interface 2801 or the reversible color space 2802 (if included) from the wavelet transform block 2803 received, which performs the wavelet transform with the pixel data. In one embodiment, the transform provided by the wavelet transform block 2803 is an overlapped wavelet transform. It provides energy compression for both lossless and lossy image compression. For lossy compression, the block boundary artifacts, the JPEG plagues, are avoided. The filter coefficients are normalized, if properly aligned, for scalar quantization to provide good results in lossy compression. In one embodiment, the wavelet transform block performs 2803 a 2,6 transformation through. In another embodiment, the wavelet transform block results 2803 a 2,10 transformation by. The wavelet transformation block 2803 can perform other well-known transformations. Various implementations of the wavelet transformation block 2803 will be described in more detail below.

The coefficient output from the wavelet transform block 2803 may be written back to the memory (eg, the band buffer) via the coefficient data interface 2804 for later coding. In one embodiment, the data that is written back to the memory is less important data and will be described in more detail below. Such data is later read back into the IC chip and encoded.

The coefficients generated by the wavelet transform block 2803 be output or via the coefficient data interface 2804 are received, the context model 2805 provided. The context model 2805 provides the context for encoding (and decoding) data using the encoder / decoder 2806 , In one embodiment, the context model supports 2805 sending data directly for encoding. In this way, the context model works 2805 as the most important context model. An architecture for implementing various context models has been described above.

In one embodiment, the encoder / decoder comprises 2806 a high-speed parallel coder. The high speed parallel coder handles different bits in parallel. In one embodiment, the high speed parallel encoder is implemented in a VLSI hardware or a multiprocessor computer without sacrificing compression performance. One embodiment of a high speed parallel coder which can be used in the present invention is described in U.S. Patent No. 5,381,145, entitled "Method and Apparatus for Parallel Decoding and Encoding of Data", issued January 10, 1995.

at alternative embodiments comprises the binary Entropy encoder either a Q-encoder, a QM encoder, a FSM Encoder, etc. The Q and QM encoders are well known and available efficient binary Entropy coder. The FSM coders provide the simplest conversion from a probability and an outcome to a compressed one Bitstream. In one embodiment The FSM encoder is realized by looking up both lookup tables for one Decoder and a coder can be used. A variety of probability estimation can be used in such a FSM encoder. In one embodiment comprises the FSM encoder of the present invention includes a B-coder incorporated in U.S. Patent No. 5,272,478, entitled "Method and Apparatus for Entropy Coding", issued to December 21, 1993, is defined.

The output of the encoder / decoder 2806 is with the interface 2807 for encoded data providing an interface to the disc or other storage medium or even another channel.

the interface 2807 For encoded data, encoded data is sent and received from the disk. In one embodiment, if the SCSI controller or controller is included in the chip, it may be implemented at that location. In another embodiment, the interface is 2807 for encoded data, connect to an external SCSI controller. Non-SCSI memory or communication can be used.

During decompression, encoded data is output from the encoder / decoder 2806 from the disk (or other memory or channel) via the interface 2807 for encoded data and decompressed in it, using contexts from the context model 2805 be used. The coefficients that result from decompression become inverse through the wavelet transform block 2803 transformed. (It is noteworthy that, although a wavelet transform block 2803 performing both forward and inverse transforms in one embodiment, in other embodiments, the two transformations may be performed by separate blocks.) The output of the transform block 2803 includes pixels that undergo any optional color space conversion and those to the band buffer via the pixel data interface 2801 be issued.

The basic timing of the system during printing is in 29 shown. If you take reference 29 Thus, the encoded data from each encoding unit is read from the disc. As much data as possible is read and after a short delay coefficients are decoded. After the decoding is completed, the inverse wavelet transform is calculated. After the transformation is completed, the pixels can be sent to the printing device. It is noteworthy that the cross hatching in 29 indicates when various actions occur for a specific encoding unit.

Embed of coefficients for storage on a disk

10 shows the organization of the coded data in the present invention. If you take reference 10 so be the most important data 1003 encoded in coefficient order (not embedded) immediately after they have been transformed. Therefore, these data do not need to be buffered. In one embodiment, the scope of the most important data 1003 so limited that it can always be read from the disk.

A certain amount of less important data 1004 is buffered, embedded and written to the disk in the order of importance. The amount of data that can be buffered, embedded, and written is determined based on the transmission time. That is, the system reads the data until the transfer time from the disk is exhausted. The transfer rate of the disc determines how much data is retained. These rates are known and dependent on physical characteristics of a particular transmission.

For images that are difficult to compress, some data may be omitted during the encoding time. The data is considered the least important data 1005 shown. In the case where there is no possibility that the least important data can be read on the assumption of the best possible disk transfer rate, there is no reason to store that data on the disk. For many and perhaps most images, no data would be deleted or deleted.

The Ordering of coded data and how it is accomplished is described in more detail below.

in the Following is the band buffer management during compression and decompression followed by a description of the embedding scheme for the coded data. Hardware implementations of the transformation, the Contextual model and parallelism with the encoder / decoder are also described.

Pixel and Coefficients interfaces

30 Figure 1 shows one possible embodiment of how pixel data is organized. If you take reference 30 , so one page (picture) 3000 in ribbons 3001 to 3004 divided up. In one embodiment, the page 3000 a page description language or display list description of a page used to generate pixels for each band. In one embodiment, each band 3001 to 3004 individually rasterized using ad-list technology. Every band 3001 to 3004 is further divided into coding units (eg 3001A -D).

One Advantage of using multiple encoding units per band, that sections the tape buffer in rotation or rotating as memory during the Decompression (similar the ping-pong buffers). In other words, one Part of the pixels may be decompressed, stored in the tape buffer and sent to the printer while a second part of the Bandbuffers can be used as memory to coefficient to save while is decoded using a third part of the buffer, to store the pixels corresponding to the coefficients.

31 shows a band buffer 3101 the side 3100 , The tape buffer 3101 includes coding units 3001A -D. The coding units 3101a and 3101b act as a memory for the decompressor to store coefficients. The coding unit 3101C stores pixels to be output to the printer (or channel) while the encoding unit 3101D works as a work space for the decompressor by storing the next pixels.

The sections of the tape buffer 3101 can be used in rotation when the whole page 3100 is printed. For example, for the next encoding unit, the pixels are in the encoding unit 3101D the pixels to be output to the printer. When this occurs, the encoding units become 3101b and 3101C used as a work space for the decompressor to store coefficients. Likewise, at that time, a coding unit 3101a used as memory for the decompressor to store the next pixels to be output to the printer.

at In the present invention, the coefficients are larger than the pixels. Therefore, twice as much memory becomes the workspace memory assigned. In an alternative embodiment, the Ribbons in more or less coding units are split. For example can in one embodiment the bands divided into eight coding units each.

Memory Bandwidth

Together manage the pixel data interface and the coefficient data interface the tape buffer efficiently. If a fast-page mode DRAM, an EDO DRAM or other memories are used, one after the other Favor access, then transfer these interfaces receive data from consecutive addresses in sufficiently long bursts to the potential bandwidth of the memory efficient to use. Some buffers may be needed to handle bursts or discontinuous accesses to successive addresses to support.

32 FIG. 12 is a timing diagram of decoding showing memory access requirements for concurrent memory access. FIG. If you take reference 32 Thus, the bandwidth required for decoding is as follows. Recall that in one embodiment, a 2 MHz pixel clock, an 8 MHz component clock, and a 32 MHz decoder clock were used and that the printer requires 1 byte / component clock, the transform reads two bytes per coefficient and writes Byte per component. If the transformation is performed in half the encoding unit time, this would require a 6 byte / component clock. The speed of the transformation is limited by the memory bandwidth, not the computation time. If a bandwidth of a 24 byte / component clock is available, the transform can be calculated within one eighth of the encoder unit time. The transformation may require extra bandwidth if external memory is used for seams. In one embodiment, encoding coefficients requires writing of two bytes per component clock for the most important part of the encoded data. Decoding requires reading and writing one byte per component clock for each bitplane of the less important part of the encoded data. It should be noted that in some embodiments this may be less. Bandwidths of 4 bytes per component clock and 24 bytes per component clock would respectively be required if both operations require half the encoder unit time. Additional bandwidth may be required if external memory was used for context seam information.

at an embodiment is the maximum burst mode transmission rate four memory accesses per component clock (one access per encoder clock). Therefore, for a 32-bit data bus, the maximum transfer rate slightly smaller than 16 bytes / component clock. With a 64-bit data bus is the maximum transfer rate slightly less than 32 bytes / component clock.

reduction LIC memory bandwidth requirements

each Bit of each coefficient in the LIC requires reading and writing of the external memory during of decoding (encoding only requires reading). These Memory accesses make up the majority of the required memory bandwidth out. In one embodiment stores the present invention instead of having each LIC coefficient in 8 bits stores the coefficients, with less than 8 bits, if possible, used to reduce the bandwidth requirements.

• * Geschrieben während der Verarbeitung des wichtigsten Teils bzw. Batzens (MIC).
• + Gelesen während inverser Transformation.

Table 8 shows how much memory is needed to store the LIC coefficients for decoding each bitplane. Referring to Table 8, when dealing with the MIC, one bit is written per coefficient, which is the tail-one-bit. What is written for the bitplane 5 is read back to the bitplane 4: 2 to 3 bits which was the tail-a-bit, which was bit 5 and if bit 5 was 1, then a sign bit. The percentage indicates for each bit level what percentage of the coefficients participate. This can be made clearer by looking at the 13B looks. If one refers to the 13B Thus, the bit plane has 5 coefficients from all participating subbands because all the coefficients from the DD1 to the DS4 and SD4 subbands have data in the bit plane 5 (as indicated by shading). The bitplane 0 has only coefficients from the DD1 subband. As shown in Table 8, both bit-planes 4 and 5 have coefficients of all sub-bands, so that the percentage is 100, while bit-plane 0 has only 25% of the coefficients (in the DD1 sub-band). As more decodes occur, some bit-planes are completed before a bit-level 0 is reached. Table 8 - Required bits to store LIC coefficients during decoding

• * Written during processing of the most important part (MIC).
• + Read during inverse transformation.

In Table 8 is during the beginning of the decoding no decoding of the bit planes occurred; therefore only one bit (bit / coefficient) of each coefficient is read, to determine if it is a head or a tail. If the decoding As the rate increases, the number of bits per coefficient increases.

33 shows how circular addressing can be used to handle the writing of data larger than the read data. This occurs because the results of processing generate more bits to write than originally read. If you take reference 33 Thus, the process begins by writing one bit per coefficient, which is 1/8 of the memory space. Subsequently, one bit per coefficient is read while writing 2 to 3 bits per coefficient. Then, the 2 to 3 bits per coefficient are read while writing 3 to 4 bits per coefficient. This continues until all the data has been dealt with.

It gives some options to simplify the hardware implementations. Instead of always the minimum number of bits would be used would only be e.g. 1, 2, 4, 6 or 8 bits, which would cause one bit to be wasted on some sizes would become. A room for the sign bit could always be used even if the sign bit is not in the LIC was coded or not yet known.

A Option that would further reduce memory bandwidth would be that Cock-a-bit not to save, if it is not necessary. For example when If you write the bit-level 0, there are 6 bits that are either header or tail bits. If any of these bits are not 0, must be cock-one ("tail-on") to be true, and there is no need to store the tail-on values and the sign bit can be stored as the seventh bit.

Memory bandwidth for the most important chunk (MIC) can also be reduced by variable length memory techniques. Simply using the minimum number of bits rather than always using 8 bits per coefficient would result in savings. Storing 6-bit predictive values (as in 15 ) instead of 0 coefficient bits would result in even more efficient use of the memory.

Reversible color space

The The present invention provides an optional implementation of a reversible color space conversion ready, which is a conversion between two color spaces allowed, so they completely reversible and implementable in an integer arithmetic is. This means, The color space data that is converted can be reversed to all existing data, regardless of any rounding or any clipping during the forward conversion process occurs. Be reversible color spaces in U.S. Patent Application No. 08 / 436,661, entitled "Method and Apparatus for Reversible Color Conversion ", filed May 8, 1995 and assigned on the present Applicant, described.

The Allow color space conversions the benefits of an opposite Color space, without the ability to sacrifice lossless results. For the lossless case supplies an opposite color space is a decorrelation, the campression improved. For the lossy code allows an opposite color space, that luminance information is less quantized as chrominance information, giving a higher visual quality supplies. If a reversible color space with the transformation of present invention is a correct embedding the luminance and chrominance coefficients sub-sample the lossy one Superior to compression, while still a lossless compression is allowed.

If a reversible color space is used, it is desirable align the coefficients so that the most significant bit or most significant bit of 8-bit luminance components and the 9-bit chrominance components have the same orientation. For the lossy compression causes this alignment to cause chrominance data twice as common be quantized like luminance data, and also allows the possibility Lossless compression for luminance and a lossy (but very high quality) compression for or in terms of chrominance. These two results draw one Advantage from the properties of the human visual system.

Other pixel operations

Frequently becomes a printer have documents that are predominantly or completely non-continuous are. For example, you can Text images with only black and white (only the 0 and 255 value) will be common.

In one embodiment, the histogram of bands is completed. For example, pure 0.255 black and white images (the K component) can be remapped to 0.1 images. Similar densifications can be made with respect to spot color images. It is noteworthy that when compression is used, the compression must be lossless. However, the scored lossless compression significantly improved when the compaction is performed.

alternative can, instead of using the overlapped one Wavelet transforms described herein are binary and spot color images through a lossless bit-plane based JBIG-like context model be handled.

In another alternative embodiment, the system may be designed to include a binary mode. 35 Figure 12 shows an embodiment of a binary context model that is similar to the JBIG style context model template. If you take reference 35 , so put shift registers 3501 to 3503 several bits per or for the JBIG standard. The shift registers 3501 and 3502 receive second and first upper lines from the line buffer 3500 , The "upper" lines provide the bits corresponding to the pixels in the Northwest (NW), North (N), and Northeast (NE) positions of the template, as in FIG 37 is shown. The outputs of the shift registers 3501 and 3502 become the context model directly 3505 delivered. The outputs of the shift register 3503 become an optional multiplexer 3504 which can implement the adaptive template of the JBIG standard. The context model 3505 is connected to the probability estimator 3506 , in turn, to the bit generator 3507 connected. The context model 3505 , the probability estimator 3506 and the bit generator 3507 work together as is well known in the art.

The output of the multiplexer 3504 in conjunction with the outputs of the shift register 3501 and 3502 and feedback from the bit generator form the context bin address used to address the context memory. In one embodiment, the context memory includes 3505 1024 6-bit contexts to describe each probability state. This requires a context memory of 1024 by 6 bits.

There the bit generator takes a decoded bit from the current line as Providing part of the context address, there is a large "bit-to-context" delay including the Access time for the context memory.

36 Figure 4 shows an alternative embodiment that uses the decoded bit from the current line to access the probability estimator in conjunction with a same address block 3601 access the outputs of the shift register 3501 and 3502 and the output of the multiplexer 3504 receives. The PEM 3506 receives the previous bit and uses it to select the correct one from the context pair used. The selected context is updated and both contexts are written back to memory. The same address block 3601 detects addresses that have already been written so that the data is already in the probability estimator. The same address block 3801 also sends the signal to use the data already in the PEM (which may be updated data) instead of the old information in memory.

In one embodiment, the decoder includes 1024 Context bins with 6 bits to describe each probability state. This requires a 512x12 bit context memory. The outputs of the shift register 3501 and 3502 along with the output of the multiplexer 3504 provide a partial context bin address which only misses the use of the previous bit. This results in a selection of a context bin pair from the context store 3505 , More than one bit of a context bin can be excluded from the subcontext. Each memory location contains 2 ⁿ probability states, where n is the number of excluded bits.

Remarkable is that the "bit-to-context" delay reduces is. The context memory access can occur before the previous one Bit is decoded. The processing of the PEM state for both conditions in a pair can start in parallel before the previous bit is decoded. High speed operation can be achieved.

Kodiererratensteuerung

In addition to the ability to to quantize the data requires performing a rate control in the coder also measuring the rate so that decisions about the Quantization can be made. If the rate indicates that the Compression is not good (i.e. not at a desired level is, the quantization can be increased become. On the other hand, if the rate indicates that the compression is too high, the quantization can be reduced. Rate control decisions must be identical in the encoder and the decoder.

One Procedure for ensuring that the Encoder and the decoder make the same decisions is it to use a signaling. The encoder measures the rate at predetermined intervals and stores the quantization Q in a store for the future Use in the next Interval. The decoder simply calls the quantization again from the memory for every interval. This would be one Require extra memory. For example, an on-chip SRAM would be SRAM, which is on a chip, with 256 bits of 2 bits (to display a change in q by +2, +1, 0, -1 or for storing Q as 1, 2, 3, 4) sufficient to quantize Q every 16 lines for to change a 4096-line image.

There are many options for rate measurement. 34 shows a coder and decoder pair. If you take reference 34 Thus, there is shown an encoder / decoder pair comprising context models (CM), probability estimation models (PEM) and bit generators (BG) together with a run count reorder unit, a nested word reordering unit ("interleaved word reorder unit") and a sliding device contains. All of this is well known in the art. For the description, reference is made to U.S. Patent Nos. 5,381,145 and 5,583,500 to the present assignee, the contents of which are hereby incorporated by reference.

The Rate measurement must be explicit if the decoder is not in the same place or at the same place can measure. For example, the rate measurement is the decoder as Part of the compressed code stream provided.

Another option for rate handling, shown as the smaller circle (position 2 in 34 ) is to count the start of the interlaced words in the encoder. In another embodiment, this is done after the biting stage (position 4 in FIG 34 ). Because the encoder and decoder start a codeword at the same time, implicit rate signaling can be used. The counting may be performed with a counting hardware comprising a register and an adder which adds the code word lengths and determines the average code word length. Hardware for performing the counting and determining an average number of bits is well known in the art and is disclosed in US Pat 34 as a block 3401 shown. It is obvious that this block can be used to perform similar measurements at other locations in the system (eg, positions 1, 2, 3, 4 on both the encoder and decoder).

Other options would be to count the size of completed codewords after the bit generator and before the nested word reordering unit (position 3 in FIG 34 ), or determining the current amount of data written to the disc (position 1 in 34 ).

The rate measurement may be implicit: both the encoder and the decoder perform the same rate determination calculation. For example, the encoder and decoder could accumulate the average size of a codeword each time a new codeword is started. This is determined by the position in 34 shown. (The current size can not be used because the encoder does not know the size to the end of the codeword). If the R codes used in the core vary in size from R2 (0) to R2 (7), the average codeword size varies from 1 to 4.5 bits. If the probability estimate works well, the use of the middle should be very accurate. In other cases, the differences between the minimum and maximum codeword length are typically not as large as the mean, so the estimate should still be useful. The average size of an Rz (k) codeword is (k / 2) + 1 bits.

It the goal may be that in almost all cases the most important data are well compressed and no quantization (Q = 1) will be required. Only "pathological" images will require quantization (Q> 1). The Lock in However, the quantization feature can guarantee that the system will not collapse in pathological images.

One Another advantage of encoder rate control is that coding less important data can be stopped if the maximum Bandwidth exceeded becomes. This increases the speed of coding and reduces the total time the output data (e.g., the total printing time is decreased).

Continuously tracking the effects of quantization changes (the value of Q) is important. For example, the definition of the largest coefficient in a group of coefficients must be consistent with the quantization changes. Similarly, the reconstruction of quantized coefficients (if bitplanes are omitted) must reduce the number of bitplanes omitted to achieve the best result take into account.

High-speed parallel coding and context model

Of the Entropy coding section of the present invention comprises two Parts. First, make high-speed encoding cores in parallel work, a probability estimate and a biter generation ready. Second, a contextual model provides the contexts for coding be used.

The Number of cores needed to achieve the desired speed is application-dependent.

Of the another part of the entropy coding system is the context model for the coefficients of the present invention. There are a lot of compromises that are possible when implementing the context model. In one embodiment the present invention provides a context model with low hardware overhead, that a parallelism provides for the use of high speed parallel encoders to assist the present invention. Embodiments of the context model are described above.

Even though only the context model for Wavelet coefficient is described herein is the present The invention is not limited to context models that only use wavelet coefficients support. For example, if a bit-plane encoding mode is binary or Spot color images desired is an additional one Use contextual model, as e.g. in US patent application no. 08 / 642,518, filed May 3, 1996, entitled "Compression and Decompression with Wavelet Style and Binary Style Including Quantization by Device Dependent Parser ", and in US Patent Application No. 08 / 643,268, filed May 3, 1996, entitled "Compression / Decompression Using Reversible Embedded Wavelets "is described.

parallelism

at an embodiment Four high-speed encoding cores are used, 8 bits to code / decode coefficients where coefficients of 8 to 12 bits suffice (13, if a reversible color space is used). In one embodiment a core is assigned to each component of the four components whereby the parallelism and the data flow are simplified. Everyone Coefficient can take up to 16 cycles to encode / decode bits use (including Foresight decisions, etc.).

The present invention the cores for every component in synchronization, even if certain cores are unproductive are because of their successful foresight, or one another core handles a sign bit after a first "on" bit. The total time to run the contextual model will depend on the data, in particular the effectiveness of the foresight and to a lesser extent vary from the location of the first "on" bits.

The invention can be summarized in particular as follows:
A method and apparatus for performing compression and / or decompression is described. In one embodiment, the present invention includes a system including a buffer, a wavelet transform unit, and an encoder. The wavelet transform unit has an input connected to the buffer to perform a wavelet transform with the pixels stored therein and to produce coefficients at the output. The encoder is connected to the wavelet transform unit to encode the transformed pixels received from the buffer.

Brief Description:

14

1401

Encode MIC

1402

Encode Position of the first LIC bit plane with data

1403

Set current LIC bit level to first LIC bit level with data

1404

All LIC bit planes encoded with data

1405

Encode a LIC bit plane

1406

Set current LIC bit level to next LIC-bit level

16

1601

Set current tree to first tree

1602

Encode SS coefficients

1603

Perform MIC (or tree) foresight ( 5 )

1604

is the MIC of the whole tree 0?

1605

Set current coefficients to first non-SS coefficients in the tree

1606

Set Current bit level to first bit level with data

1607

Encode Bit of a current coefficient in the current bit plane

1608

All Bite levels coded?

1609

Set current bit level to next bit level

1610

is current coefficient 0?

1611

Encode sign

1612

Set current coefficients on next Coefficients in the tree

1613

All Coded coefficients in the tree?

1614

All Trees coded?

19

1901

Set current tree to first tree

1902

Set current coefficients to first non-SS coefficients in the tree

1903

At the Start a foresight interval?

1904

foresee

1905

foresee enabled?

1906

Encode Head or tail bit

1907

first Non-zero bit?

1908

Encode sign

1909

All Coded coefficients in the tree?

1910

Set current coefficients to the next Coefficients in the tree after vor

herseh interval

1911

All Coded coefficients in the tree?

1912

Set current coefficients to the next Coefficients in the tree

1913

All Trees coded?

Claims (87)

System with: A buffer; - one Wavelet transformation unit with an input connected to the buffer is connected to a reversible wavelet transform with Perform pixels, which are stored in the buffer and coefficients at a To produce output; - one Encoder connected to the wavelet transformation unit, to bit planes of wavelet-transformed pixels from the wavelet transformation unit and bit planes stored in the buffer of wavelet-transformed ones Encode pixels. The system of claim 1, wherein the buffer has a Band buffer to store at least one band of pixels. The system of claim 1, wherein the encoder comprising: - one Context model; and - one parallel entropy coders; - in which the most important Data are not embedded and in a coefficient order or sequence are coded without buffers, a part less important data buffered, embedded in order of importance and then written to a memory. The system of claim 1, wherein the encoder a high speed parallel encoder. The system of claim 1, wherein the encoder a QM encoder. The system of claim 1, wherein the encoder comprises a Encoder with a finite-state machine or an FSM encoder includes. The system of claim 1, further comprising an interface for coded Includes data. Method for compressing information that the following steps include: - a wavelet transformation of pixel information received from a buffer becomes performed, where at least one bit-plane of coefficients reversible wavelet-transformed Representing pixels; - the Pixels in the buffer are replaced by coded bit-planes; and - bitplanes, which are stored in the buffer are encoded. Decompression system comprising: - one Band buffer comprising: - one Number of coding units for Coefficients to undergo an inverse transformation operation; - at least a coding unit for storing pixels that are sent to an output device are to be issued; - at least a coding unit for Pixels that correspond to previously inverted transformed coefficients, which are to be sent to the output device; - one Decompressor connected to the band buffer, the decompressor decompressed compressed data into transformed coefficients, writes the transformed coefficients to the band buffer Retrieving coefficients from the band buffer, an inverse transformation with the transformed coefficients read back from the band buffer were, performed, to generate pixel values and write pixel values to the band buffer. A decompression system according to claim 9, wherein the decompressor reads compressed data from a storage area. A decompression system according to claim 10, wherein the storage area comprises a hard disk. The decompression system of claim 9, further includes a printing machine connected to the tape buffer is. Method for coding a set of transformed Coefficients in image compression, the following steps includes: - the Data bits of a transformed coefficient become the most important ones Split data and less important data; - the most important Data becomes a context model for coding in coefficient order or coefficient order sent; - the less important data and a number of signaling bits are stored in a memory; and - to coding the most important data of all the coefficients in the sentence of coefficients the less important data are encoded and according to a Order or order embedded, in part on the number or variety of Signalisierbits based. The method of claim 13, wherein the signaling bits a first bit and a second bit. The method of claim 13, wherein a first the signaling bits indicates whether the first bit is the less important one Data of the coefficient is a head or a tail bit, and a second of the signaling bits indicates the sign bit, if that first of the signaling bits indicates that the first bit of the less important data of the coefficient is a bit header. The method of claim 13, wherein the signaling bits stored next to the less important data. An apparatus for performing a forward transform, comprising: an input buffer having an input connected to receive input data and first and second outputs for transmitting even and odd samples; A first-level transform unit connected to receive the even and odd values and generate coefficients, horizontal low-pass and vertical high represent pass-coefficient outputs of the forward transform; A memory having a first input connected to receive ss coefficients generated by the first level transformation or by the first level transformation of the first level transformation unit and having a second input receive ss coefficients from higher level transform filtering; An ordering unit having a first input connected to the memory for ordering ss coefficients for higher levels of filtering; and a first filter unit connected to the ordering unit for applying a number of transformation levels, the filter unit performing a transformation of ss coefficients according to a higher level and a higher level transformation ss coefficients, respectively, received from the ordering unit wherein the filter unit generates ss coefficient values which are fed back to the second input of the memory and to the second input of the ordering unit. Device for carrying out a forward transformation according to claim 17, wherein the first level transformation with 2x2 blocks the input data works or processes these. Device for carrying out a forward transformation according to claim 17, wherein the first level transformation comprises includes: - one second filter unit to a first-level horizontal transformation perform, in which the second filter unit has a first and a second Output has; - one first single or single delay, which is connected to the first output of the second filter; - a second single or single delay, which is connected to the second output of the second filter; - a double delay, which is connected to the second output of the second filter; - one first multiplexer, which is connected to the outputs of the first single delay and twice the delay to recieve; - one second multiplexer connected to receive an output of first filter unit and an output of the second single delay receive; and - one third filter unit, which is connected to the outputs of receive the first and second multiplexers and a first level vertical transformation perform. The system of claim 1, further comprising: - one Compressor; - one Workspace storage, which is connected to the compressor, wherein the work space memory has the same size as the image, and the Compressor uses the workspace memory to encode the image by using coefficients larger than the pixels in the Image. Method for Coding Information Consisting of main data and less important data, the Method comprising the following steps: - Coding of the most important Dates; - Coding the position of the first bit plane in the less important data for each Coefficients that are not complete consists of zero overhead bits; - Encoding each bit level of less important data that does not consist entirely of zero overhead bits. The method of claim 21, wherein the information Includes wavelet coefficients. The method of claim 21, wherein the step for coding the position of the first less important bit plane the performing of a foresight includes the entire bitplanes of less important data. The method of claim 21, wherein the step coding the key data involves the following steps: for each Tree: - Coding the ss coefficient; - Perform a Foresight the most important data; and - for each non-ss coefficient: - Coding a head or tail bit for every bit-level with data, and - coding a sign bit, if the coefficient is not zero. The method of claim 24, wherein anticipating includes tree anticipation, and the step of performing the Predictively encode the ss coefficients and encode the first one Zero bit-plane with non-zero overhead bits for the entire tree. The method of claim 24, wherein the most important Data with a wavelet tree at one time or wavelet tree for wavelet tree processed become. The method of claim 21, wherein anticipating Bite planes determines all zero overhead bits for all non-ss coefficients in the wavelet tree. The method of claim 27, further comprising the steps Identifying the first bit level involves being customized to code. The method of claim 28, wherein the step identifying the first bit-plane to encode individually indicating that all non-ss coefficients of the second decomposition Are zero, using a first bit, and displaying, that all non-ss coefficients of the first decomposition are zero, below Using a second bit. The method of claim 21, wherein the step coding the key data involves the following steps: for each Tree: - Coding the ss coefficient; - Perform a Predictably, to determine bit planes, all zero overhead bits for all non-ss coefficients in every tree; - it determines if the main data of the entire tree is zero are; - if the main data of the whole tree are not zero, then for all coefficients in the tree: - bits the current coefficient for all bit planes are coded, where the current coefficient of the first non-ss coefficient in the tree is and with the first bit plane is started, which contains data; - the sign bit is coded if the current coefficient is not zero. The method of claim 21, wherein the step of coding the less important data the following steps includes: For every tree: - for each coefficients: - one Foresight is carried out if at the start of a foresight interval; - Coding of a header or Tail bits if foresight is not active; and - Coding a sign bit if the first one bit has occurred and foresight is not active. Apparatus for coding information resulting from Most important data and less important data exist, whereby the Apparatus comprising: - a device for coding the most important data; - one Device for coding the position of the first bit plane in the less important data for any coefficient that does not consist entirely of zero overhead bits; - An institution to encode each bit-level of less important data that is not Completely consist of zero overhead bits. Apparatus according to claim 32, wherein the information Includes wavelet coefficients. Apparatus according to claim 32, wherein the device for coding the position of the first less important bit plane a device for performing of a foresight includes the entire bitplanes of less important data. Apparatus according to claim 32, wherein the device for coding the most important data includes: - An institution for encoding the ss coefficient for each tree; - An institution to perform of a foresight for the most important data for every tree; - one Device for coding a header or tail bit for each bit plane with data for each non-ss coefficient for every tree; and - one Means for coding a sign bit if the coefficient for each Non-ss coefficients for each Tree is not zero. Apparatus according to claim 35, wherein said anticipating a tree anticipation, and the means for performing the Predictably, means for encoding the ss coefficients and means for encoding the first zero bit level Non-zero header bits for includes the entire tree. Apparatus according to claim 35, wherein the most important Data according to one Wavelet tree too a time or wavelet tree for Wavelet tree are processed. Apparatus according to claim 32, wherein the device to perform of foresight determines the bit planes, all zero overhead bits for all Comprise non-ss coefficients in the wavelet tree. The apparatus of claim 38, further comprising means To identify the first bit level includes to individually encode. Apparatus according to claim 39, wherein the device for identifying the first bit plane to encode individually means to use a first bit indicate that all non-ss coefficients of the second decomposition Are zero, and means include using a second bits indicate that all non-ss coefficients of the first Decomposition are zero. Apparatus according to claim 32, wherein the device for coding the most important data includes: - An institution for encoding the ss coefficient for each tree; - An institution to perform of a prediction to determine bit planes, all zero overhead bits for all non-ss coefficients in every tree; - one Device for determining if the most important data of the whole Tree for every tree is zero; and - one Set up to use bits of the current coefficient for all bit planes for all Encode coefficients in the tree if the most important data for the Whole tree are not zero, with the current coefficient of first non-ss coefficient in the tree and being the first Bite level is started, which contains data; - a device for coding the sign bit if the current coefficient is not zero for all Coefficients in the tree, if the most important data for the whole Tree are not zero. Apparatus according to claim 32, wherein the device for coding the less important data comprises: - An institution to perform of a foresight for every coefficient for every tree, if at the start of a foresight interval; - An institution for coding a header or tail bit for each coefficient for each Tree, if the foresight is not active; and - An institution for coding a sign bit for each coefficient for each Tree, if the first one-bit has occurred and the anticipation is not active. Procedure for m-ary encoding information, the method being the following Steps includes: - one predetermined number of coefficients are examined; - an entropy coding all header bits with one per cycle until all header bits in the predetermined one Number of coefficients are coded; - a coding of the sign and tail bits of the predetermined number of coefficients in the same cycle. Integrated circuit (IC) chip, the following includes: - one Pixel data interface to pixel data between the IC chip and to transfer to the memory; - a reversible Wavelet transformation connected to the pixel data interface is to get information to and from the memory via the pixel data interface transferred to; - a context model, which is connected to the reversible wavelet transformation, contexts to encode the data that comes from it provide; - one Encoder to encode coefficients by the reversible Wavelet transform based on contexts provided by the context model will be generated. The integrated circuit chip of claim 44, further comprising a coefficient data interface which is connected to coefficients of the transformation to transfer the memory without coding. The integrated circuit chip of claim 44, wherein the coefficient data interface Transfer coefficients from the memory to the context model for coding. The integrated circuit chip of claim 44, further comprising an interface for coded Includes data to provide entropy-coded data to the memory. The integrated circuit chip of claim 47, further comprising a decoder includes to decode encoded data. The integrated circuit chip of claim 46, further comprising an interface for coded Data includes the decoder with entropy-coded data for decoding to supply. The IC chip of claim 44, further comprising a reversible Color space converter that covers the pixel data interface and the reversible wavelet transform is connected to to perform a reversible color space conversion. Decoder for decoding encoded image data, wherein the decoder comprises: At least one bit generator, which is connected to receive and encode the encoded data the coded data based on a probability estimate decode, wherein the at least one bit generator is a decoded one Bit generated by a current line; A probability estimator, which is connected to the at least one bit generator to the probability estimate based on the decoded bit from the current line; - a context model, which is connected to the probability estimator, around a number of contexts of the probability estimator based on a partial context address, the probability estimator among the number of contexts based on the decoded one Select bit. The decoder of claim 51, further comprising an indicator for same Addresses or an equal address indicator, which corresponds to the Probability estimation machine is connected to detect the addresses that are already read indicating that the data is already displayed in the probability estimator available are, with the indicator for same addresses an indication to the probability estimator which indicates that the data is already in a probability estimator are based on the sub-context being addressed. The decoder of claim 51, further comprising a number of shift registers that are connected to the context model are to provide the sub-context address. The decoder of claim 51, further comprising a line buffer which is connected to a number or a plurality of upper To provide rows. Contextual model comprising: - a first one Bit-plane unit connected to less important data and receive the most important data to determine which bit-planes Data, wherein the first bit-plane unit is an indication of Bit plane with the first one bit for the entire coding unit for use when processing the less important data generated; - one Comparison mechanism that is connected to the less important ones Data and the most important data to receive a signaling information for the to generate less important data; - a memory that is connected is to the sign bit, the most important data and an indication receive the first bit plane with data, the memory coefficients delayed to provide conditioning information; - a first Context model connected to the memory to contexts for sign bits provide; - one second context model attached to the memory and the most important data is connected to contexts for to provide the header bits; and - a third contextual model, which is connected to the memory and the most important data, around contexts for to provide the tail bits. The context model of claim 55, further comprising Separation mechanism or separation mechanism includes the input data into more important and less important data. Context model according to claim 56, wherein the separation mechanism mus comprises a barrel slide or "barrel" slider. Context model according to claim 57, wherein the Tons slider shifts data based on a quantization level. Context model according to claim 55, wherein the Comparative mechanism comprising: A first comparison unit, to determine if the most important data is equal to zero, to indicate that a tail bit has already occurred, the output of the first Comparison unit is a tail one bit; - a second Compare unit to determine if the most important data is the same One are where an output of the second compare unit is the same Zero is when the most important data equals one; and - one Multiplexer connected to the output of the second comparator and receive the sign bit to output a first tail bit, if the selection input is in a first state, and to output the sign if the selection input is in a second state. Context model according to claim 59, wherein the select input the tail-one issue the first comparison unit comprises. Context model according to claim 58, in which the first and / or second comparison unit comprises a bit comparator. Context model according to claim 55, wherein the first bit-plane unit comprises: - an OR gate connected is to receive a coefficient and a feedback; - a register, connected to receive the output of the OR gate; and - one priority encoder, which is connected to receive the output of the register, to record the first bit plane of the coefficient, the one One has. Context model according to claim 62, wherein said Register a reset input contains to reset the content of the register at the start of the encoding unit. Context model according to claim 62, wherein the Reset input also the content or data content of the register at the start of a reset each tree. The method of claim 8, further comprising the following Steps includes: - outgoing from the middle length the code words a current compression level is determined; and - a compression rate is set based on the current compression level or adjusted. The method of claim 65 further comprising the following Steps: - one The extent of a quantization level is increased if the coding rate indicates that the compression is below a first desired Levels is; and - of the The degree of quantization is lowered if the Encoding rate indicates that the compression is above a second desired Levels is. The method of claim 66, wherein the first and second desired Level are not the same. The method of claim 65, wherein the step Determination of average length of codewords performed after the biter production becomes. The method of claim 65, further comprising the step comprising, after which a decoder signals a new compression rate becomes. The method of claim 69, wherein signaling is explicit. The method of claim 69, wherein signaling is implicit. A system comprising: a context model; A probability estimator connected to the context model; A bit generator connected to the probability estimator; and A coding rate control connected to an output of the bit generator to control the coding rate by determining an average code word length. The system of claim 72, wherein a coding rate control adjusts or adjusts a quantization. The system of claim 72, including a signaling block includes to a decoder with respect signal a new quantization level. The system of claim 72, further comprising a signaling block includes to header data for to generate a compressed data stream output of the encoder which concatenated to the compressed bitstream, to the encoder display new quantization level. The system of claim 72, wherein the coding rate control stores an indication of the quantization level that is for a subsequent one Use by the decoder is necessary. Process for processing a least important Part of data bit planes of a set of transformed coefficients, which includes the following steps: A first dataset of the Data of the transformed coefficients is from a memory read; and - one second amount of data greater than the first amount of data is written to the memory while the first Dataset is read to transformed bit-planes with less Data in the lower-order bit-planes of the sentence transformed To equalize coefficients. The method of claim 77, wherein the bits, required to store the least important coefficients are increasing as the bit plane number decreases. Method for decompressing information, wherein providing a band buffer comprising: - a number of coding units for Coefficients to undergo an inverse transformation operation; - at least a coding unit for storing pixels that are sent to an output device are to be issued; - at least a coding unit for Pixels that correspond to previously inverted transformed coefficients, which are to be sent to the output device; by means of a Decompressors compress data to transformed coefficients decompressed, the transformed coefficients to the band buffer are written, transformed coefficients from the band buffer read back be an inverse transformation with the transformed coefficients, which read back from the tape buffer were carried out, to generate pixel values and write pixel values to the band buffer become. Apparatus for coding a set of transformed ones Coefficients in image compression, wherein the device is formed is to carry out the method of claim 13. Method for carrying out a forward transformation, which includes the following steps: - Receive input data by means of an input of an input buffer; - Transfer of even and odd values or samples or samples by means of a first and a second output of the input buffer; - receive of even and odd values and samples and generating Coefficients, where horizontal low-pass or vertical high-pass coefficients Issues of the forward transformation represent, by means of a first-level transformation unit; - receive of ss coefficients which are determined by the first-level transformation or by the transformation according to a first level of the first-level transformation unit are generated, by means of a first input of a memory, and receiving ss coefficients from higher-level transform filtering by means of a second input; - ordering ss coefficients for higher levels the filter by means of an ordering unit with a first input; and - Apply a number of transformation levels by means of a first filter unit, wherein by means of the filter unit, a transformation of ss coefficients according to one higher Level or higher level transformation ss coefficients carried out is received by the ordering unit, by means of the filter unit ss coefficient values generated to the second input of the memory and the second input of the ordering unit returned or fed back become. An apparatus for m-ary encoding information, wherein the apparatus is adapted to the Verfah Ren carry out according to claim 43. Method for coding information by means of a Integrated circuit (IC) chips, which includes the following steps: - Transfer pixel data between the IC chip and a memory by means of a pixel data interface of the IC chips; - Transfer of information to and from the memory via the pixel data interface using a reversible wavelet transform applied to the pixel data interface connected; - Provide contexts for encoding the data using a contextual model, where the data is supplied and the context model the reversible wavelet transformation connected; - Coding of coefficients by the reversible wavelet transformation based on contexts provided by the context model will be generated. Method for decoding encoded picture data, the the following steps include: - receiving encoded data and decoding encoded data based on a probability estimate at least one bit generator, wherein by means of the bit generator a decoded bit is generated from a current line, where the probability estimate based on the decoded bit from the current line of one Probability estimation machine is delivered; - Provide a number of contexts of the probability estimator by means of a contextual model, which is sent to the probability estimator connected, based on a partial context address, the probability estimator among the number of contexts based on the decoded one Image selected. Method for providing contexts that the following steps include: - Receive less important Data and most important data by means of a first bit-plane unit, to determine which bit-planes contain data, the first Bit plane unit is an indication of the bit plane with the first one bit for the entire coding unit for use when the less important Data processed, generated; - Receive the less important Data and key data using a comparison mechanism to signaling information for the less important data to create; - receive the sign bit, the most important data and a display of the first bit plane with data by means of a memory, by means of of memory coefficients delayed to provide conditioning information; - Provide of contexts for Sign bits by means of a first context model sent to memory shot at; - Provide of contexts for Header bits by means of a second context model, which is sent to the memory and the most important data is shot; and - Provide of contexts for Tail bits by means of a third contextual model sent to the memory and the most important data is connected. Method for controlling a coding rate with the following steps: Providing a contextual model; Connecting one Probability estimation machine to the context model; Connecting a bit generator the probability estimator; in which the coding rate is controlled by using a coding rate control, which is connected to an output of the bit generator, a middle one code word is determined. Apparatus for processing at least one important part of data bit planes of a set of transformed ones Coefficients, wherein the device is designed, the method to carry out according to claim 77.