DE10350865A8 - Speicherbaustein mit variabel verzögerter Spaltenauswahl - Google Patents

Speicherbaustein mit variabel verzögerter Spaltenauswahl Download PDF

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Publication number
DE10350865A8
DE10350865A8 DE10350865A DE10350865A DE10350865A8 DE 10350865 A8 DE10350865 A8 DE 10350865A8 DE 10350865 A DE10350865 A DE 10350865A DE 10350865 A DE10350865 A DE 10350865A DE 10350865 A8 DE10350865 A8 DE 10350865A8
Authority
DE
Germany
Prior art keywords
memory block
column selection
delayed column
variable delayed
variable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE10350865A
Other languages
English (en)
Other versions
DE10350865A1 (de
Inventor
Harald Streif
Stefan Sunnyvale Wuensche
Michael A. Killian
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qimonda AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of DE10350865A1 publication Critical patent/DE10350865A1/de
Publication of DE10350865A8 publication Critical patent/DE10350865A8/de
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/002—Isolation gates, i.e. gates coupling bit lines to the sense amplifier
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2281—Timing of a read operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/229—Timing of a write operation
DE10350865A 2002-10-31 2003-10-31 Speicherbaustein mit variabel verzögerter Spaltenauswahl Ceased DE10350865A1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US285027 1994-08-02
US10/285,027 2002-10-31
US10/285,027 US7035150B2 (en) 2002-10-31 2002-10-31 Memory device with column select being variably delayed

Publications (2)

Publication Number Publication Date
DE10350865A1 DE10350865A1 (de) 2004-05-27
DE10350865A8 true DE10350865A8 (de) 2004-09-23

Family

ID=32175067

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10350865A Ceased DE10350865A1 (de) 2002-10-31 2003-10-31 Speicherbaustein mit variabel verzögerter Spaltenauswahl

Country Status (2)

Country Link
US (2) US7035150B2 (de)
DE (1) DE10350865A1 (de)

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US8077535B2 (en) 2006-07-31 2011-12-13 Google Inc. Memory refresh apparatus and method
US8327104B2 (en) 2006-07-31 2012-12-04 Google Inc. Adjusting the timing of signals associated with a memory system
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US7609567B2 (en) * 2005-06-24 2009-10-27 Metaram, Inc. System and method for simulating an aspect of a memory circuit
US10013371B2 (en) 2005-06-24 2018-07-03 Google Llc Configurable memory circuit system and method
US8060774B2 (en) 2005-06-24 2011-11-15 Google Inc. Memory systems and memory modules
US7472220B2 (en) * 2006-07-31 2008-12-30 Metaram, Inc. Interface circuit system and method for performing power management operations utilizing power management signals
US7392338B2 (en) * 2006-07-31 2008-06-24 Metaram, Inc. Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits
US20080082763A1 (en) * 2006-10-02 2008-04-03 Metaram, Inc. Apparatus and method for power management of memory circuits by a system or component thereof
US7580312B2 (en) * 2006-07-31 2009-08-25 Metaram, Inc. Power saving system and method for use with a plurality of memory circuits
US8244971B2 (en) 2006-07-31 2012-08-14 Google Inc. Memory circuit system and method
US8041881B2 (en) 2006-07-31 2011-10-18 Google Inc. Memory device with emulated characteristics
US8055833B2 (en) 2006-10-05 2011-11-08 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
US8081474B1 (en) 2007-12-18 2011-12-20 Google Inc. Embossed heat spreader
US7386656B2 (en) * 2006-07-31 2008-06-10 Metaram, Inc. Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
US8111566B1 (en) 2007-11-16 2012-02-07 Google, Inc. Optimal channel design for memory devices for providing a high-speed memory interface
US8130560B1 (en) 2006-11-13 2012-03-06 Google Inc. Multi-rank partial width memory modules
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US8397013B1 (en) 2006-10-05 2013-03-12 Google Inc. Hybrid memory module
US8359187B2 (en) 2005-06-24 2013-01-22 Google Inc. Simulating a different number of memory circuit devices
US8335894B1 (en) 2008-07-25 2012-12-18 Google Inc. Configurable memory system with interface circuit
US8089795B2 (en) 2006-02-09 2012-01-03 Google Inc. Memory module with memory stack and interface with enhanced capabilities
US8386722B1 (en) 2008-06-23 2013-02-26 Google Inc. Stacked DIMM memory interface
US8438328B2 (en) 2008-02-21 2013-05-07 Google Inc. Emulation of abstracted DIMMs using abstracted DRAMs
WO2007028109A2 (en) * 2005-09-02 2007-03-08 Metaram, Inc. Methods and apparatus of stacking drams
US7549092B2 (en) * 2005-09-29 2009-06-16 Hynix Semiconductor, Inc. Output controller with test unit
US9632929B2 (en) 2006-02-09 2017-04-25 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
US7724589B2 (en) 2006-07-31 2010-05-25 Google Inc. System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits
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US8209479B2 (en) 2007-07-18 2012-06-26 Google Inc. Memory circuit system and method
US8080874B1 (en) 2007-09-14 2011-12-20 Google Inc. Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween
US8521979B2 (en) * 2008-05-29 2013-08-27 Micron Technology, Inc. Memory systems and methods for controlling the timing of receiving read data
US7979757B2 (en) 2008-06-03 2011-07-12 Micron Technology, Inc. Method and apparatus for testing high capacity/high bandwidth memory devices
US7855931B2 (en) 2008-07-21 2010-12-21 Micron Technology, Inc. Memory system and method using stacked memory device dice, and system using the memory system
US8289760B2 (en) 2008-07-02 2012-10-16 Micron Technology, Inc. Multi-mode memory device and method having stacked memory dice, a logic die and a command processing circuit and operating in direct and indirect modes
US8756486B2 (en) 2008-07-02 2014-06-17 Micron Technology, Inc. Method and apparatus for repairing high capacity/high bandwidth memory devices
US8127204B2 (en) * 2008-08-15 2012-02-28 Micron Technology, Inc. Memory system and method using a memory device die stacked with a logic die using data encoding, and system using the memory system
EP2441007A1 (de) 2009-06-09 2012-04-18 Google, Inc. Programmierung von dimm-abschlusswiderstandswerten
US8400808B2 (en) 2010-12-16 2013-03-19 Micron Technology, Inc. Phase interpolators and push-pull buffers
US9081665B2 (en) * 2012-02-02 2015-07-14 OCZ Storage Solutions Inc. Apparatus, methods and architecture to increase write performance and endurance of non-volatile solid state memory components
US9171597B2 (en) 2013-08-30 2015-10-27 Micron Technology, Inc. Apparatuses and methods for providing strobe signals to memories
CN108139994B (zh) * 2016-05-28 2020-03-20 华为技术有限公司 内存访问方法及内存控制器
KR20180058478A (ko) * 2016-11-24 2018-06-01 에스케이하이닉스 주식회사 반도체 장치, 이를 포함하는 반도체 시스템 및 반도체 장치의 리드 및 라이트 동작 방법
KR102386811B1 (ko) * 2017-07-18 2022-04-15 에스케이하이닉스 주식회사 메모리 시스템 및 그것의 동작 방법
US11340831B2 (en) 2020-08-28 2022-05-24 Micron Technology, Inc. Systems and methods for adaptive read training of three dimensional memory
CN116052737B (zh) * 2023-03-28 2023-08-29 长鑫存储技术有限公司 列控制电路以及存储装置
CN117809708A (zh) * 2024-02-29 2024-04-02 浙江力积存储科技有限公司 存储阵列及提高存储阵列的数据读取准确度的方法

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JP2000048567A (ja) * 1998-05-22 2000-02-18 Mitsubishi Electric Corp 同期型半導体記憶装置
JP2001035195A (ja) * 1999-07-19 2001-02-09 Nec Ic Microcomput Syst Ltd 半導体記憶装置
US7035150B2 (en) 2002-10-31 2006-04-25 Infineon Technologies Ag Memory device with column select being variably delayed

Also Published As

Publication number Publication date
US7149134B2 (en) 2006-12-12
US7035150B2 (en) 2006-04-25
US20040088475A1 (en) 2004-05-06
DE10350865A1 (de) 2004-05-27
US20060050574A1 (en) 2006-03-09

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8716 Sentence in annex german patentblatt annex 1a6
OP8 Request for examination as to paragraph 44 patent law
8127 New person/name/address of the applicant

Owner name: QIMONDA AG, 81739 MUENCHEN, DE

8131 Rejection