DE102004061310B4 - Embedded data processing system with dynamic regulation of the power consumption of the individual components - Google Patents

Abstract

Embedded data processing system (1) of functional system units (4-1, ..., 4-N) with dynamic monitoring and regulation of the power consumption of the system units (4-1, ..., 4-N) with:
a) at least one power supply unit (2) for generating a system supply voltage (VDD, VSS);
b) at least one clock generation unit (3) for generating a system clock signal (CLKS);
c) a plurality of clocked system units (4-1, 4-2, ..., 4-N), each having at least one controllable clock adaptation unit (5-1, ..., 5-N), a controllable supply voltage adjustment unit (6-1 , ..., 6-N) and an activity monitoring unit (14-1, ..., 14-N) for generating operating state signals BZS1, ..., BZSN) of the respective system unit (4-1, ..., 4 -N);
d) an operating state monitoring unit (9) for evaluating the operating state signals (BZS1, ..., BZSN) and for providing operating state information (BZI) of the embedded system (1);
e) memory means (11) for storing an event database of supply voltage and clock signal configurations of the embedded system (1) for predetermined combinations of the operating condition signals (BZS1-BZSN); and
f) a power receiving control unit (10) for controlling the clock adjusting units (5-1, ..., 5-N) and the supply voltage adjusting units ...

Description

The The present invention relates to an embedded data processing system with a dynamic monitoring and regulation of the power consumption of its individual components. The The invention relates in particular to a particularly power-efficient one DMA controller for use in such an embedded data processing system.

Under the term embedded data processing systems or Embedded Systems are understood to be systems that have one or more computers or functional system units and this system of User is perceived as a unit. Such embedded Data processing systems are used in many devices, machinery, and equipment household goods to find, taking over control and monitoring functions and the introduction enable new features of such products.

Embedded Systems are also called highly integrated system on chips, for example for telecommunication applications used. Especially mobile devices are battery powered and require one as possible Low power consumption, especially of the embedded data processing system. Complex embedded systems have a large number of individual system units on, such as B. digital signal processors, central processing units, Memory, DMA controllers, interfaces and other elements that when operating the embedded system is not always fully, evenly loaded are. Therefore, in the past, there has been a reduction in power consumption of an embedded system by the definition of so-called Power states, the particular application situations, such as the structure a data connection using a preselected protocol, accordingly he follows. The corresponding operating system of the embedded system detects then in which operating or Performance state of the system exists and lowers, for example, the Supply voltage of unused individual components. These operating conditions have to stated in the design phase of the development of the embedded system become. This is embedded at a very early stage of development for the desired System necessary because only at this early date the respective power consumption determining parameters, such as clock frequency, internal Supply voltages or the temperature taken into account can be and corresponding operating states or performance states of the affected components are stably programmed or designed can. For these reasons can only a clear Number of such operating states for typical Processing situations of the embedded system become. If during the operation of the embedded system events occur previously not defined as a predetermined performance condition, must entire system will be re-analyzed and a new mapping of operating conditions on one as possible Effective allocation of benefits to the individual components new. This is expensive and in the simplest case only by software updates the corresponding operating system possible.

The For example, US 2003/0065960 A1 discloses a corresponding method and system for controlling local supply voltages and clock frequencies in a multiprocessor system. There is an embedded system suggested that several specially equipped microprocessors contains each independently controlling their power consumption. It is in each case a limited number of operational states for each microprocessor considered, so that when designing the appropriate multiprocessor system a defined number of states for clock frequencies and supply voltages must be specified.

In US 2003/0204762 A1 discloses a method which comprises a Adjust the power consumption of a portable computer system allowed, in particular, the particular CPU is throttled. The power consumption of the CPU is provided by measurements to estimate a battery voltage or current. In Dependence on An increasing or decreasing power consumption becomes a Throttling the CPU or resetting in a normal operating state of the CPU made.

In the DE 69909924 T2 is a program-dependent control of the power consumption of individual elements in a circuit arrangement generally described. It is provided time-dependent or program dependent to shut down certain power receiving elements of the circuit.

It Therefore, an object of the present invention is an embedded To create a data processing system through a flexible adaptation of the Power consumption of its individual components to the existing data processing situation particularly power- or power-saving works.

These Task is characterized by an embedded data processing system functional system units with dynamic monitoring and control of the Power consumption of the system units with the features of the claim 1 solved.

An essential idea underlying the invention is any functional system to assign an activity monitoring unit, which provides information about the load or the power requirement of the respective system unit to the operating state monitoring unit by means of the operating state signals. By continuously transmitting this power information, an individual control of at least the corresponding clock and the supply voltage for the system units is possible. In certain processing situations, system units which are less stressed can thereby be shut down or switched off, resulting in an overall lower power consumption of the embedded data processing system. In the operation of the embedded system similar events such. For example, a particular memory access from a system unit to a system unit configured as a memory is quickly detected, and a most favorable configuration for the timing and supply voltages of the affected system units can be set.

In a preferred embodiment At least one further clock adjustment unit is provided, for Forming an intermediate clock signal from the system clock signal for a selection of system units, where the selection of system units is one Power consumption island forms. Often can handle multiple system units that have similar tasks and power consumption requirements to so-called power islands or power receiving islands sum up. It is sufficient then an intermediate clock signal for to provide this selection of system units of the power receiving island.

Prefers is a selection of system units also from a common Supply voltage supplied by the power supply unit is delivered, this selection of system units a Power consumption island forms.

Favorable Way are those of the selection Spatial system units arranged adjacent. It is then further advantageous that the Selection of system units via the system clock signal or intermediate clock signal switchable clock distribution line system is supplied. It is possible then entire part of the clock tree or the clock distribution line system possibly complete shut down, whereby electricity or energy can be saved.

In preferred embodiments The clock adjustment units each have at least one frequency divider on, for gradually generating internal clock signals with a across from the system clock signal multiple clock period. This has the advantage that when switching between different clock frequencies for each System unit a stepped change possible is, causing interference by a clock change as low as possible fail.

In still a preferred embodiment at least one clock adjustment unit for generating a low-frequency clock signal provided from the system clock signal.

In a development of the embedded system according to the invention is the embedded system completely integrated as system on chip. Characterized in that the embedded invention System is particularly energy efficient, is an integration of all system units advantageous on a single chip.

In an advantageous embodiment of the embedded system at least one temperature sensor unit is provided for measuring Operating temperatures in the embedded system and for generating of temperature measuring signals for the operating state monitoring unit. It is also advantageous that at least one voltage sensor unit is provided for measuring supply voltages in the embedded System and for generating voltage measurement signals for the operating state monitoring unit. By means of this additional Parameters Temperature and supply voltage can be controlled by the operating state monitoring unit or the connected power consumption control unit the power allocation by adapted clock frequencies and supply voltages for the system units even cheaper design, or specifically reduce power consumption, if a Operating temperature is too high.

In preferred embodiments are the system units as a microprocessor, DMA controller, digital Signal processor memory device, bus system time measuring device or communication interface.

The respective operating state signals preferably show the power requirement the respective system unit.

Favorable Way is at least one activity monitor with clocked at a lower frequency than the respective system unit. The lower the frequency, the lower the power consumption the respective activity monitoring unit. For many Applications is enough it to generate the operating state signals at relatively low frequency whereby the needed Power consumption is minimized.

Advantageously, the power consumption control unit controls the clock adjustment unit of art that a predetermined target clock frequency for the respective clock adjustment unit is achieved by stepwise switching of the clock frequency. As a result, disturbances due to clock switching are practically impossible.

In preferred embodiments provides a CPU as a system unit cache hit / miss signals, translation Lookaside buffer hit / miss signals (TLB) or merge / no-merge signals as operating state signals the operating state monitoring unit. For example, cache hit / miss signals indicate that the CPU is successful or failed accesses to a cache. Runs a cache access unsuccessful, the CPU must access a slower main memory. Accordingly, the power consumption control unit can clock and supply voltages adjust the system units involved. Similar information is provided by the TLB hit / miss and WTB merge / no-merge signals.

In Further developments of the invention is the power consumption control unit executed as a central processing unit of the embedded system, or the Power consumption control unit is considered part of an operating system of the embedded system.

• a) mindestens einer Schnittstelle zum Ankoppeln einer Peripheriesystemeinheit;
• b) mindestens einer abschaltbaren, mit einem Sendetakt-Signal getakteten Datensendekontrolleinheit zum Senden von Daten an eine angeschlossene Peripheriesystemeinheit, wobei das Sendetaktsignal von einer ersten Taktanpassungseinheit geliefert ist;
• c) mindestens einer abschaltbaren, mit einem Empfangstaktsignal getakteten Datenempfangskontrolleinheit zum Empfangen von Daten von einer angeschlossenen Peripheriesystemeinheit, wobei das Empfangstaktsignal von einer zweiten Taktanpassungseinheit geliefert ist; und
• d) mindestens einer abschaltbaren, mit einem Überwachungstaktsignal getakteten Aktivitätsüberwachungseinheit zum Erzeugen von Betriebszustandssignalen für die Betriebszustandsüberwachungseinheit, wobei das Überwachungstaktsig nal von einer dritten Taktanpassungseinheit geliefert ist, und wobei die Betriebszustandsüberwachungssignale zumindest Informationen über Speicherzugriffsanfragen der Peripheriesystemeinheiten und Datendurchsatzraten an die Betriebszustandsüberwachungseinheit liefert;
• e) wobei die Taktanpassungseinheiten von der Leistungsaufnahmesteuerungseinheit gesteuert sind und die Sende-, Empfangs- und Überwachungstaktsignale in Abhängigkeit von den Speicherzugriffsanfragen und Datendurchsatzraten angepasst sind.

The invention further provides a DMA controller for an embedded data processing system according to the invention with dynamic monitoring and control of the power consumption of the system units with:

• a) at least one interface for coupling a peripheral system unit;
• b) at least one disconnectable data transmit control unit, clocked with a transmit clock signal, for transmitting data to a connected peripheral system unit, the transmit clock signal being provided by a first clock adder;
• c) at least one disconnectable data receiving control unit clocked with a receive clock signal for receiving data from a connected peripheral system unit, the receive clock signal being provided by a second clock adder unit; and
• d) at least one deactivatable activity monitoring unit clocked with a monitoring clock signal for generating operating status signals to the operating status monitoring unit, the monitoring clock signal being provided by a third clock adjusting unit, and wherein the operating status monitoring signals provide at least information about memory access requests of the peripheral system units and data throughput rates to the operating status monitoring unit;
• e) wherein the clock adjustment units are controlled by the power consumption control unit and the transmission, reception and monitoring clock signals are adjusted in response to the memory access requests and data throughput rates.

Of the DMA controller according to the invention can be designed to save energy because the internal logic circuits, such as data reception control unit and data transmission control unit independently of each other can be clocked. By doing that, the DMA controller uses its activity monitoring unit the power consumption control unit information about the Memory accesses and desired Transmitted throughput rates, the clock frequency is always adjusted so that a minimum power consumption which is sufficient to fulfill the corresponding task.

In a preferred embodiment is for the DMA controller at least A switch-off configuration register for configuration data of the DMA controller intended. Preferably, by the power consumption control unit by means of control signals an upper and a lower limit of the respective Clock frequencies for the transmit, receive, and monitor clock signals established.

In a further preferred embodiment of the DMA controller according to the invention is each a descriptor table for the data transmission control unit and the data receiving control unit, wherein the respective Data transmission or reception control unit is deactivated if not a valid one Descriptor entry exists. A descriptor contains information for a segment from the linear address space. It is given a base address in it, and the segment size of the memory access. If there is no valid entry in the respective descriptor table, then it favorable according to the invention deactivate the respective data transmission or reception control unit, which reduces the power consumption of the DMA controller.

Further advantageous embodiments of the invention are the subject of the dependent claims and the Description of the embodiments with reference to the drawings.

in the The invention is described below with reference to the attached schematic Figures closer explained. It shows:

1 an embedded data processing system according to the invention;

2 a preferred embodiment of the embedded data processing system according to the invention;

3 an embodiment of the embedded data processing system according to the invention;

4 an embodiment of a DMA controller according to the invention; and

5 : an example of an inventive adaptation of the power consumption of a DMA controller.

In the figures are the same or not stated otherwise functionally identical elements with the same reference numerals Service.

The 1 shows an embedded data processing system according to the invention 1 ,

The embedded system 1 has a supply voltage unit 2 for generating a system supply voltage VDD, VSS, a clock generation unit 3 for generating a system clock signal CLKS and a plurality of clocked system units 4-1 . 4-2 , ..., 4-N to each of which the system clock signal CLKS and the system supply voltages VDD, VSS are supplied.

Each clocked system unit 4-1 . 4-2 , ..., 4-N has a controllable clock adjustment unit 5-1 . 5-2 , ..., 5-N on each of which the system clock signal CLKS is supplied. The system units 4-1 . 4-2 , ..., 4-N each further comprise a controllable supply voltage adjustment unit 6-1 . 6-2 , ..., 6-N on, in each case the supply voltages VDD, VSS are supplied. The system units 4-1 . 4-2 , ..., 4-N For example, DMA controllers, memory, interface devices, or other functions that work in functional cores 7-1 . 7-2 , ..., 7-N the system units 4-1 . 4-2 , ..., 4-N are realized.

The embedded data processing system according to the invention 1 has a so-called system performance monitor 8th on with an operating state monitoring unit 9 , a power consumption control unit 10 and a storage device 11 ,

The system 1 also has a temperature sensor unit 12 , which measures operating temperatures and corresponding temperature measuring signals TMS to the operating state monitoring unit 9 sends. There is also a voltage sensor unit 13 provided for measuring supply voltages and generating corresponding voltage measurement signals SMS, which also to the operating state monitoring unit 9 are guided.

Each system unit 4-1 . 4-2 , ..., 4-N is an activity monitoring unit 14-1 . 14-2 , ..., 14-N assigned to generate operating state signals BZS1, BZS2, ..., BZSN, which are also the operating state monitoring unit 9 are fed.

The operating state monitoring unit 9 evaluates the corresponding operating state signals BZS1, BZS2, ..., BZSN and supplies to the power consumption control unit 10 Operating state information BZI of the entire embedded system 1 ,

The of the activity monitoring units 14-1 , ..., 14-N supplied operating state signals BZS1, ..., BZSN, for example, information about outstanding CPU read operations, upcoming DMA (Direct Memory Access) transactions or required DMA data paths. A Risc-core CPU may output, as an operating state signal, for example, via its respective activity monitoring unit, the CPU load calculated from the executed commands and the time of one CPU cycle. In a digital signal processor as a system unit, the respective activity monitoring unit supplies, for example, the DSP load. In the case of a DMA controller, possible operating state signals are the number of DMA transactions to be performed and DMA data threads. For memory controllers, memory usage can be used as the operating state signal. For standard peripheral devices, such as interfaces, or system time measuring devices, the operating state may also be an activity signal.

In the system performance monitor 8th For example, in the operating system of the embedded data processing system 1 can be integrated, thus information about the load or idle times of all processing system units 4-1 , ..., 4-N known so that the power consumption control unit 10 the power consumption of individual system units 4-1 , ..., 4-N for example, by a controlled change in the timing of individual system units 4-1 , ..., 4-N by control signals CT to the corresponding clock adjustment unit 5-1 , ..., 5-N regulates. Also, a targeted adjustment of the respective supply voltages can via control signals CT to the corresponding Versorgungsspannungsanpas sung unit 6-1 , ..., 6-N respectively. A control of the timing and individual supply voltages affects the power consumption of the individual units 4-1 , ..., 4-N because the power P is in each case proportional to the supply voltage V and clock frequency f PαU ² f.

In the storage device 11 are, for example, supply voltage and clock signal configurations of the embedded system 1 stored in an event database, which is for a Given combination of operating state signals are characteristically favorable. The power consumption control unit 10 can also update this event database during operation, and so for the power consumption of the entire system 1 Select the most favorable configuration of cycles and supply voltages for the individual system units.

The embedded data processing system according to the invention, with its dynamic monitoring and regulation of the power consumption of the individual units, has the advantage that it is characterized by the closed loop of activity monitoring units 14-1 , ..., 14-N , the operating condition monitoring unit 9 the power consumption control unit 10 and the clock adjustment and supply voltage adjustment units 5-1 , ..., 5-N . 6-1 , ..., 6-N the respective power consumption are continuously regulated and so the resulting power consumption can be optimally minimized.

The 2 shows a particularly preferred embodiment of an embedded data processing system according to the invention 10 ,

There are power receiving islands 15 . 16 . 17 each defining a selection of system units which are clocked with a common intermediate clock signal CLK1, CLK2, CLK3 and are each supplied with a supply voltage V1, V2, V3.

In this case, initially a system clock signal CLKS from a clock generation unit 3 supplied by controllable clock adjustment units 18 . 19 . 20 to the corresponding clock signals CLK1, CLK2, CLK3 for the power receiving islands 15 . 16 . 17 to be brought. The clock adjustment units 18 . 19 . 20 are by a device for the step change of the clock frequency 21 controlled by control signals CT1, CT2, CT3. This device 21 is again from the system performance monitor 8th controlled or the power consumption control unit, not shown here. The clock adjustment units 18 . 19 . 20 are controlled such that the respective clock frequencies of the clock signals CLK1, CLK2, CLK3 are adjustable in a fine gradation. To do this, submit the power consumption control unit of the system performance monitor 8th a target clock frequency for the respective power receiving island 15 . 16 . 17 to the device for the stepwise adaptation of the clock frequencies 21 , which by stepwise switching of the respective clock frequency, for example, the first clock signal CLK1, reaches the target clock frequency. These are in the clock adjustment units 18 . 19 . 20 Frequency divider provided which generate the corresponding clock signal CLK1, CLK2, CLK3 from the system clock signal CLK. In this case, the generated internal clock signals CLK1, CLK2, CLK3 clocks with a multiple clock period compared to the system clock signal. Thus, a smooth transition between different clock signal frequencies is achieved when the system performance monitor 8th recognizes that the power consumption of a power consumption island 15 . 16 . 17 either increased or decreased.

The advantage of the common clock frequencies or clock signals CLK1, CLK2, CLK3 for the respective power receiving islands 15 . 16 . 17 Amongst other things, the associated system units consist in that the corresponding clock distribution line system or the clock distribution tree for the power receiving islands 15 . 16 . 17 switchable executable. Thereby, power dissipation in the clock distribution tree can be prevented when the system units of the power reception control island are deactivated. The stepwise adjustment up to a target clock frequency also allows a smaller dimensioning of the power supply unit 2 because the fine gradation between different controllable clock frequencies no power peaks can occur during switching. Within the power receiving islands 15 . 16 . 17 For example, the corresponding system units according to the invention can be designed such that the corresponding activity monitoring units are clocked at a lower frequency than the respective system unit itself. This additionally saves power consumption.

In the 3 is an example of a system-on-chip 101 with only one power receiving island 22 shown.

It is again a system performance monitor 8th provided, which is a power supply unit 2 and a clock control unit 18 controls. The power consumption island 22 contains four system units 4-1 . 4-2 . 4-3 . 4-4 , here exemplified as the central processing unit 4-1 , DMA controller 4-2 and two peripheral system units 4-3 . 4-4 are shown. The system units 4-1 , ..., 4-4 each have activity monitoring units 14-1 . 14-2 . 14-3 . 14-4 on, the operating state signals BZS1-BZS4 to the system performance monitor 8th deliver. The central processor unit 4-1 and the DMA controller unit 4-2 are provided here as master units and via a suitable bus system 23 to the peripheral system units running as slave units 4-3 and 4-4 coupled. The peripheral unit 4-4 is here exemplified as an interface unit designed to externally form, for example, a USB bus.

The supply voltage unit 2 supplies a supply voltage VDD, VSS to the power receiving island 22 , and the clock control unit 18 supplies a corresponding clock signal CLK1 the power consumption island 22 , The clock control unit 18 is designed so that the corresponding frequencies of the clock signals CLK1 is performed in a fine gradation, so that arise when switching from one to the next clock frequency no power consumption peaks. This leads to a small-sized supply voltage unit 2 , Further, the clock control unit is designed to be fully implemented by the system performance monitor 8th can be switched off and thus no output clock signal CLK1 to the power receiving island 22 supplies. As a result, the entire line tree, which is used for distribution of the corresponding clock signal CLK1, is not current-flowed through, whereby considerable power is saved.

In the exemplary power receiving island shown here 22 is also the internal bus system 23 with that of the clock control unit 18 clock signal CLK1 clocked. In certain power receiving islands, which mainly comprise peripheral system units, it may be advantageous to provide an island with a particularly low clock frequency.

In the 4 For example, a DMA controller is shown as a system unit for use in an embedded data processing system according to the invention.

The DMA controller 4 has interfaces 24 . 25 . 26 on, for coupling peripheral system units 27 . 28 . 29 , It is a data transmission control unit 30 and a data reception control unit 31 intended. Furthermore, the DMA controller has 4 a send / receive arbiter 32 via the DMA controller to a memory controller 33 is coupled. It is a clock control unit 18 provided, the respective clock signals CLK1, CLK2, CLK3, CLK4 to the transmission and data reception control unit, a configuration register 34 and the activity monitor 14 supplies.

The activity monitoring unit 14 is to the interface device 24 . 25 . 26 , the data transmission control unit 30 and the data reception control unit 31 coupled and receives status information about transfer requests to be processed, activities of the data transmission and data reception control unit 30 . 31 and requested data throughput rates from the peripheral system units 27 . 28 . 29 ,

In the DMR controller according to the invention 4 is also a disable configuration register 34 provided to a CPU 35 is coupled in the corresponding embedded system. The interface units 24 . 25 . 26 , the configuration register 34 , the data reception control unit 31 and the data transmission control unit 30 are each operable with different clock frequencies, and the different clock signals CLK1-CLK4 and their clock frequencies are through the system performance monitor 8th given the frequencies in dependence on the operating state signals BZS, which of the activity monitoring unit 14 be delivered, determined. This causes the individual logic elements in the DMA controller 4 can be individually clocked, the power consumption of the DMA controller 4 be reduced. For example, the clock frequency for the data reception control unit 31 be reduced when from the peripheral units 27 . 28 . 29 there are no requests to send data. This allows data requests from the peripheral units 27 . 28 . 29 as status information of the activity monitoring unit 14 and supplies such information as operating state signals to the system performance monitor, the power allocation may be in the form of clock frequencies to the functional blocks 30 . 31 . 34 of the DMA controller 4 done efficiently. In addition, the peripheral units 27 . 28 . 29 even brought into a state of low power consumption when no data transfer with these peripheral units is requested. In this case, the system performance monitor turns off 8th the corresponding clock signals.

In the 5 is exemplified when the data reception control unit 31 is put into a sleep state or an intermediate state with low power consumption.

If a peripheral unit 27 acting as a data source, directing a memory access request to the DMR controller becomes the data reception control unit 31 or their supplied clock signal CLK2 increases if a corresponding DMA channel is activated and if at the same time a valid descriptor entry in the descriptor list 36 is present for the activated DMA channel. Is the data reception control unit 31 thus activated by a similar wake-up request, the DMA controller receives from the peripheral unit 27 over the interface 24 and the data reception control unit 31 Data and transmits them to the docked memory controller 33 ,

Similarly, the configuration register can also be used 35 out 4 switched off or put into a power-saving state, if the part of the CPU 35 no access to the register 34 takes place, the data reception control unit 31 is deactivated and the data transmission control unit 30 is disabled. Once one of these three conditions is not met, the configuration register becomes 35 started up or clocked.

An advantage of the DMA controller according to the invention is, in particular, that the functional units z. B. the Datenendekon troll unit 30 individually tactile, are and therefore draws power only when needed. Overall, the DMA controller can thus be extremely energy-efficient. The setting of the respective operating clock frequency is preferably carried out by specifying a frequency range for the individual clock signals by the system performance monitor 8th , In addition, it is of particular advantage that if the system performance monitor 8th As part of the embedded system operating system, the operating system is aware of both active or in-progress data transfers within the DMA controller and can regulate performance allocation accordingly.

Even though the present invention above based on preferred embodiments described, it is not limited thereto but variously modifiable. In particular, the combination of power receiving islands and configure further system units as required. As with the example of the DMA controller If the system units themselves are hierarchically executable with activity monitors, then so that also separates the functional cores of the system units themselves and are specifically tactile to reduce power consumption compared to one To reach normal operation. Furthermore, any embedded data processing system is made up functional system units executable, without the inventive device an operating state monitoring and power consumption control.

1

embedded Data processing system

2

Power supply unit

3

Clock generation unit

4

system unit

5

Stroke adjusting unit

6

Power supply matching unit

7

functional core

8th

System Performance Monitor

9

Operating status monitoring unit

10

Power consumption control unit

11

memory device

12

Temperature sensor unit

13

Voltage sensor unit

14

Activity monitoring unit

15 16, 17

Power consumption Island

18 19, 20

Stroke adjusting unit

21

Facility for frequency control

22

Power consumption Island

23

bus system

24 25, 26

Interface unit

27 28, 29

peripheral unit

30

Data transmission control unit

31

Data reception control unit

32

Transmission / Empfangsarbiter

33

Memory controller

34

configuration register

35

CPU

36

descriptor

100 101

embedded system

BZI

Operating state information

SMS

Voltage measurement signal

TMS

Temperature measurement signal

BZS1-BZSN

Operating condition signals

VDD, VSS

supply voltage

CLKS, CLK1-CLK4

control signal

V1-V3

supply voltage

Claims (20)

Embedded data processing system ( 1 ) from functional system units ( 4-1 , ..., 4-N ) with dynamic monitoring and regulation of the power consumption of the system units ( 4-1 , ..., 4-N ) with: a) at least one power supply unit ( 2 ) for generating a system supply voltage (VDD, VSS); b) at least one clock generation unit ( 3 ) for generating a system clock signal (CLKS); c) several clocked system units ( 4-1 . 4-2 , ..., 4-N ), each having at least one controllable clock adaptation unit ( 5-1 , ..., 5-N ), a controllable supply voltage adjustment unit ( 6-1 , ..., 6-N ) and an activity monitoring unit ( 14-1 , ..., 14-N ) for generating operating state signals BZS1, ..., BZSN) of the respective system unit ( 4-1 , ..., 4-N ) exhibit; d) an operating state monitoring unit ( 9 ) for evaluating the operating state signals (BZS1, ..., BZSN) and for providing operating state information (BZI) of the embedded system ( 1 ); e) a memory device ( 11 ) for storing an event database with embedded system supply voltage and clock signal configurations ( 1 ) for predetermined combinations of the operating state signals (BZS1-BZSN); and f) a power consumption control unit ( 10 ) for controlling the clock adjustment units ( 5-1 , ..., 5-N ) and the supply voltage adjustment units ( 6-1 , ..., 6-N ) as a function of the operating state information (BZI) for dynamically controlling the power consumption of the individual system units th ( 4-1 , ..., 4-N ); g) where the power consumptions are continuously controlled and the event database in the operation of the embedded system ( 1 ) from the power consumption control unit ( 10 ) is continuously adjusted. Embedded system ( 1 ) according to claim 1, characterized in that at least one further clock adjustment unit ( 18 . 19 . 20 ) is provided for forming an intermediate clock signal (CLK1, CLK2, CLK3) from the system clock signal (CLK) for a selection of system units, wherein the selection of system units comprises a power receiving island (CLK1). 15 . 16 . 17 ). Embedded system ( 1 ) according to claim 1 or 2, characterized in that a selection of system units of a common supply voltage (V1, V2, V3) is supplied by the power supply unit ( 2 ), the selection of system units comprising a power receiving island ( 15 . 16 . 17 ). Embedded system ( 1 ) according to claim 2 or 3, characterized in that the selection of the associated system units are arranged spatially adjacent. Embedded system ( 1 ) according to at least one of the preceding claims 2-4, characterized in that the selection of system units, the system clock signal (CLK) or the intermediate clock signal (CLK1, CLK2, CLK3) is supplied via a switchable clock distribution line system. Embedded system ( 1 ) according to at least one of the preceding claims, characterized in that the clock adjustment units ( 5-1 , ..., 5-N . 18 . 19 . 20 ) each comprise at least one frequency divider for the stepwise generation of internal clock signals having a clock cycle that is a multiple of the system clock signal (CLK). Embedded system ( 1 ) according to at least one of the preceding claims, characterized in that the embedded system is designed completely integrated as a system on chip. Embedded system ( 1 ) according to at least one of the preceding claims, characterized in that at least one temperature sensor unit ( 12 ) is provided for measuring operating temperatures in the embedded system ( 1 ) and for generating temperature measurement signals (TMS) for the operating state monitoring unit ( 9 ). Embedded system ( 1 ) according to at least one of the preceding claims, characterized in that at least one voltage sensor unit ( 13 ) is provided for measuring supply voltages in the embedded system ( 1 ) and for generating voltage measurement signals (SMS) for the operating state monitoring unit ( 9 ). Embedded system ( 1 ) according to at least one of the preceding claims, characterized in that at least one system unit ( 4-1 , ..., 4-N ) is designed as a microprocessor, DMA controller, digital signal processor, memory device, bus system, system time measuring device or communication interface. Embedded system ( 1 ) according to at least one of the preceding claims, characterized in that the respective operating state signals (BZS1, BZS2) the power requirement of the respective system unit ( 4-1 , ..., 4-N ) Show. Embedded system ( 1 ) according to at least one of the preceding claims, characterized in that at least one of the activity monitoring units ( 14-1 , ..., 14-N ) is clocked at a lower frequency than the respective system unit ( 4-1 , ..., 4-N ). Embedded system ( 1 ) according to at least one of the preceding claims, characterized in that the power consumption control unit ( 10 ) the clock adjustment units ( 5-1 , ..., 5-N . 18 . 19 . 20 ) such that a predetermined target clock frequency for the respective clock adjustment unit ( 5-1 , ..., 5-N . 18 . 19 . 20 ) is achieved by stepwise switching of the clock frequency. Embedded system ( 1 ) according to at least one of the preceding claims, characterized in that a CPU as a system unit provides cache hit / miss signals, translation lookaside buffer hit / miss signals and / or write table merge / no-merge signals as operating state signals. Embedded system ( 1 ) according to at least one of the preceding claims, characterized in that the power consumption control unit ( 10 ) as the central processing unit of the embedded system ( 1 ) is executed. Embedded system ( 1 ) according to at least one of the preceding claims, characterized in that the power consumption control unit ( 10 ) as part of an embedded system operating system ( 1 ) is executed. DMA controller ( 4 ) for an embedded data processing system ( 1 ) with dynamic monitoring and regulation of the power consumption of the system units ( 4-1 , ..., 4-N ) according to at least one of the preceding claims 1-16, with: a) at least one interface ( 24 . 25 . 26 ) for coupling a peripheral system unit ( 27 . 28 . 29 ); b) at least one turn-off data transmission control unit clocked with a transmission clock signal (CLK1) ( 30 ) for sending data to a connected peripheral system unit ( 27 . 28 . 29 ), wherein the transmit clock signal from a first clock adjustment unit ( 18 ) is delivered; c) at least one disconnectable data reception control unit clocked by a receive clock signal (CLK2) ( 31 ) for receiving data from a connected peripheral system unit ( 27 . 28 . 29 ), wherein the receive clock signal (CLK2) from a second clock adjustment unit ( 18 ) is delivered; d) at least one deactivatable activity monitoring unit clocked with a monitoring clock signal (CLK4) ( 14 ) for generating operating state signals (BZS) for the operating state monitoring unit ( 8th . 9 ), wherein the monitoring clock signal (CLK4) from a third clock adjustment unit ( 18 ), and wherein the operating state monitoring signals (BZS) at least information about memory access requests of the peripheral units ( 27 . 28 . 29 ) and data throughput rates to the operating state monitoring unit ( 8th . 9 ) supplies; e) the clock adjustment units ( 18 ) from the power consumption control unit ( 8th . 10 ) and the transmit, receive and monitor clock signals (CLK1, CLK2, CLK3) are adjusted in response to the memory access requests and data throughput rates. DMA controller ( 4 ) according to claim 17, characterized in that at least one deactivatable configuration register ( 34 ) for configuration data of the DMA controller ( 4 ) is provided. DMA controller ( 4 ) according to one of claims 17 or 18, characterized in that by the power consumption control unit ( 9 . 10 ) by means of control signals (CT) an upper and a lower limit of the respective clock frequencies of the transmission, reception and monitoring clock signals (CLK1-CLK3) is fixed. DMA controller ( 4 ) according to at least one of claims 17-19, characterized in that in each case a descriptor table ( 36 ) for the data transmission control unit ( 30 ) and the data reception control unit ( 31 ), wherein the respective data transmission or reception control unit ( 30 . 31 ) is deactivated if there is no valid descriptor entry.