CN1581699B - Phase swallowing device and signal generating device using same - Google Patents
Phase swallowing device and signal generating device using same Download PDFInfo
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- CN1581699B CN1581699B CN 03153401 CN03153401A CN1581699B CN 1581699 B CN1581699 B CN 1581699B CN 03153401 CN03153401 CN 03153401 CN 03153401 A CN03153401 A CN 03153401A CN 1581699 B CN1581699 B CN 1581699B
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- phase place
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- clock pulse
- phase
- engulfing
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Abstract
The signal generation device includes following parts: a timing pulse generator in multiple phases receives a reference timing pulse, and generates reference timing pulse in multiple phases, which are same frequency but in different phases; a multiplexer receives multiple reference timing pulses in multiple phases, an selects a output reference timing pulse from the said received pulses based on a phase selection signal; phase phagocytosis control unit possesses a comparing unit and receives a phase phagocytosis quantity, then generates a phase control signal; a timing selection unit receives phase control signal and generates phase selection signal. Comparison is carried out between reference signal and phase phagocytosis quantity not according to bit sequence. Thus, phase control signal is not continuous and as equipartition in order to lower cycle jitter quantity of output signal of signal generation device.
Description
Technical field
The invention relates to phase place and engulf device and signal generation device, particularly engulf device about the phase place that can reduce the amount of jitter of exporting clock pulse and engulf the signal generation device of device with using this phase place.
Background of invention
Figure 1 shows that the Organization Chart of known signal generation device.This signal generation device 10 is to produce the frequency synthesis clock pulse, and this clock pulse can be adjusted frequency according to demand.This signal generation device 10 comprises a leggy clock pulse generation unit (multi-phase clock generator) 11, one multiplexer (multiplexer) 12, a phase place is engulfed control unit (phase-swallow control unit) 14 and timing selection unit (clock selector) 15.Leggy clock pulse generation unit 11 is to produce identical but the leggy that phase place is different of a plurality of frequencies with reference to clock pulse CKn-1, CKn-2..., CK0 according to one with reference to clock pulse.The leggy that Fig. 2 shows 8 outs of phase with reference to clock pulse CK7, CK6 ..., the waveform of CK0.Multiplexer 12 receives a plurality of leggies with reference to clock pulse CKn-1, CKn-2..., CK0, and selects these leggies with reference to the clock pulse output of clock pulse according to a Selecting phasing signal, uses the signal that produces an output clock pulse.Phase place is engulfed 14 of control units and is engulfed volume production according to phase place and give birth to a phase control signal (swallow control signal, SCS).Clock pulse selected cell 15 is selected signal according to phase control signal SCS output phase again.Clock pulse selected cell 15 can be a counter, and take phase control signal as triggering signal.When phase control signal was enabled, counter just added 1, so the Selecting phasing signal also adds 1, used allowing multiplexer 12 select the reference clock pulse of next phase place as the signal of output clock pulse.So, according to the activation number of times of phase control signal, i.e. the frequency of the signal of the output clock pulse of fine-tuning this signal generation device 10.
General traditional phase place is engulfed control unit and can be utilized a delta-sigma modulation device (sigma-deltaModulator), reach and accurately control output frequency, and the requirement that dither cycle is little, if take First-order Integral triangle modulator as example, embodiment can be an accumulator (Accumulator), and its circuit area is still greater than general logic element (reaching lock or lock, flip-flop).
For the circuit design requirement of the small circuit area occupied size of needs, it then is to utilize a counter (can be considered a plurality of flip-flop forms) to finish that general traditional phase place is engulfed control unit, please refer to Fig. 3.Fig. 3 is the calcspar that the phase place of Fig. 1 is engulfed control unit.As shown in the drawing, phase place is engulfed control unit 14 and is comprised a counter 31, a comparator 32 and a buffer 33.Counter 31 is clock pulse numbers of counting clock signal, and the output reference signal is to comparator 32.And buffer 33 is temporary phase place amounts of engulfing.Comparator 32 is the reference signal exported of comparison counter 31 and the phase place amount of engulfing of buffer 33.That is, when reference signal during less than the phase place amount of engulfing, then with phase control signal SCS activation (enable), otherwise when reference signal during more than or equal to the phase place amount of engulfing, then with phase control signal SCS forbidden energy (disable).So as shown in Figure 3, the low bit of the low bit of reference signal and the phase place amount of engulfing compares, and the high bit of the high bit of reference signal and the phase place amount of engulfing relatively.
In the framework of Fig. 3, because engulfing of its phase place is successional.For example: if phase difference is 3 phase places, then to engulf method be respectively to engulf a phase place in the cycle at continuous 3 clock pulses to known phase place.Therefore the dither cycle (cycle-cycle jitter) of the output clock pulse of signal generation device 10 is larger.According to system requirements designs, can with the signal of output clock pulse divided by suitable value, reach required frequency.Namely utilize the frequency eliminator (not shown) to receive the clock signal that multiplexer 12 is exported, and carry out frequency elimination.When 8 clock pulse cycles will be engulfed (swallow) 3 phase places continuously, and frequency eliminator is divided by 3, and then maximum dither cycle amount is 3 Δ T, and wherein Δ T is that two adjacent leggies are with reference to the phase difference of clock pulse.And the phase place of engulfing is more, and its maximum dither cycle amount is just larger.
Therefore, can the little requirement of coincident circuit area size, and effectively to reduce the dither cycle amount be an important topic.
Summary of the invention
The purpose of this invention is to provide a kind of phase place that reduces the dither cycle amount engulfs device and uses this phase place to engulf the signal generation device of device.
A kind of phase place provided by the invention is engulfed device, be to receive a plurality of leggies with reference to clock pulse, and produce an output clock pulse, and those leggies is identical with reference to its frequency of clock pulse, phase place is different, and this phase place is engulfed device and comprised:
One multiplexer is to receive those leggies with reference to clock pulse, and according to a Selecting phasing signal select those leggies with reference to clock pulse one with reference to clock pulse output, as described output clock pulse; And
One phase place is engulfed control unit, according to a phase place amount of engulfing and a reference signal, and by non-bit mode sequentially, relatively after this phase place amount of engulfing and this reference signal, exports this Selecting phasing signal.
Described phase place is engulfed device and is also comprised a counter, in order to export this reference signal.
It is that those bits of this reference signal are made comparisons with those corresponding bits of this phase place amount of engulfing with the anti-phase order of bit that described phase place is engulfed control unit.
A kind of signal generation device comprises:
One leggy clock pulse generator receives one with reference to clock pulse, and produces identical but the leggy that phase place is different of a plurality of frequencies with reference to clock pulse;
One multiplexer receives those leggies with reference to clock pulse, and according to a Selecting phasing signal select those leggies with reference to clock pulse one with reference to clock pulse output, as described output clock pulse;
One phase place is engulfed control unit, has a comparing unit and receives a phase place amount of engulfing, and produce a phase control signal; And
Timing selection unit receives described phase control signal, and produces described Selecting phasing signal;
Wherein, described comparing unit is with different bit order relatively this phase place amount of engulfing and a reference signal, and exports this phase control signal.
The described phase place amount of engulfing and this reference signal are all the signal with a plurality of bits, and this phase place is engulfed control unit and is comprised a plurality of bit comparing units, in order to relatively the m bit of this phase place amount of engulfing and the n bit of this reference signal, to export this phase control signal, wherein, m, n is all positive integer, and m is not equal to n.
Described signal generation device, wherein this different bit sequentially is the bit reverse sequence.
Described signal generation device also comprises a counter, in order to export this reference signal.
Described phase place is engulfed control unit and is also comprised a buffer, in order to store and to export this phase place amount of engulfing.
Because phase place is engulfed in the control unit, comparator is to come comparison reference signal and the phase place amount of engulfing with different bit order, therefore this phase place is engulfed phase control signal that control unit produces and discontinuous, and can be considered mean allocation, use the dither cycle amount of the output signal that reduces signal generation device.
Description of drawings
Figure 1 shows that the Organization Chart of known signal generation device;
Fig. 2 is the waveform schematic diagram of a plurality of leggy clock pulses;
Fig. 3 is the calcspar that known phase place is engulfed control unit;
Fig. 4 shows the Organization Chart of signal generation device of the present invention;
Fig. 5 shows that the phase place of Fig. 4 engulfs the schematic diagram of control unit;
Fig. 6 shows the value of the counter that the comparator of Fig. 5 receives;
Fig. 7 shows that the different corresponding phase places of the phase place amount of engulfing engulfs schematic diagram, and the zone of its bend is the zone of phase control signal SCS activation, and N is the phase place amount of engulfing.
Embodiment
Describing phase place of the present invention in detail below with reference to accompanying drawing engulfs device and uses this phase place to engulf the signal generation device of device.
Because it is successional that the phase place in the known framework is engulfed, so the dither cycle amount is larger.So the present invention proposes a kind of framework phase place is engulfed dispersion in order to reduce the dither cycle amount.
Fig. 4 shows the Organization Chart of signal generation device of the present invention.Signal generation device 40 of the present invention comprises a leggy clock pulse generation unit 41, a phase place is engulfed device 42 and a frequency eliminator 43.Device 42 comprises a multiplexer 421, a phase place is engulfed control unit 422 and timing selection unit 423 and phase place is engulfed.Leggy clock pulse generation unit 41 is to produce identical but the leggy that phase place is different of a plurality of frequencies with reference to clock pulse CKn-1, CKn-2..., CK0 according to one with reference to clock pulse.Multiplexer 421 receives a plurality of leggies with reference to clock pulse, and selects these leggies to export with reference to clock pulse with reference to one of clock pulse according to a Selecting phasing signal.Phase place is engulfed 422 of control units and is engulfed volume production according to phase place and give birth to a phase control signal SCS.Clock pulse selected cell 423 is selected signal according to phase control signal SCS output phase again.The difference of signal generation device of the present invention 40 and known signal generation device is that phase place is engulfed the phase control signal that control unit 422 produces and disperseed, and is not successional.Because the framework of leggy clock pulse generation unit 41, multiplexer 421, frequency eliminator 43 and the clock pulse selected cell 423 of signal generation device 40 and function and known signal generation device are identical, in this no longer repeat specification.
Fig. 5 shows that the phase place of Fig. 4 engulfs the schematic diagram of control unit.As shown in the drawing, phase place is engulfed control unit 422 and is comprised a counter 51, a comparator 52 and a buffer 53.Counter 51 is clock pulse numbers of counting clock signal, and output count value (reference signal) is to comparator 52.And buffer 53 is temporary phase place amounts of engulfing.Phase place engulf control unit 422 and the phase place of Fig. 3 engulf the difference of control unit be counter 51 be connected to comparator 52 high and low bit out of order.That is the C2 of highest order unit that the inferior low bit C1 that the minimum bit C0 of counter 51 is connected to A2, the counter 51 of comparator 52 is connected to the A1 of comparator 52, counter 51 is connected to the A0 of comparator 52; And the minimum bit D0 of buffer 53 is connected to the B2 that the D2 of highest order unit that the inferior low bit D1 of B0, the buffer 53 of comparator 52 is connected to the B1 of comparator 52, buffer 53 is connected to comparator 52.Fig. 6 shows the value of the counter that comparator receives.As shown in Figure 6, clock signal is inputed in the comparator 52 with bit reverse (bit reverse) order, come to make comparisons with the phase place amount of engulfing, so its count value can be broken up.According to this characteristic, relatively after this count value and the phase place amount of engulfing, the output signal of this comparator is also discontinuous, approximately can be considered dispersedly and distributes for comparator.Certainly, the implementation method of its circuit is not limited to above-mentioned description, directly with the phase place amount of engulfing with reference to clock pulse in the mode not according to the bit order, the logical operations such as utilization and lock or anti-or lock also do not break away from the spirit of utilizing non-bit sequentially to reach dispersion effect proposed by the invention.
Fig. 7 shows that the corresponding phase place of the different phase place amounts of engulfing suppresses situation, and the zone of its bend is the zone of inhibitory control signal SCS activation, and N is the phase place amount of engulfing.Situation shown in Figure 7 is that hypothesis has 8 leggies with reference to clock pulse.As shown in Figure 7, the time point engulfed of phase place is to be spread out.Known framework, its maximum dither cycle amount is directly proportional with the number of phases N that engulfs.And maximum cycle amount of jitter of the present invention has two kinds of situations, and when the divisor of frequency eliminator was even number, its maximum cycle amount of jitter was 0 or Δ T, and wherein Δ T is that two adjacent leggies are with reference to the phase difference of clock pulse.And when the divisor of frequency eliminator was odd number, its maximum cycle amount of jitter was 2 Δ T.
So the output clock pulse that signal generation device lock of the present invention produces can effectively reduce its amount of jitter.Though more than with embodiment the present invention is described, therefore do not limit scope of the present invention, only otherwise break away from main idea of the present invention, the sector person can carry out various distortion or change.
Claims (13)
1. a phase place is engulfed device, receives a plurality of leggies with reference to clock pulse, and produces an output clock pulse, and leggy is identical with reference to the frequency of clock pulse, phase place is different, it is characterized in that this phase place engulfs device and comprise:
One multiplexer receives leggy with reference to clock pulse, and selects leggy to export with reference to clock pulse with reference to one in the clock pulse according to a Selecting phasing signal, as described output clock pulse; And
One phase place is engulfed control unit, according to a phase place amount of engulfing and a reference signal, and by non-bit mode sequentially, relatively after this phase place amount of engulfing and this reference signal, produces phase control signal; And
Timing selection unit is exported this Selecting phasing signal according to this phase control signal.
2. phase place as claimed in claim 1 is engulfed device, it is characterized in that this phase place amount of engulfing and this reference signal are all the signal with a plurality of bits, and this phase place is engulfed control unit and is comprised a plurality of bit comparing units, in order to relatively the m bit of this phase place amount of engulfing and the n bit of this reference signal, to export this Selecting phasing signal, wherein, m, n is all positive integer, and m is not equal to n.
3. phase place as claimed in claim 2 is engulfed device, it is characterized in that this phase place engulfs control unit and also comprise a buffer, in order to store and to export this phase place amount of engulfing.
4. phase place as claimed in claim 2 is engulfed device, it is characterized in that this phase place engulfs control unit and also comprise a counter, in order to export this reference signal.
5. phase place as claimed in claim 1 is engulfed device, it is characterized in that it is that the order that a plurality of bits of this reference signal are put upside down with the height bit is made comparisons with corresponding a plurality of bits of this phase place amount of engulfing that this phase place is engulfed control unit.
6. signal generation device is characterized in that comprising:
One leggy clock pulse generator receives one with reference to clock pulse, and produces identical but the leggy that phase place is different of a plurality of frequencies with reference to clock pulse;
One multiplexer receives these a plurality of leggies with reference to clock pulse, and according to a Selecting phasing signal select these a plurality of leggies with reference to clock pulse one with reference to clock pulse output, as the output clock pulse;
One phase place is engulfed control unit, has a comparing unit and receives a phase place amount of engulfing, and produce a phase control signal; And
Timing selection unit receives this phase control signal, and produces this Selecting phasing signal;
Wherein, this phase place is engulfed control unit the phase place amount of engulfing that receives is offered described comparing unit, and described comparing unit is with non-bit order relatively this phase place amount of engulfing and a reference signal, and exports this phase control signal.
7. signal generation device as claimed in claim 6, it is characterized in that this phase place amount of engulfing and this reference signal are all the signal with a plurality of bits, and this comparing unit is the comparing unit with a plurality of bits, in order to relatively the m bit of this phase place amount of engulfing and the n bit of this reference signal, to export this phase control signal, wherein, m, n is all positive integer, and m is not equal to n.
8. signal generation device as claimed in claim 6 is characterized in that this non-bit sequentially is the bit reverse sequence.
9. signal generation device as claimed in claim 6 is characterized in that this phase place engulfs control unit and also comprise a counter, in order to export this reference signal.
10. signal generation device as claimed in claim 6 is characterized in that this phase place engulfs control unit and also comprise a buffer, in order to store and to export this phase place amount of engulfing.
11. a signal generating method is characterized in that comprising:
According to one with reference to clock pulse to produce identical but the leggy that phase place is different of a plurality of frequencies with reference to clock pulse;
Foundation one Selecting phasing signal is to select these a plurality of leggies to export clock pulse with reference to clock pulse as one with reference to one in the clock pulse;
After coming the comparison one phase place amount of engulfing and a reference signal by the mode of non-bit order, export this Selecting phasing signal.
12. signal generating method as claimed in claim 11, it is characterized in that this phase place amount of engulfing and this reference signal are all the signal with a plurality of bits, relatively the m bit of this phase place amount of engulfing and the n bit of this reference signal, to export this phase control signal, wherein, m, n is all positive integer, and m is not equal to n.
13. such as claim the 11 described signal generating methods, it is characterized in that the order that non-bit is sequentially put upside down for the height bit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03153401 CN1581699B (en) | 2003-08-12 | 2003-08-12 | Phase swallowing device and signal generating device using same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03153401 CN1581699B (en) | 2003-08-12 | 2003-08-12 | Phase swallowing device and signal generating device using same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1581699A CN1581699A (en) | 2005-02-16 |
| CN1581699B true CN1581699B (en) | 2013-01-30 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 03153401 Expired - Lifetime CN1581699B (en) | 2003-08-12 | 2003-08-12 | Phase swallowing device and signal generating device using same |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4613980A (en) * | 1984-09-04 | 1986-09-23 | Conoco Inc. | System for high accuracy remote decoding |
| US5889436A (en) * | 1996-11-01 | 1999-03-30 | National Semiconductor Corporation | Phase locked loop fractional pulse swallowing frequency synthesizer |
| US6281721B1 (en) * | 2000-02-24 | 2001-08-28 | Lucent Technologies, Inc. | Programmable frequency divider |
| US6424192B1 (en) * | 1998-07-24 | 2002-07-23 | Gct Semiconductor, Inc. | Phase lock loop (PLL) apparatus and method |
-
2003
- 2003-08-12 CN CN 03153401 patent/CN1581699B/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4613980A (en) * | 1984-09-04 | 1986-09-23 | Conoco Inc. | System for high accuracy remote decoding |
| US5889436A (en) * | 1996-11-01 | 1999-03-30 | National Semiconductor Corporation | Phase locked loop fractional pulse swallowing frequency synthesizer |
| US6424192B1 (en) * | 1998-07-24 | 2002-07-23 | Gct Semiconductor, Inc. | Phase lock loop (PLL) apparatus and method |
| US6281721B1 (en) * | 2000-02-24 | 2001-08-28 | Lucent Technologies, Inc. | Programmable frequency divider |
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| CN1581699A (en) | 2005-02-16 |
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