CN1328850C - Nested chopper circuit and method for chopping analog inputting signal to supply samples - Google Patents
Nested chopper circuit and method for chopping analog inputting signal to supply samples Download PDFInfo
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- CN1328850C CN1328850C CNB031379796A CN03137979A CN1328850C CN 1328850 C CN1328850 C CN 1328850C CN B031379796 A CNB031379796 A CN B031379796A CN 03137979 A CN03137979 A CN 03137979A CN 1328850 C CN1328850 C CN 1328850C
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Abstract
The present invention relates to a nested chopping circuit. The chopping circuit comprises a first chopping part and a second chopping part, wherein the first chopping part is coupled with an input end and controlled by a pair of non-overlapping clocks; the output end of the first chopping part is connected with the input end of the second chopping part; the second chopping portion is controlled by a pair of non-overlapping clocks which are mutually and periodically inverted. The nested chopping circuit is coupled with a triangular integration regulator circuit, wherein samples are provided to the input end of the first chopping part after positive input signals and negative input signals are sampled by the periodically inverted clocks. A method capable of cutting off analog input signals for sampling is also provided.
Description
Technical field
The present invention relates to chopper circuit (chopper circuitry), particularly a kind of chopper circuit that can reduce the residual noise (residual noise) that produces because of not matching between the chopping switch input.
Background technology
In the application of analog-digital converter, the accuracy and the feasibility of trigonometric integral adjuster (delta-sigma modulator) make it receive an acclaim on many circuit application, for example audio coding circuit (audio codec circuits), communicating circuit (communication circuits), inductor circuit (sensorcircuits) and apparatus circuit for testing (instrumentation circuits).The task performance of trigonometric integral adjuster (delta-sigma modulator) then with because of switch, operational amplifier and input noise that digital circuit produced relevant.This noise can reduce the dynamic range of input signal.
In low-frequency band, the increase of flicker noise is the direct ratio that is reduced to frequency, then is to dominate noise by offset (offset) in relative low-frequency band, particularly in the confined inductor circuit circuit interface of system works usefulness.In common technology, correlated double sampling (correlated doublesampling), self-correction operational amplifier (self-calibrating operational amplifiers) and chopped wave stabilizing technology (chopper-stabilized techniques) all are used for handling the noise of this class.These skills are classified into auto zero (autozeroing) and copped wave (chopping) two big classes, and can be used for amplifier and integrator.
At Y.H.Chang, the article that T.C.Wu and C.Y.Wu showed " Chopper-stabilizedsigma-delta modulator; " IEEE ISCAS, pp.1286-1289, mention copped wave trigonometric integral adjuster (delta-sigma modulator) among the May 1993 and add that traditional operational amplifier can have better immunity to low-frequency noise, but copped wave has also produced residual noise (residual noise) because of the electric charge between the switch injects not match simultaneously.The conducting of switch (be called not only ON) the and also input of trigonometric integral adjuster (delta-sigma modulator) has been produced pulse by (but also being called OFF).These high-frequency switching signals can enter adjuster along with input signal and reduce the SNDR and the parsing power of system.
Another method then be by A.Bakker, K.Thiele and J.H.Huijsing at " A CMOSnested-chopper instrumentation amplifier with 100-nV offset; " IEEEJ.Solid-State Circuits, vol.35.12, pp.1877-1883, this piece of Dec.2000 article proposes.It mentions a nido chopper amplifier (nested-chopper amplifier) can reduce residual noise (residual noise), if use on trigonometric integral adjuster (delta-sigma modulator) then can eliminate offset (offset) and the relevant low-frequency noise of OP AMP.But the high-frequency noise that is produced that do not match that the adjuster of front end still can be subjected between the sampling switch influences.
Another kind method by C.B.Wang at " A 20bit 25kHz delta-sigma A/D converterutilizing frequency-shaped chopper stabilization scheme; " IEEE customintegrated circuits conference, pp.9-12,2000 this piece articles propose, and frequently organize chopped wave stabilizing trigonometric integral analog-digital converter (frequency-shaped chopper stabilized delta-sigmaA/D converter) and can be used to remove clock pulse noise (clock spike noise).Copped wave clock (chopperclock) is produced to a digital filter by input pseudorandom clock (pseudo-random clock), and this digital filter has two zero at DC and half sampling frequency (half sampling frequency).And clocking noise can't occur at assigned frequency band.
The high-frequency noise of sampling in auto zero (autozeroing) method of input switch can be turned back to assigned frequency band; Similarly, the advantage of wave chopping technology is that just it has than the lower noise of auto zero (autozeroing) method in the application of trigonometric integral adjuster (delta-sigma modulator).
Therefore, in future, we will need a kind of circuit or method that can be reduced in the noise that is produced when the analog digital of carrying out input signal is changed effectively.
Summary of the invention
The present invention proposes to use nido copped wave trigonometric integral adjuster (delta-sigma modulator) as solution for overcoming the above problems, and the residual noise (residual noise) that is produced because of not matching between the chopping switch input can use closed circuit to reduce.And the present invention can be applicable to many aspects, as processing procedure, system or device.
Therefore, the invention provides a kind of nido chopper circuit, it comprises: one first copped wave part, and this part is coupled to input, and is controlled by a pair of first and second non-overlapping clock; And one second copped wave part, be coupled to the above-mentioned first copped wave part, the output of above-mentioned first copped wave part is connected to the input of above-mentioned second copped wave part, and above-mentioned second copped wave part is controlled by a pair of first and second copped wave clock, in order to control S1, S2, S3, the S4 switch, when the above-mentioned first non-overlapping clock and the first copped wave clock conducting, or above-mentioned second when non-overlapping clock and the second copped wave clock conducting, above-mentioned S1 and S4 switch conduction, and when the above-mentioned first non-overlapping clock and the second copped wave clock conducting, or above-mentioned second when non-overlapping clock and the first copped wave clock conducting, above-mentioned S2 and S3 switch conduction; Wherein above-mentioned first and second non-overlapping clock is made up of above-mentioned several copped wave clocks, and above-mentioned first and second non-overlapping clock also is periodically anti-phase mutually.
The present invention also provides a kind of nido chopper circuit, it comprises: one first copped wave part, this part is coupled to input, and wherein first copped wave partly has two external switch and two internal switches of being controlled by the second non-overlapping clock of being controlled by the first non-overlapping clock; And one second copped wave part, being coupled to the above-mentioned first copped wave part, the output of wherein above-mentioned first copped wave part is connected to the input of above-mentioned second copped wave part; The S1 that wherein above-mentioned second copped wave has part ownership and controlled by a pair of copped wave clock, S2, S3, the S4 switch, the above-mentioned first non-overlapping clock and the above-mentioned second non-overlapping clock are made up of above-mentioned several copped wave clocks and are periodically anti-phase, and the phase place of the above-mentioned first non-overlapping clock becomes anti-phase with the phase place of the above-mentioned second non-overlapping clock, when the above-mentioned first non-overlapping clock and the first copped wave clock conducting, or above-mentioned second when non-overlapping clock and the second copped wave clock conducting, above-mentioned S1 and S4 switch conduction, and when the above-mentioned first non-overlapping clock and the second copped wave clock conducting, or above-mentioned second when non-overlapping clock and the first copped wave clock conducting, above-mentioned S2 and S3 switch conduction.
The present invention also provides a kind of method that can chop analog input signal for sampling off, and it comprises: receive an input signal; When input had signal, a pair of periodically mutual first and second anti-phase non-overlapping clock can enter the first copped wave part; Another first and second right copped wave clock can enter the second copped wave part, and in order to control S1, S2, S3, S4 switch, above-mentioned first and second non-overlapping clock then is made up of numerous copped wave clock; Above-mentioned analog input signal can be by first copped wave part and the second copped wave part, its periodic continuously anti-phase characteristic then can be taken a sample on the forward of above-mentioned analog input signal and reversal periods, when the above-mentioned first non-overlapping clock and the first copped wave clock conducting, or above-mentioned second when non-overlapping clock and the second copped wave clock conducting, above-mentioned S1 and S4 switch conduction, and when the above-mentioned first non-overlapping clock and the second copped wave clock conducting, or above-mentioned second when non-overlapping clock and the first copped wave clock conducting, above-mentioned S2 and S3 switch conduction.
The application of several specifics will disclose as follows.
At first we need a nido chopper circuit (nested chopper circuit), have wherein comprised first a copped wave part that is coupled with input and is controlled by the clock of a pair of non-overlapping (non-overlapping).One second copped wave part partly is coupled with first copped wave, and the output of first copped wave part is connected with the input of second copped wave part, and wherein second copped wave part is by a pair of non-overlapping and be the anti-phase clock of periodicity mutually and controlled.This is made up of several copped wave clocks clock.
Nido chopper circuit (nested chopper circuit) and trigonometric integral adjuster (delta-sigmamodulator) which couple, wherein periodically anti-phase clock then align and the sampling of negative input signal after again this sampling is provided to the input of first copped wave part.The clock of a pair of non-overlapping is made up of Ф A and Ф B, and a pair of copped wave clock then is made up of Ф 11 and Ф 12.S1, S2, S3, the S4 switch of this copped wave clock control second copped wave part, and these switches have following row logic: S1﹠amp when operating together with non-overlapping clock; S4: Ф A Ф 11+ Ф B Ф 12; S2﹠amp; S3: Ф A Ф 12+ Ф B Ф 11.
First copped wave partly has two external switch and two internal switches of being controlled by the second non-overlapping clock of being controlled by the first non-overlapping clock, second copped wave part then has 4 switches being controlled by a pair of copped wave clock, and wherein the first non-overlapping clock and the second non-overlapping clock are periodically anti-phase.
The invention provides a kind of can the break simulation input signal for the method for sampling.When input has signal, a pair of be periodically anti-phase non-overlapping clock can enter first copped wave part another anti-phase copped wave clock can enter the second copped wave part to being periodically.Wherein, non-overlapping clock is made up of numerous copped wave clock.Input signal is performed in first copped wave part and second copped wave part, and takes a sample on the forward of input signal and reversal periods.
For the present invention's above-mentioned purpose, feature and advantage can be become apparent, some preferred embodiments cited below particularly, and cooperate appended diagram, be described in detail below:
Description of drawings
Fig. 1 represents the circuit diagram of nido copped wave trigonometric integral adjuster of the present invention (delta-sigma modulator).
A pair of non-overlapping clock is relative with the running of copped wave clock schemes for Fig. 2 (a) expression.
Fig. 2 (b) expression is by the pulse after another copped wave institute demodulation.
Fig. 2 (c) and 2 (d) are illustrated in the switch of running under a pair of non-overlapping clock and the copped wave clock.
Fig. 3 represents the exemplary view of the nido copped wave trigonometric integral adjuster (delta-sigma modulator) of a second differential that thermal noise and operational amplifier arranged.
Fig. 4 represents the exemplary view of the nido copped wave trigonometric integral adjuster (delta-sigma modulator) of the second differential that another has thermal noise and operational amplifier.
Fig. 5 represents that an input signal is-6dB, and 5.78125kHz, sampling frequency are that the dB of the copped wave spike of 2.56MHz and peak 0.5 μ V schemes Hz.
Fig. 6 represents that SNDR is to input amplitude figure.
Embodiment
Nido chopper 100 as shown in Figure 1, it has switch A and the B that is controlled by two non-overlapping clock Ф A that are made up of several chopping cycles and Ф B.And copped wave 100 ' (shown in Fig. 3 and 4) be by clock Ф 11 and Ф 12 control.Nido chopper 100 has comprised first a copped wave part 104 that is coupled with input.104 clock Ф A and Ф B institutes by a pair of non-overlapping of the above-mentioned first copped wave part are controlled, and the second copped wave part 102 is coupled in the first copped wave part 104.The input of the output of the first copped wave part 104 and the second copped wave part 102 joins, and second copped wave part is controlled by copped wave clock Ф 11 and Ф 12.Wherein the clock Ф A of a pair of non-overlapping and Ф are made up of several copped wave clocks and are become periodically anti-phase mutually.
Relevant pulse shown in Fig. 2 A, and by the spike after another copped wave demodulation shown in Fig. 2 B.In common technology, the front end of adjuster can't be directly received in a nido copped wave that has traditional clock because the bifrequency displacement meeting of input signal took place before this signal enters adjuster.Therefore, being based upon nido chopper 100 with chopped wave stabilizing technology is disclosed out and can be used on the trigonometric integral adjuster (delta-sigma modulator).
At first, input signal is by the previous paramount frequency band of copped wave modulation.Then, send a signal to the trigonometric integral adjuster (delta-sigma modulator) of high-frequency noise, and come this signal of demodulation with following chopper circuit.Used as shown in Figure 1 nido copped wave trigonometric integral adjuster (nested chopper delta-sigmamodulator) in order to overcome the residual noise (residual noise) that produces because of previous copped wave at this.The noise spike (noise spike) that produces because of chopping switch is inverted to a kind of tunable cycle, so average residual noise (average residual noise) is reduced or eliminates and makes the SNR of adjuster make moderate progress.
Time diagram shown in Fig. 2 A, forward and reverse signal alternatively input to adjuster.Therefore, as Ф A during at ON, the control signal of s1 and s4 is Ф 11, and the control signal of s2 and s3 is Ф 12.State about switch please refer to Fig. 2 C and Fig. 2 D.
In order to keep the running of chopped wave stabilizing adjuster (chopper-stabilized modulator), the clock of nido chopper is changed according to the present invention.Fig. 1 104 in, as Ф A during at ON, the effect of nido chopper 100 is just identical with a single chopper circuit.Shown in Fig. 2 C, in 102a, s1 and s4 are ON when phase angle is Ф 11; In 102b, s2 and s3 are ON when phase angle is Ф 12.Shown in Fig. 2 D, in 104b, Ф B is ON.In order to keep forward and reverse signal alternatively inputs to adjuster, s2 among the 102b and s3 are ON when phase angle is Ф 11, and s1 among the 102a and s4 are ON when phase angle is Ф 12.Therefore, the control logic of s1, s2, s3, s4 is:
S1&S4：ФA·Ф11+ФB·Ф12
S2&S3：ФA·Ф12+ФB·Ф11
So nido copped wave trigonometric integral adjuster (nested chopper delta-sigma modulator) can reduce residual noise (residual noise) and have lower low-frequency noise.Make those skilled in the art it can be used on the CMOS integrated circuit because of the structure of nido copped wave trigonometric integral adjuster (nested chopper delta-sigma modulator) and operational simplification.
Fig. 3 has shown a calcspar with second differential nido copped wave trigonometric integral adjuster (delta-sigma modulator) of thermal noise (thermal noise) and operational amplifier noise.The thermal noise 110 of icon is the thermal noise and the operational amplifier noise of the non-linear output of first resonator and operational amplifier, and nido chopper 100 is then before first operational amplifier of DSM (delta-sigma modulator).In Fig. 4, nido chopper 100 moves on to the output of operational amplifier, and above-mentioned switch can be reduced to single nmos switch because of the virtual earth input of operational amplifier.Yet, feedback should comprise positive feedback more positive and negative to class copped wave logic.
Fig. 5 represents that an input signal is-6dB, and 5.78125kHz, sampling frequency are that the dB of the copped wave spike of 2.56MHz and peak 0.5 μ V schemes Hz.This figure has three kinds of examples.At first, diagram is the individual chopped wave stabilizing DSM that residual noise (residual noise) arranged of one of common technology topmost.Secondly, be the individual nido copped wave DSM that residual noise (residual noise) is arranged of one of the present invention in the middle of the diagram.At last, the diagram bottom is a perfect chopped wave stabilizing DSM who does not have residual noise (residual noise).As shown in the figure, the residual noise of second example (residual noise) is lower than first example in lower band.Therefore, the present invention can effectively constrain unwanted input composite noise.Fig. 6 is SNDR vs. input amplitude figure, and the spike SNDR of nido copped wave DSM wherein of the present invention is 69.9dB and be 86.3dB at the 8khz frequency range at the 22.05khz frequency range.
The present invention also is applicable to various relevant with computer and need the operation of ingenious use on the amount of material, is stored in computer as data.Usually these quantity can store, changes, synthesize, compare and nido chopper 100 defined connection or interfaces via electronics or electromagnetic signal, and these use cleverly and then usually be defined as manufacturing, authentication, determine and comparison.
Though this creation in preferred embodiment openly as above; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; still can do a little change, so protection scope of the present invention is defined by the accompanying Claim book.
Claims (8)
1. a nido chopper circuit is characterized in that, comprising:
One first copped wave part, this part is coupled to input, and is controlled by a pair of first and second non-overlapping clock; And
One second copped wave part, be coupled to the above-mentioned first copped wave part, the output of above-mentioned first copped wave part is connected to the input of above-mentioned second copped wave part, and above-mentioned second copped wave part is controlled by a pair of first and second copped wave clock, in order to control S1, S2, S3, the S4 switch, when the above-mentioned first non-overlapping clock and the first copped wave clock conducting, or above-mentioned second when non-overlapping clock and the second copped wave clock conducting, above-mentioned S1 and S4 switch conduction, and when the above-mentioned first non-overlapping clock and the second copped wave clock conducting, or above-mentioned second when non-overlapping clock and the first copped wave clock conducting, above-mentioned S2 and S3 switch conduction;
Wherein above-mentioned first and second non-overlapping clock is made up of above-mentioned several copped wave clocks, and above-mentioned first and second non-overlapping clock also is periodically anti-phase mutually.
2. nido chopper circuit as claimed in claim 1 is characterized in that above-mentioned nido chopper circuit is coupled to a trigonometric integral modulator.
3. nido chopper circuit as claimed in claim 1 is characterized in that the anti-phase clock of above-mentioned mutual periodicity then aligns and the sampling of negative input signal provides this sampling to the input of first copped wave part afterwards again.
4. a nido chopper circuit is characterized in that, comprising:
One first copped wave part, this part is coupled to input, and wherein first copped wave partly has two external switch and two internal switches of being controlled by the second non-overlapping clock of being controlled by the first non-overlapping clock;
And one second copped wave part, being coupled to the above-mentioned first copped wave part, the output of wherein above-mentioned first copped wave part is connected to the input of above-mentioned second copped wave part;
The S1 that wherein above-mentioned second copped wave has part ownership and controlled by a pair of copped wave clock, S2, S3, the S4 switch, the above-mentioned first non-overlapping clock and the above-mentioned second non-overlapping clock are made up of above-mentioned several copped wave clocks and are periodically anti-phase, and the phase place of the above-mentioned first non-overlapping clock becomes anti-phase with the phase place of the above-mentioned second non-overlapping clock, when the above-mentioned first non-overlapping clock and the first copped wave clock conducting, or above-mentioned second when non-overlapping clock and the second copped wave clock conducting, above-mentioned S1 and S4 switch conduction, and when the above-mentioned first non-overlapping clock and the second copped wave clock conducting, or above-mentioned second when non-overlapping clock and the first copped wave clock conducting, above-mentioned S2 and S3 switch conduction.
5. nido chopper circuit as claimed in claim 4 is characterized in that above-mentioned nido chopper circuit is coupled to a trigonometric integral modulator.
6. nido chopper circuit as claimed in claim 4, it is characterized in that being mutually anti-phase clock periodically can provide sampling to the input of above-mentioned first copped wave part required just reach negative input signal.
7. the method that can chop analog input signal for sampling off is characterized in that, comprising:
Receive an input signal;
When input had signal, a pair of periodically mutual first and second anti-phase non-overlapping clock can enter the first copped wave part;
Another first and second right copped wave clock can enter the second copped wave part, and in order to control S1, S2, S3, S4 switch, above-mentioned first and second non-overlapping clock then is made up of numerous copped wave clock;
Above-mentioned analog input signal can be by first copped wave part and the second copped wave part, its periodic continuously anti-phase characteristic then can be taken a sample on the forward of above-mentioned analog input signal and reversal periods, when the above-mentioned first non-overlapping clock and the first copped wave clock conducting, or above-mentioned second when non-overlapping clock and the second copped wave clock conducting, above-mentioned S1 and S4 switch conduction, and when the above-mentioned first non-overlapping clock and the second copped wave clock conducting, or above-mentioned second when non-overlapping clock and the first copped wave clock conducting, above-mentioned S2 and S3 switch conduction.
8. a kind of method that can chop analog input signal for sampling off as claimed in claim 7 is characterized in that, also comprises:
The output of above-mentioned second copped wave part is coupled to a trigonometric integral modulator.
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| CNB031379796A CN1328850C (en) | 2003-05-19 | 2003-05-19 | Nested chopper circuit and method for chopping analog inputting signal to supply samples |
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| CNB031379796A CN1328850C (en) | 2003-05-19 | 2003-05-19 | Nested chopper circuit and method for chopping analog inputting signal to supply samples |
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| CN1328850C true CN1328850C (en) | 2007-07-25 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7301384B2 (en) * | 2006-03-31 | 2007-11-27 | Qualcomm Incorporated | Multimode, uniform-latency clock generation circuit |
| TWI492739B (en) * | 2013-06-26 | 2015-07-21 | Shuenn Yuh Lee | A wireless bio-signal acquisition system and a bio-signal |
| CN104682957B (en) * | 2013-11-29 | 2018-10-16 | 展讯通信（上海）有限公司 | Quadrature Sigma-Delta analog-digital converter |
| CN108667439B (en) * | 2017-04-01 | 2021-08-31 | 杭州晶华微电子股份有限公司 | Novel low-power-consumption high-precision low-temperature-drift RC oscillator |
| CN116488657A (en) * | 2023-06-20 | 2023-07-25 | 南方电网数字电网研究院有限公司 | Integrator circuit, sigma-delta modulator and analog-to-digital converter |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5148166A (en) * | 1990-04-06 | 1992-09-15 | General Electric Company | Third order sigma delta oversampled analog-to-digital converter network with low component sensitivity |
| CN1304202A (en) * | 1999-10-15 | 2001-07-18 | 精工爱普生株式会社 | Chopper circuit, method for controlling chopper circuit, chopper type charge circuit, electronic device and timekeeping appliance |
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2003
- 2003-05-19 CN CNB031379796A patent/CN1328850C/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5148166A (en) * | 1990-04-06 | 1992-09-15 | General Electric Company | Third order sigma delta oversampled analog-to-digital converter network with low component sensitivity |
| CN1304202A (en) * | 1999-10-15 | 2001-07-18 | 精工爱普生株式会社 | Chopper circuit, method for controlling chopper circuit, chopper type charge circuit, electronic device and timekeeping appliance |
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