CN1237623C - 在衬底上成形晶体管的方法和含聚亚苯基聚酰亚胺的衬底 - Google Patents
在衬底上成形晶体管的方法和含聚亚苯基聚酰亚胺的衬底 Download PDFInfo
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Abstract
通过在包含聚亚苯基聚酰亚胺的衬底上沉积至少一个半导体材料层来制造晶体管。该衬底允许在用于成形该晶体管的过程中采用超过300℃的加工温度,从而能够制成高质量硅半导体层。该衬底还具有低热膨胀系数,与硅的膨胀系数密切匹配,从而可减少任何硅层龟裂或脱层的倾向。
Description
技术领域
本发明涉及一种制造薄膜晶体管的方法。
薄膜晶体管(TFT)已知在,特别是,控制各种类型显示器方面有用;例如,TFT被普遍用来控制便携式电脑和类似电子装置中使用的液晶显示器。TFT还可用来控制电泳显示器;例如参见WO-A-00/67327;WO-A-01/08241;WO-A-01/170209;WO-A-01/17040;和WO-A-01/17041。在此,所有这些申请的公开内容均收作参考。
虽然大多数TFT迄今一直是在刚性衬底上制造的,然而对在柔性衬底,尤其是在柔性聚合物薄膜上制造TFT的兴趣正与日俱增。在此种柔性衬底上制造的TFT可构成既轻又结实的大显示器的基础,因而使它们得以用在移动装置中。基于无定形硅半导体的TFT由于能以最少的工艺步骤制造并且热量消耗低,故用于此种柔性衬底颇受青睐。无定形硅晶体管是在超薄不锈钢衬底(例如参见Ma等人,《应用物理通讯》74(18),2661(1999))上和在聚酰亚胺薄膜(参见Gleskova等人,《IEEE电子器件通讯》20(9),473(1999))上制造的。
然而,后一篇文章所描述的方法使用的聚酰亚胺,以商品名“Kapton”市售供应,仅具有约300℃的玻璃化转变温度,这就限制了制造过程中能够采用的温度,并因而生产出不甚令人满意的无定形硅半导体层。此种聚酰亚胺还具有高吸湿(约4wt%)的特性,而此种高吸湿又可造成衬底的溶胀以及随之而来在衬底上沉积的薄层的龟裂或薄层从衬底上的剥离。虽然不锈钢衬底能够耐受远高于300℃的温度,但此种衬底要求在其上制造晶体管之前进行钝化和平面化的步骤。要求钝化为的是保证准备在衬底上形成的邻接金属导体之间有恰当的电气绝缘,以及保证不锈钢中潜在杂质不会扩散到晶体管中。不过,不锈钢衬底却又具有高尺寸稳定性和在制造环境中容易操作的优点。
现已发现,某些类型聚酰亚胺具有使其非常适合在TFT制造中作为使用。
因此,本发明提供一种通过在衬底上沉积至少一层半导体材料从而在该衬底上成形至少一个晶体管的方法。在本发明方法中,衬底包含聚亚苯基聚酰亚胺。该方法尤其预期用于成形无定形硅晶体管,而在此种情况下,半导体材料当然是一种无定形硅。
本发明还提供在包含聚亚苯基聚酰亚胺的衬底上成形的晶体管,该衬底载有至少一个晶体管。
唯一的附图是按本发明方法在聚酰亚胺衬底上成形的薄膜晶体管阵列的一个晶体管的剖面示意图。
优选用于本发明方法中的聚亚苯基聚酰亚胺是由UBE(美国)公司(55 East 59th Street,18th Floor,纽约NY 10022,美国)以商品名Upilex-S和Upilex-VT市售供应的那些。这两种材料据制造商称,具有通式:
其中R是亚烷基基团。此种聚酰亚胺是联苯-3,3’,4,4’-四羧酸与α,ω-链烷二胺如1,6-己二胺(正式地称己烷-1,6-二胺)的衍生物。这两种材料之间的主要区别在于,Upilex-S是简单聚酰亚胺薄膜,而Upilex-VT是一侧表面经过了处理,以促使薄膜不用粘合剂,仅靠热就能层合到陶瓷或金属箔上。为达到本发明的目的,Upilex VT可层合到不锈钢背衬薄膜上。另一种优选用于本发明方法中的聚酰亚胺是Upilex-50SS,得自同一制造商。
聚亚苯基聚酰亚胺具有比此前用作晶体管衬底的其他聚酰亚胺高得多的玻璃化转变温度和低得多的吸水性。上面已经提到的市售Upilex材料具有超过400℃的玻璃化转变温度和不超过约1.4%的吸水性。这样高的玻璃化转变温度允许在制造过程中采用比此前作为晶体管衬底使用的聚酰亚胺迄今可能达到的温度更高的温度(大于约300℃,优选大于约400℃),而此种更高的加工温度将生产出具有较高可移动性和较低超限漏电流的较高品质硅层。聚亚苯基聚酰亚胺在加工期间还具有高尺寸稳定性和表面光滑的优点,这对于薄膜晶体管成形中使用的薄层材料的沉积至关重要;例如,上面提到的Upilex-50SS具有约0.01%的尺寸稳定性和约20~30nm的平均表面粗糙度。聚亚苯基聚酰亚胺的另一个优点是它们的低热膨胀系数,典型值为约2~10×10-6℃-1,相比之下此前使用的聚酰亚胺的典型值为35×10-6℃-1。鉴于硅的热膨胀系数为约3×10-6℃-1,聚亚苯基聚酰亚胺衬底的系数与沉积在其上的硅层匹配密切得多,因此硅层龟裂和/或脱层的倾向低得多。
聚亚苯基聚酰亚胺衬底的上述性能使得本发明方法能很好地适应卷材到卷材的加工,其中半导体材料的沉积是在聚酰亚胺衬底的连续片材上进行的。
上面已经提到,本发明方法中使用的聚亚苯基聚酰亚胺在其准备沉积半导体材料的相反一面可以具有,也可以不具有金属背衬层。此种金属背衬层对提高晶体管制造过程中薄膜的机械整体性有用,从而避免,例如,操作期间聚酰亚胺薄膜拉长或畸变的任何倾向,减少在衬底上成形晶体管期间衬底的畸变。另外,金属背衬层还可起到挡光的作用,以减少任何由聚酰亚胺薄膜背面入射的光在半导体材料中造成的不希望的光效应(例如,在无定形硅膜中的光生电流)。金属背衬层不必是连续的;该层可具有贯通层的孔,以降低挺度并从而赋予带金属背衬的衬底以更高的柔性。倘若设有此种孔,出于显而易见的原因较好的是,它们可成形为一种规则图形,相应地,某些或全部孔可用于衬底与制造过程所用设备之间的机械套准。的确,在某些情况下,图形金属背衬层可作为荫罩用于在衬底上成形晶体管期间的光刻胶曝光图案成形步骤中。替代或附加地,可能有利的是,在聚酰亚胺本身中加入染料以阻止或消除此种不希望的光效应。
如同在某些现有技术方法中那样,可能较好的是,在向此种衬底上沉积晶体管之前先在衬底上沉积一种二氧化硅、氮化铝、氮化硅或其他材料的钝化层。就典型而言,此种钝化层的厚度可介于约20~约100nm。钝化不仅对提高聚酰亚胺表面的表面电阻,从而增加连接导体之间的电气绝缘有用,而且通过防止衬底在加工期间吸水还能提高衬底的尺寸稳定性,而为达到后一目的,较好的是,在衬底两个表面都设置钝化层。较好的还有,对衬底进行热处理(“烘烤”)以便在钝化层沉积之前从衬底中除掉水分;此种烘烤通常在至少约150℃的温度持续至少约1分钟的时间,优选约3分钟。
可能有利的还有,对钝化的衬底实施后烘烤。按照Philips研究实验室题为“聚合物衬底上的AMLCD和电子学”(《欧洲显示器)1996)的文章,在275℃加热10小时后自由放置的聚酰亚胺薄膜的收缩率可降低2个数量级,而在同样温度下100小时后降低2.4个数量级。在该文章中描述的一个具体实验中,275℃下烘烤100小时后,聚酰亚胺薄膜(未指出品牌)收缩了3ppm h-1。据此,若要求对钝化衬底实施此种后烘烤,它应在至少250℃的温度持续至少5小时的时间。尚未在实验中确定上述结果是否适用于张紧卷材形式中的衬底,也未在实验中确定降低收缩是否在预烘烤的衬底在经过冷却、退绕、为在其上成形晶体管所需要的加工、张力下再成卷以及随后预热几天之后,也如同在卷材到卷材加工中在衬底上成形晶体管那样必要。替代地,衬底可在临实施成形晶体管所要求的层沉积之前在传送带烘炉中进行预烘烤。
然而,聚亚苯基聚酰亚胺的表面电阻却是如此之高(典型值大于1016Ω),以致在许多情况下,有可能在相邻导体之间不需要此种钝化层便能获得足够的电气绝缘。若省略钝化层,在衬底上沉积半导体层之前烘烤衬底以赶出水分和任何其他吸收在聚酰亚胺上的挥发性材料,仍然是有利的,因为这样可降低聚酰亚胺因吸水造成的溶胀并可提高在聚酰亚胺上成形晶体管期间聚酰亚胺的尺寸稳定性。此种烘烤较好在大于250℃的温度持续至少1小时的时间。在下面描述的一种优选实施方案中,衬底加热到接近其玻璃化转变温度的350℃,并持续4小时。
下面描述的本发明目前优选实施方案采用倒相晶体管设计,其中门(或栅)电极紧靠衬底布置。为成形此种倒相晶体管,第一步(按所描述的方式完成对衬底的任何可能钝化和/或预烘烤之后)是在衬底上沉积金属层。为此目的,优选的金属是铬。在沉积半导体材料以便形成要成形的晶体管阵列的门电极和选通线之前,通常优选将铬或其他金属沉积为连续膜,典型厚度介于50~200nm,然后使金属膜图形化,典型方法采用传统光刻技术。方法的下一个步骤通常是介电材料的沉积,例如氮化硅;此种沉积可通过等离子增强的化学气相沉积而方便地完成。随后成形半导体材料,优选无定形硅,依然方便地采用等离子增强的化学气相沉积。如同在上面提到的WO-A-00/67327中所讨论的,在一种适当设计中,无定形硅层(以及相联系的介电层)可保持为非图形的,因此该无定形硅层连续延伸在一对相邻晶体管之间。接着,在该无定形硅上沉积n-型硅层,同样,方便地采用等离子增强的化学气相沉积。最后,通常在清洗步骤以除掉化学气相沉积过程留下的残余物之后,在n-型硅层上沉积金属层,例如,铝层,该金属层仍可方便地采用热蒸发来沉积。随后,该金属层通过传统光刻技术转化为图形,以便形成源和漏电极,然后该图形化的金属层被用作n-型硅层的反应离子腐蚀用的腐蚀掩模;用四氟化碳/氧气混合物进行腐蚀,据发现令人满意。
下面将结合附图详细描述本发明优选的实施方案,然而仅作为举例说明而已,图中显示按本发明方法在聚亚苯基聚酰亚胺衬底上成形的一个晶体管的断面示意图。
该附图显示在聚亚苯基聚酰亚胺衬底12上成形的晶体管阵列(总称为10)的一个晶体管。图中画出的衬底12备有不锈钢金属背衬层14,沿整个背衬按规则间隔分布着通孔16,在图中仅画出一个。如同上面已经提到的,金属背衬层14的存在在本发明方法中是任选的,尽管此种金属背衬层的确给衬底提供额外的机械整体性,并因此便于衬底的操作,尤其当本发明在卷材到卷材的涂布设备上实施时。
在衬底12的上表面上(如图所示),沉积着由二氧化硅或氮化硅形成的钝化层18。如上所述,此种钝化层18的存在是任选的,而在某些情况下,钝化层18可以省略,因为聚亚苯基聚酰亚胺的高表面电阻在相邻晶体管之间已提供足够绝缘。然而,在省掉钝化层18时须小心,因为倘若不存在这一层,则从聚酰亚胺衬底12排出的气体往往会导致各种各样层与该衬底的脱层。
在钝化层18的上表面,沉积着按一定间隔排列的金属门电极的阵列20(图中仅看到一个门电极),而在电极20的上面顺序地沉积着由氮化硅形成的介电层22和无定形硅的层24。如上面提到的WO-A-00/67327所讨论的,介电层22和无定形硅层24可保持为非图形的,因此不必使这些层图形化,从而大大降低了晶体管阵列的制造成本。最后,该晶体管阵列包含n-型硅的层26和金属电极层28;这两个层采用任何传统方法转化为图形以提供晶体管的源和漏电极。
本发明第二优选实施方案大体类似于上面所描述的方案,只是使用了不带金属背衬或钝化层的聚酰亚胺衬底。在该第二优选实施方案中,上述Upilex-50SS首先在350℃烘烤4小时以去掉水分和任何其他存在的溶剂。一个100nm厚的铬层通过热蒸发沉积在烘烤的衬底上,然后光刻成图形,从而形成最终晶体管阵列的门电极和选通线。接着,通过等离子增强的化学气相沉积(PECVD)使用硅烷/氨混合物在衬底上沉积320nm氮化硅介电层;在此沉积期间,衬底达到其最高加工温度350℃。然后,通过PECVD由纯硅烷沉积160nm无定形硅半导体材料层,随后通过PECVD由硅烷/膦混合物沉积40nm n-型无定形硅层。
在这些PECVD步骤后,在衬底上沉积铝层,并通过光刻成形为图形,于是形成晶体管阵列的源和漏电极。随后,衬底利用四氟化碳/氧气混合物接受反应性离子腐蚀,以图形状铝层作为腐蚀掩模使n-型硅层图形化。最后,采用低分辨率成图步骤使无定形硅和氮化硅层图形化,从而制成与选通粘合线部位的电气接触。
如此制造的薄膜晶体管可直接用于制造电泳显示器或其他类型显示器,而不需要进一步加工。例如,附图所述薄膜晶体管阵列可通过WO-A-00/36465所描述的方法结合到电泳显示器中;在此将该共同未决申请的整个公开内容收作参考。在某些情况下,较好的是提供一种覆盖薄膜晶体管的阻挡层以保护晶体管免遭溶剂或往往会从电泳显示器中扩散出来的其他材料的侵害。
按本发明方法生产的薄膜晶体管阵列尤其准备用于电泳显示器中,特别是封装电泳显示器,如以下文献中描述的那些:美国专利5,930,026;5,961,804;6,017,584;6,067,185;6,118,426;6,120,588;6,120,839;6,124,851;6,130,773;6,130,774;和6,172,798,以及国际申请公开WO 97/04398;WO 98/03896;WO98/19208;WO 98/41898;WO 98/41899;WO 99/10769;WO 99/10768;WO99/10767;WO 99/53373;WO 99/56171;WO 99/59101;WO 99/47970;WO00/03349;WO 00/03291;WO 99/67678;WO 00/05704;WO 99/53371;WO00/20921;WO 00/20922;WO 00/20923;WO 00/26761;WO 00/36465;WO00/38000;WO 00/38001;WO 00/36560;WO 00/20922;WO 00/36666;WO00/59625;WO 00/67110;WO 00/67327和WO 01/02899.在此,所有这些专利和公开的申请的全部公开内容一并收作参考。
在不偏离本发明精神和技术的前提下,从已给出的本发明方法的优选实施方案中可制定出许许多多修改和变化。例如,本发明不限于如附图所示的下门电极晶体管的制造,该方法也可用于上门电极晶体管的制造,其中首先在衬底上制造源和漏电极(带或不带钝化层),然后在电极上面成形无定形硅层和介电层,最后成形门电极作为结构的顶层。可见,上面的描述应视为说明性的,而不是限制性的。
综上所述,可以看出,本发明方法提供一种在柔性衬底上成形晶体管的方法,它允许使用比现有技术方法高的加工温度,因此它能生产出比现有技术方法质量高的半导体层。本发明方法中使用的衬底的热膨胀系数与大多数半导体层的热膨胀系数最接近匹配,因此可减少因该层与衬底之间热膨胀差异造成半导体层龟裂和/或脱层的危险。本发明提供一种能很好地适应卷材到卷材操作的方法,因此本发明方法非常适合在柔性衬底上制造大面积晶体管阵列。
Claims (15)
1.一种在衬底(12)上成形至少一个晶体管(10)的方法,该方法包括在衬底(12)上沉积至少一层半导体材料(24,26),其特征在于,衬底(12)包含聚亚苯基聚酰亚胺,该聚亚苯基聚酰亚胺是联苯-3,3’,4,4’-四羧酸的衍生物。
2.按照权利要求1的方法,其特征在于,该聚酰亚胺是联苯-3,3’,4,4’-四羧酸与α,ω-链烷二胺的衍生物。
3.按照权利要求1中的方法,其特征在于,在半导体材料(24,26)沉积到衬底(12)上之前,在衬底(12)的一个或两个表面沉积钝化层(18)。
4.按照权利要求3的方法,其特征在于,钝化层(18)包含二氧化硅或氮化铝,和/或厚度介于20~100nm。
5.按照权利要求3的方法,其特征在于,衬底(12)在沉积钝化层(18)之前在高于150℃的温度加热至少1分钟的时间.
6.按照权利要求3的方法,其特征在于,衬底(12)在沉积了钝化层(18)之后在高于250℃的温度加热至少5小时的时间。
7.按照权利要求1的方法,其特征在于,衬底(12)在沉积半导体材料(24,26)之前在高于250℃的温度加热至少1小时的时间。
8.按照权利要求1的方法,其特征在于,衬底(12)包含位于其远离半导体材料(24,26)的一面上的金属层(14)。
9.按照权利要求8的方法,其特征在于,金属层(14)具有通孔(16)。
10.按照权利要求1的方法,其特征在于,半导体材料(24)的沉积是在超过300℃的温度进行的。
11.按照权利要求1的方法,其特征在于,半导体材料(24)包含无定形硅。
12.按照权利要求11的方法,其特征在于,无定形硅未制成图形,因此它连续地延伸在至少某些相邻晶体管对之间。
13.按照权利要求1的方法,其特征在于,半导体材料(24,26)的沉积是在衬底(12)的连续片材上进行的。
14.一种包含聚亚苯基聚酰亚胺的衬底(12),该衬底载有至少一个晶体管(10),该聚亚苯基聚酰亚胺是联苯-3,3’,4,4’-四羧酸的衍生物。
15.权利要求14的衬底,其特征在于具有权利要求1~13中任一项规定的任何一个或多个特征。
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-
2001
- 2001-04-17 AU AU2001253575A patent/AU2001253575A1/en not_active Abandoned
- 2001-04-17 EP EP01927094A patent/EP1275156B1/en not_active Expired - Lifetime
- 2001-04-17 WO PCT/US2001/012429 patent/WO2001080287A2/en active Application Filing
- 2001-04-17 US US09/836,884 patent/US6825068B2/en not_active Expired - Lifetime
- 2001-04-17 AT AT01927094T patent/ATE438927T1/de not_active IP Right Cessation
- 2001-04-17 JP JP2001577586A patent/JP2003531487A/ja not_active Ceased
- 2001-04-17 CN CNB018081681A patent/CN1237623C/zh not_active Expired - Fee Related
- 2001-04-17 DE DE60139463T patent/DE60139463D1/de not_active Expired - Lifetime
- 2001-04-17 KR KR1020027013880A patent/KR100767233B1/ko active IP Right Grant
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2004
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Publication number | Publication date |
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WO2001080287A3 (en) | 2002-05-23 |
KR100767233B1 (ko) | 2007-10-17 |
EP1275156B1 (en) | 2009-08-05 |
AU2001253575A1 (en) | 2001-10-30 |
WO2001080287A2 (en) | 2001-10-25 |
EP1275156A2 (en) | 2003-01-15 |
US20050067656A1 (en) | 2005-03-31 |
CN1441967A (zh) | 2003-09-10 |
DE60139463D1 (de) | 2009-09-17 |
US7365394B2 (en) | 2008-04-29 |
US20020019081A1 (en) | 2002-02-14 |
ATE438927T1 (de) | 2009-08-15 |
KR20020089479A (ko) | 2002-11-29 |
JP2003531487A (ja) | 2003-10-21 |
US6825068B2 (en) | 2004-11-30 |
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