CN1180464C - 用于输入/输出的球限定冶金结构及其制造方法 - Google Patents

用于输入/输出的球限定冶金结构及其制造方法 Download PDF

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CN1180464C
CN1180464C CNB018119883A CN01811988A CN1180464C CN 1180464 C CN1180464 C CN 1180464C CN B018119883 A CNB018119883 A CN B018119883A CN 01811988 A CN01811988 A CN 01811988A CN 1180464 C CN1180464 C CN 1180464C
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mtallurgy
ball limiting
film
pad
nickel
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CN1446375A (zh
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K������ɳ��
K·塞沙
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Intel Corp
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/12All metal or with adjacent metals
    • Y10T428/12493Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
    • Y10T428/12535Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.] with additional, spatially distinct nonmetal component
    • Y10T428/12556Organic component

Abstract

本发明涉及用于器件的输入/输出及其制造方法。本发明的输入/输出包括其上形成有球限定冶金结构的焊盘,和球限定冶金结构上形成的凸起。本发明的一个实施例中,球限定冶金结构包括含有镍-钒-氮的第一膜。本发明的第二实施例中,球限定冶金结构包括含有镍-铌合金的第一膜。

Description

用于输入/输出的球限定冶金结构及其制造方法
发明背景
1.技术领域
本发明涉及半导体集成电路(IC),具体涉及用于器件的输入/输出(I/O)的凸起限定冶金结构。
2.背景技术
器件中的输入/输出用于限定和分配电功率,接地和输入/输出信号。输入/输出用金(Au)或铜(Cu)丝构成的引线焊到外壳或电路板。但是,当输入/输出的数量达到400至1000个时,凸起焊(bumping)往往比丝焊更有利。
图1(a)和图1(b)显示出直径为1和节距为2的焊料凸起15。焊料凸起15形成在球限定冶金结构(BLM)14上。球限定冶金结构(balllimiting metallurgy,BLM)也是已知的焊盘限定冶金结构(padlimiting metallurgy,即PLM)或凸起下冶金结构(under bumpmetallurgy,UBM)。球限定冶金结构14经钝化层13中的通路12连接到下层焊盘11b。钝化层13包括一或多个材料层,例如,氧化硅、氮化硅或聚酰亚胺构成的膜层,它们用作阻挡湿气,离子或污物的阻挡层。焊盘11b是器件的金属顶层中的金属线11a的焊接部分。金属线11a通过通路10连接到下层,即,再连接到下层线9。器件通常有2到8层金属层,所以,通路和金属线垂直交替直到电接点形成为IC或衬底下的所需部分为止。
凸起焊明显改善了芯区的进入并使硅区的利用率达到最大。图1(a)和图1(b)显示出芯片整个有效面积上的凸起15的区域阵列3。阵列3基本上是周期性的,而且可以是面心立方体或六面体,以使凸起15有较高的密度。凸起焊后的器件翻转封装成倒装芯片(FC)。以受控的扁平芯片连接(C4)为基础的焊料凸起技术可用于芯片直插(DCA)到外壳或电路板上的导电线。电路板可以是陶瓷衬底,印刷电路板(PWB),软电路,或硅衬底。器件的凸起焊还可以降低输入/输出中的电阻值和电感量,因此,能明显提高性能。
高性能器件,例如,微处理器,特殊用途的集成电路(ASIC),可编程场栅阵列(FPGA)或芯片上的系统(SOC)可以有600到7000个I/O,因此需要减小规模以限制管芯尺寸。进行丝焊用直径小于25微米的焊丝,焊球直径小于40微米,节距应小于60微米。凸起焊涉及的凸起直径为45到90微米,节距为125到300微米。
引线或凸起的规模下降时,功率控制和热控制是关键。如果每个I/O的接点温度超过100到125℃,或电流密度超过150到425mA,则I/O会损坏。在造成最后开路之前电迁移和热迁移造成电阻值增大2个数量级以上。温度升高还会引起金属间扩散。生成的金属间合金易碎,还会造成应力破坏。热膨胀温度系数(CTE)不匹配会在引线或凸起上引起大的剪切应力。例如焊料的热膨胀温度系数(CTE)是30ppm/℃,可与陶瓷衬底的热膨胀温度系数(CTE)7ppm/℃和硅衬底的热膨胀温度系数(CTE)5ppm/℃相比。如果,温度升高速度超过15到20℃/分,引线或凸起会因为热冲击而损坏。由于弹性变形和蠕动变形造成疲劳,按低的温度升高速度进行热循环也会引起引线或凸起破裂。
由于高温和大电流导致的I/O,特别是功率I/O故障是关注重点。
附图说明
图1a是现有的凸起平面图;
图1b是现有的凸起的剖视图;
图2a是半导体器件的局部剖视图;
图2b是图2a所示半导体器件中的焊盘上形成开口的剖视图;
图2c是图2b所示半导体器上形成球限定冶金结构(BLM)的剖视图;
图2d是图2c所示半导体器件上形成凸起的剖视图;
图2e是从是图2d所示半导体器件上除去BLM层的露出部分的剖视图;
图2f是显示图2e所示半导体器件上的凸起的回流的剖视图;
具体实施方式
本发明涉及器件的输入/输出(I/O)用的球限定冶金结构(BLM)及其制造方法。以下的描述中陈述了诸如具体材料,尺寸,和工艺等许多具体细节,以便充分理解本发明。但是本领域技术人员应了解,除了这些细节也能实施发明。其他实施例中,不再详细描述公知的半导体设备和工艺,以避免使本发明不必要地不清楚。
本发明涉及诸如半导体器件等器件用的输入/输出(I/O)用的球限定冶金结构(BLM)。按本发明的实施例的输入/输出(I/O)装置包括其上形成有球限定冶金结构(BLM)的焊盘,和在球限定冶金结构(BLM)上的凸起。按本发明的第一实施例,球限定冶金结构(BLM)包括含镍-钒-氮的第一合金膜。按本发明的第二实施例,球限定冶金结构(BLM)包括镍-铌合金膜。用氮饱和的钒-钛膜,或者,用镍-铌膜形成球限定冶金结构(BLM),可以提高输入/输出(I/O)的寿命。
按本发明的输入/输出(I/O)用到诸如微处理器,存储器,特殊用途的集成电路(ASIC),可编程的场栅阵列(FPGA)和那些需要例如600-7000个大量输入/输出(I/O)的地方,输入/输出(I/O)电信号是很理想的。
图2a显示出典型的半导体器件或集成电路200的一部分的一个实例。器件200包括半导体衬底,例如,其上形成有多个晶体管和电容器的有源构件204的硅衬底202。这些有源构件204通过用层间介质层(ILD)207使其相互隔离的多级互连线206连接在一起,形成功能电路。电接点或通路208经层间介质层(ILD)207电连接不同级的互连线。通常用诸如铝,掺铜的铝和铜等低电阻金属构成金属互连线。接点和通路208通常用钨构成,但是,也可以用例如铜的其他材料构成。
最上层的金属化层包括互连线206和焊盘212。焊盘或连接区212是最上层金属化层的焊接部分,外部器件上的电接点连接到该焊接部分,使外部器件连接到半导体器件200。
最上层的金属化层是被用于阻挡湿气,离子和/或污物的阻挡层的钝化层214覆盖的层。通常的钝化层214包括提供器件200的密封的下层氮化硅密封层216和提供划伤保护的聚酰亚胺上层218。
按本发明的输入/输出(I/O)制造方法中,如图2b所示,形成穿过钝化层214的开口220,以露出部分焊盘212。用光刻胶层和公知的光刻腐蚀方法形成开口220。或者,用可以光限定的聚酰亚胺膜218在钝化层214中形成开口220。
之后,如图2c所示,在钝化层214上,开口220中和焊盘212上覆盖淀积球限定冶金结构(BLM)。本发明的实施例中,球限定冶金结构(BLM)222层包括给焊盘212和钝化层214提供良好粘接力的下粘接层224。下粘接层224可以用厚度为200-1500(埃)的钛(Ti)膜构成。可以用作粘接层224的金属包括钛化钨(TiW),钽(Ta)或铬(Cr),但是,不限于这些金属。任何公知的方法,例如,溅射法可以用来淀积粘接层224。
按本发明,球限定冶金结构(BLM)222层包括可被焊料浸润的上层226。按本发明第一实施例,上层226是镍,钒和氮构成的膜层。氮加入膜中,用氮锁定钒,使其不与氧反应和损害球限定冶金结构(BLM)222层的稳定性。上层226包含适量的氮,以充分防止上层226中的钒氧化。按本发明的实施例中,上层膜中包含相同量的氮和钒。上层膜中包含8原子百分数的氮,8原子百分数的钒和任意量的镍。上层镍-钒-氮合金膜226的厚度范围可以在1000到4000。
用镍-钒靶在含氮的环境中反应溅射形成合适的镍-钒-氮合金膜226。本发明的实施例中,在例如,Material Research Corporation(MRC)制造的磁控溅射室内,同时,给溅射室输入氮气(N2),从镍-钒靶用氩气的磁控溅射形成镍-钒-氮合金膜226。溅射过程中溅射室内没有氧存在。按足以使淀积的膜226用氮饱和的速度给溅射室输入氮气(N2)。本发明的实施例中,给溅射室按15-30sccms的速度输入氮气(N2)。通过氮化镍-钒-合金膜,用氮气(N2)锁定钒,以防止它扩散到表面和防止它氧化,以免造成球限定冶金结构(BLM)222层的电组值增大,使其具有可靠性。
本发明第二实施例中,球限定冶金结构(BLM)222的上层226是镍-铌(Ni-Nb)合金膜。本发明实施例中,上层226是镍-铌(Ni-Nb)合金膜,有10原子百分数的铌(Nb)和剩余量的镍(Ni)。镍-铌(Ni-Nb)合金膜的厚度为1000-4000。用任何公知的方法,例如用溅射法从镍-铌(Ni-Nb)靶溅射,可以形成合适的镍-铌(Ni-Nb)合金膜。镍-铌(Ni-Nb)上层合金膜226有良好的可靠性。
球限定冶金结构(BLM)222是金属扩散阻挡层。根据为凸起和BLM选择的冶金方法类型,可以在粘接层224与上层226之间插入附加层。所用的中间层必须对粘接层224和上层226有良好的粘接性。
之后,在焊盘212上的球限定冶金结构(BLM)222形成凸起228。如图2d所示,通过形成有开口的光刻胶掩膜230,以曝光焊盘212上的球限定冶金结构(BLM)222,由此可以在球限定冶金结构(BLM)222上形成凸起228。如图2d所示,之后,焊料电镀到球限定冶金结构(BLM)222上。如图2d所示,焊料形成蘑菇形。焊料可以是铅-锡(Pb-Sn)焊料,或铅-铟(Pb-In)焊料。锡防止氧化,并增强球限定冶金结构(BLM)222。在上层226中用镍使球限定冶金结构(BLM)222能够镀铅。
之后,除去光刻胶掩膜230,经腐蚀除去没被焊料球228覆盖的球限定冶金结构(BLM)222的多余部分,如图2e所示。
之后在烘箱或炉子内加热衬底,使焊料回流进焊料凸起228中,如图2f所示。凸起228中的焊料熔点与根据它的相对浓度选择的材料类型相关。诸如按95Pb/5Sn重量比的高铅焊料的回流温度是300-360℃。而按诸如37Pb/63Sn重量比的低熔点焊料的回流温度是180-240℃。已回流的凸起228连接到外壳或电路板上的对应凸起。用锡(Sn)或诸如160℃的低熔点焊料构成外壳或电路板上的凸起,使在芯片的连接工艺中芯片上的凸起不会回流。
按本发明的输入/输出及其制造方法,可以在器件200的上表面上制造大量的输入/输出,例如600-7000个I/O。按本发明的输入/输出,每个凸起能承受的电流密度为200-300Ma,能耐受110-120℃的工作温度而不会对可靠性造成不利的影响。本发明的输入/输出可以制造需要大量I/O的半导体器件。

Claims (24)

1.一种用于器件的输入/输出的球限定冶金结构,包括:
焊盘;
所述焊盘上的球限定冶金结构,其具有包括镍-钒-氮的第一合金膜;和
位于所述球限定冶金结构上的凸起。
2.如权利要求1所述的球限定冶金结构,其中,所述的第一合金膜包含相同百分数的氮和钒,该百分数以原子计算。
3.如权利要求1所述的球限定冶金结构,其中,所述的第一合金膜包括防止钒氧化的足够量的氮。
4.如权利要求1所述的球限定冶金结构,其中,所述的第一合金膜含有约8%的氮,该百分数以原子计算。
5.如权利要求1所述的球限定冶金结构,其中,所述的第一合金膜的厚度在1000-4000之间。
6.如权利要求1所述的球限定冶金结构,其中,所述球限定冶金结构还包括第二膜,所述第二膜包含钛并且形成在所述第一膜与所述焊盘之间。
7.如权利要求1所述的球限定冶金结构,其中,所述凸起是焊料凸起。
8.如权利要求7所述的球限定冶金结构,其中,所述焊料凸起是铅-锡。
9.一种用于器件的输入/输出的球限定冶金结构,包括:
焊盘;
位于所述焊盘上的球限定冶金结构,其具有包括镍-铌合金的第一膜;和
位于所述球限定冶金结构的镍-铌合金膜上的凸起。
10.如权利要求9所述的球限定冶金结构,其中,所述镍-铌合金含约10%铌,该百分数以原子计算。
11.如权利要求9所述的球限定冶金结构,其中,所述第一膜的厚度在1000-4000之间。
12.如权利要求9所述的球限定冶金结构,还包括含钛的第二膜,其中所述第二膜形成在所述第一膜与所述焊盘之间。
13.如权利要求9所述的球限定冶金结构,其中,所述凸起是焊料凸起。
14.如权利要求13所述的球限定冶金结构,其中,所述焊料凸起是铅-锡焊料凸起。
15.一种形成用于器件上的输入/输出的球限定冶金结构的方法,包括:
在焊盘上的钝化层中形成开口;
所述开口中的所述焊盘上和所述钝化层上形成球限定冶金结构,其中所述球限定冶金结构包括含有镍-钒-氮的第一合金膜;和
在所述球限定冶金结构上形成凸起。
16.如权利要求15所述的方法,其中,通过磁控管溅射利用镍-钒靶在氮气环境中形成第一合金膜。
17.如权利要求16所述的方法,其中,在磁控管溅射室内形成第一合金膜,并且在由所述镍-钒靶溅射时将15-30sccm的氮气输入所述磁控管溅射室中。
18.如权利要求15所述的方法,其中,所述第一合金膜包含约8%的氮,该百分数以原子计算。
19.如权利要求15所述的方法,其中,所述第一合金膜包含相同百分数的氮和钒,该百分数以原子计算。
20.一种形成用于器件的输入/输出的球限定冶金结构的方法,包括:
在焊盘上的钝化层中形成开口;
在所述开口中的所述焊盘上和所述钝化层上形成球限定冶金结构,其中所述球限定冶金结构包括含有镍-铌合金的第一合金膜;和
在所述球限定冶金结构的镍-铌合金上形成凸起。
21.如权利要求20所述的方法,其中,所述第一合金膜包含约10%的铌,该百分数以原子计算。
22.如权利要求20所述的方法,其中,其中所述第一合金膜的厚度在1000-4000之间。
23.如权利要求20所述的方法,还包括在所述球限定冶金结构中形成第二膜的步骤,其中所述第二膜包含钛,并且在形成所述第一膜之前将所述第二膜形成在所述焊盘和所述钝化层上。
24.如权利要求15所述的方法,还包括在所述球限定冶金结构中形成第二膜的步骤,其中所述第二膜包含钛,并且在形成所述第一膜之前将所述第二膜形成在所述焊盘和所述钝化层上。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107863332A (zh) * 2016-09-21 2018-03-30 英飞凌科技股份有限公司 电子器件、电子模块及其制造方法

Families Citing this family (74)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6642136B1 (en) 2001-09-17 2003-11-04 Megic Corporation Method of making a low fabrication cost, high performance, high reliability chip scale package
US6693033B2 (en) * 2000-02-10 2004-02-17 Motorola, Inc. Method of removing an amorphous oxide from a monocrystalline surface
US7271489B2 (en) * 2003-10-15 2007-09-18 Megica Corporation Post passivation interconnection schemes on top of the IC chips
AU2002228926A1 (en) * 2000-11-10 2002-05-21 Unitive Electronics, Inc. Methods of positioning components using liquid prime movers and related structures
US20020096683A1 (en) * 2001-01-19 2002-07-25 Motorola, Inc. Structure and method for fabricating GaN devices utilizing the formation of a compliant substrate
US6709989B2 (en) 2001-06-21 2004-03-23 Motorola, Inc. Method for fabricating a semiconductor structure including a metal oxide interface with silicon
US6693298B2 (en) 2001-07-20 2004-02-17 Motorola, Inc. Structure and method for fabricating epitaxial semiconductor on insulator (SOI) structures and devices utilizing the formation of a compliant substrate for materials used to form same
US7019332B2 (en) * 2001-07-20 2006-03-28 Freescale Semiconductor, Inc. Fabrication of a wavelength locker within a semiconductor structure
US6639249B2 (en) * 2001-08-06 2003-10-28 Motorola, Inc. Structure and method for fabrication for a solid-state lighting device
US6673667B2 (en) * 2001-08-15 2004-01-06 Motorola, Inc. Method for manufacturing a substantially integral monolithic apparatus including a plurality of semiconductor materials
US7099293B2 (en) 2002-05-01 2006-08-29 Stmicroelectronics, Inc. Buffer-less de-skewing for symbol combination in a CDMA demodulator
US6762122B2 (en) * 2001-09-27 2004-07-13 Unitivie International Limited Methods of forming metallurgy structures for wire and solder bonding
US6577002B1 (en) * 2001-11-29 2003-06-10 Sun Microsystems, Inc. 180 degree bump placement layout for an integrated circuit power grid
TW503496B (en) 2001-12-31 2002-09-21 Megic Corp Chip packaging structure and manufacturing process of the same
TW544882B (en) * 2001-12-31 2003-08-01 Megic Corp Chip package structure and process thereof
US6673698B1 (en) 2002-01-19 2004-01-06 Megic Corporation Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers
TW584950B (en) 2001-12-31 2004-04-21 Megic Corp Chip packaging structure and process thereof
US6715663B2 (en) * 2002-01-16 2004-04-06 Intel Corporation Wire-bond process flow for copper metal-six, structures achieved thereby, and testing method
US6622907B2 (en) * 2002-02-19 2003-09-23 International Business Machines Corporation Sacrificial seed layer process for forming C4 solder bumps
US7547623B2 (en) * 2002-06-25 2009-06-16 Unitive International Limited Methods of forming lead free solder bumps
WO2004001837A2 (en) * 2002-06-25 2003-12-31 Unitive International Limited Methods of forming electronic structures including conductive shunt layers and related structures
US7531898B2 (en) * 2002-06-25 2009-05-12 Unitive International Limited Non-Circular via holes for bumping pads and related structures
FR2842351A1 (fr) * 2002-07-12 2004-01-16 St Microelectronics Sa Adaptation d'un circuit integre a des besoins specifiques
KR100476301B1 (ko) * 2002-07-27 2005-03-15 한국과학기술원 전기도금법에 의한 반도체 소자의 플립칩 접속용 ubm의형성방법
US7169619B2 (en) * 2002-11-19 2007-01-30 Freescale Semiconductor, Inc. Method for fabricating semiconductor structures on vicinal substrates using a low temperature, low pressure, alkaline earth metal-rich process
US6806202B2 (en) 2002-12-03 2004-10-19 Motorola, Inc. Method of removing silicon oxide from a surface of a substrate
US6969909B2 (en) * 2002-12-20 2005-11-29 Vlt, Inc. Flip chip FET device
JP4170103B2 (ja) * 2003-01-30 2008-10-22 Necエレクトロニクス株式会社 半導体装置、および半導体装置の製造方法
TWI225899B (en) * 2003-02-18 2005-01-01 Unitive Semiconductor Taiwan C Etching solution and method for manufacturing conductive bump using the etching solution to selectively remove barrier layer
CN1291069C (zh) * 2003-05-31 2006-12-20 香港科技大学 微细间距倒装焊凸点电镀制备方法
US7242097B2 (en) 2003-06-30 2007-07-10 Intel Corporation Electromigration barrier layers for solder joints
US7081372B2 (en) * 2003-07-09 2006-07-25 Chartered Semiconductor Manufacturing Ltd. Aluminum cap with electroless nickel/immersion gold
US7169691B2 (en) * 2004-01-29 2007-01-30 Micron Technology, Inc. Method of fabricating wafer-level packaging with sidewall passivation and related apparatus
JP3851320B2 (ja) * 2004-03-25 2006-11-29 Tdk株式会社 回路装置及びその製造方法
US7465654B2 (en) * 2004-07-09 2008-12-16 Megica Corporation Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures
US8022544B2 (en) * 2004-07-09 2011-09-20 Megica Corporation Chip structure
US7452803B2 (en) * 2004-08-12 2008-11-18 Megica Corporation Method for fabricating chip structure
US7325716B2 (en) * 2004-08-24 2008-02-05 Intel Corporation Dense intermetallic compound layer
DE102004047730B4 (de) * 2004-09-30 2017-06-22 Advanced Micro Devices, Inc. Ein Verfahren zum Dünnen von Halbleitersubstraten zur Herstellung von dünnen Halbleiterplättchen
US7547969B2 (en) 2004-10-29 2009-06-16 Megica Corporation Semiconductor chip with passivation layer comprising metal interconnect and contact pads
US7208843B2 (en) * 2005-02-01 2007-04-24 Avago Technologies General Ip (Singapore) Pte. Ltd. Routing design to minimize electromigration damage to solder bumps
US7253528B2 (en) * 2005-02-01 2007-08-07 Avago Technologies General Ip Pte. Ltd. Trace design to minimize electromigration damage to solder bumps
US20060205170A1 (en) * 2005-03-09 2006-09-14 Rinne Glenn A Methods of forming self-healing metal-insulator-metal (MIM) structures and related devices
JP4613708B2 (ja) * 2005-06-23 2011-01-19 ブラザー工業株式会社 回路基板及びインクジェットヘッド
US7314819B2 (en) * 2005-06-30 2008-01-01 Intel Corporation Ball-limiting metallurgies, solder bump compositions used therewith, packages assembled thereby, and methods of assembling same
US7578966B2 (en) * 2005-06-30 2009-08-25 Intel Corporation Solders with intermetallic phases, solder bumps made thereof, packages containing same, and methods of assembling packages therewith
CN102157494B (zh) 2005-07-22 2013-05-01 米辑电子股份有限公司 线路组件
US7397121B2 (en) 2005-10-28 2008-07-08 Megica Corporation Semiconductor chip with post-passivation scheme formed over passivation layer
US7323780B2 (en) * 2005-11-10 2008-01-29 International Business Machines Corporation Electrical interconnection structure formation
US7674701B2 (en) 2006-02-08 2010-03-09 Amkor Technology, Inc. Methods of forming metal layers using multi-layer lift-off patterns
US7932615B2 (en) * 2006-02-08 2011-04-26 Amkor Technology, Inc. Electronic devices including solder bumps on compliant dielectric layers
EP1837910A1 (fr) 2006-03-21 2007-09-26 Stmicroelectronics Sa Puce de circuits integrés à plots externes decalés et procédé de fabrication d'une telle puce.
US7569422B2 (en) * 2006-08-11 2009-08-04 Megica Corporation Chip package and method for fabricating the same
WO2008054680A2 (en) * 2006-10-31 2008-05-08 Advanced Micro Devices, Inc. A metallization layer stack without a terminal aluminum metal layer
DE102006051491A1 (de) * 2006-10-31 2008-05-15 Advanced Micro Devices, Inc., Sunnyvale Metallisierungsschichtstapel mit einer Aluminiumabschlussmetallschicht
US8558353B2 (en) * 2006-11-15 2013-10-15 Texas Instruments Incorporated Integrated circuit having an uppermost layer comprising landing pads that are distributed thoughout one side of the integrated circuit
US8440272B2 (en) * 2006-12-04 2013-05-14 Megica Corporation Method for forming post passivation Au layer with clean surface
US7485564B2 (en) * 2007-02-12 2009-02-03 International Business Machines Corporation Undercut-free BLM process for Pb-free and Pb-reduced C4
US20090200675A1 (en) 2008-02-11 2009-08-13 Thomas Goebel Passivated Copper Chip Pads
US8114767B2 (en) 2008-03-12 2012-02-14 International Business Machines Corporation Structure, semiconductor structure and method of manufacturing a semiconductor structure and packaging thereof
US7859122B2 (en) * 2008-04-14 2010-12-28 International Business Machines Corporation Final via structures for bond pad-solder ball interconnections
US8212357B2 (en) * 2008-08-08 2012-07-03 International Business Machines Corporation Combination via and pad structure for improved solder bump electromigration characteristics
US8395051B2 (en) * 2008-12-23 2013-03-12 Intel Corporation Doping of lead-free solder alloys and structures formed thereby
US8916464B2 (en) 2008-12-29 2014-12-23 International Business Machines Corporation Structures and methods for improving solder bump connections in semiconductor devices
US20110121438A1 (en) 2009-11-23 2011-05-26 Xilinx, Inc. Extended under-bump metal layer for blocking alpha particles in a semiconductor device
US8872344B2 (en) * 2010-06-09 2014-10-28 Texas Instruments Incorporated Conductive via structures for routing porosity and low via resistance, and processes of making
KR101225844B1 (ko) * 2010-07-13 2013-01-23 플란제 에스이 스퍼터링용 로터리 타겟의 접합 조성물 및 이를 이용한 로터리 타겟의 접합방법
US8237279B2 (en) * 2010-09-10 2012-08-07 International Business Machines Corporation Collar structure around solder balls that connect semiconductor die to semiconductor chip package substrate
US8492892B2 (en) * 2010-12-08 2013-07-23 International Business Machines Corporation Solder bump connections
TWI441292B (zh) * 2011-03-02 2014-06-11 矽品精密工業股份有限公司 半導體結構及其製法
US8659173B1 (en) 2013-01-04 2014-02-25 International Business Machines Corporation Isolated wire structures with reduced stress, methods of manufacturing and design structures
DE102015104570B4 (de) 2015-03-26 2019-07-11 Infineon Technologies Ag Leistungs-chip und chipanordnung
US11189538B2 (en) * 2018-09-28 2021-11-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure with polyimide packaging and manufacturing method
US11062995B2 (en) * 2019-10-09 2021-07-13 Intel Corporation Interconnect fabricated with flowable copper

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4737839A (en) * 1984-03-19 1988-04-12 Trilogy Computer Development Partners, Ltd. Semiconductor chip mounting system
US5130779A (en) * 1990-06-19 1992-07-14 International Business Machines Corporation Solder mass having conductive encapsulating arrangement
US5175609A (en) * 1991-04-10 1992-12-29 International Business Machines Corporation Structure and method for corrosion and stress-resistant interconnecting metallurgy
US5536549A (en) * 1993-08-02 1996-07-16 Tulip Memory Systems, Inc. Austenitic stainless steel substrate for magnetic-recording media
KR100245971B1 (ko) * 1995-11-30 2000-03-02 포만 제프리 엘 중합접착제를 금속에 접착시키기 위한 접착력 촉진층을 이용하는 히트싱크어셈블리 및 그 제조방법
US5891756A (en) 1997-06-27 1999-04-06 Delco Electronics Corporation Process for converting a wire bond pad to a flip chip solder bump pad and pad formed thereby
US6162652A (en) 1997-12-31 2000-12-19 Intel Corporation Process for sort testing C4 bumped wafers
US6875681B1 (en) 1997-12-31 2005-04-05 Intel Corporation Wafer passivation structure and method of fabrication
WO1999045590A1 (en) * 1998-03-02 1999-09-10 Motorola Inc. Flipchip assembly having rigid inner core bumps
JP2000091369A (ja) 1998-09-11 2000-03-31 Sony Corp 半導体装置及びその製造方法
US6312830B1 (en) * 1999-09-02 2001-11-06 Intel Corporation Method and an apparatus for forming an under bump metallization structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107863332A (zh) * 2016-09-21 2018-03-30 英飞凌科技股份有限公司 电子器件、电子模块及其制造方法

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