CN1106689C - 半导体封装引线去边方法 - Google Patents

半导体封装引线去边方法 Download PDF

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CN1106689C
CN1106689C CN96120831A CN96120831A CN1106689C CN 1106689 C CN1106689 C CN 1106689C CN 96120831 A CN96120831 A CN 96120831A CN 96120831 A CN96120831 A CN 96120831A CN 1106689 C CN1106689 C CN 1106689C
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lead
film
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CN1169027A (zh
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崔信
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SK Hynix Inc
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Abstract

半导体封装引线去边方法包括下列步骤：在多根引线上形成镀敷薄膜；减弱镀敷薄膜的粘附力，分别从多根引线上去除溢料和形成于其下的镀敷薄膜。该引线去边方法可完全去除封装制造过程中形成的引线溢料，并且通过采用无化学去边法，可防止污染。

Description

半导体封装引线去边方法
技术领域
本发明涉及一种半导体封装，特别涉及一种去除粘附在半导体封装引线上的溢料的方法。
背景技术
封装制作过程中，完成了化合物模塑时，一般要进行芯片封装引线去边工艺，以去除在模塑工艺期间形成于引线表面上的树脂放出的液体和溢料。这种封装引线去边方法包括化学去边或机械去边。化学去边方法又分成干法腐蚀、液压腐蚀、湿法腐蚀等等。
干法腐蚀由于巨大的污物收集器和大的功率消耗会产生噪声问题。液压腐蚀会导致有害的封装损伤，及由于加于其中的高水压使封装的引线框架产生不希望的弯曲。湿法腐蚀工艺的情况下，虽然可以解决上述问题，但当引线间隔窄时，磨料会粘到引线之间，引起封装可靠性降低。
BLP引线暴露于封装的底表面。外露的底部引线表面与外部端子连接，如印刷电路板(PCB)。引线溢料会粘在底部引线整个下表面上，这便难以从引线表面去除溢料。因此，极大地降低了优质封装的产量。
图1是表示常规BLP的剖面图。用粘结剂3把半导体芯片粘结到引线框架2上。暴露底部引线2a。用模制树脂5包封内引线。金线4电连接半导体芯片1的焊盘与引线2。
如图1所示，在模塑工艺期间，在底部引线2a的底表面上不可避免地形成了引线溢料6。由于引线溢料6粘附在整个底部引线表面上，它必然暴露于外部，所以在如上所述的常规去边方法条件下，几乎无法从底部引线表面上去除溢料。
为了去除产生在这种BLP上的溢料，单独采取了研磨去边法，从而磨去引线溢料。由于研磨去边法不同于上述的化学去边法或机械去边法，所以要进行研磨去边方法，必须额外提供研磨装置。
发明内容
本发明的优点是增加了封装的可靠性。
本发明的另一个优点是增加封装成品率。
本发明的再一个优点是减少制作芯片封装的成本。
本发明的又一个优点是能有效去除引线溢料。
至少部分实现本发明的半导体封装引线去边法包括下列步骤：在多根引线上形成镀敷薄膜；减弱镀敷薄膜的粘附力；分别从多根引线上去除溢料和形成于其下的镀敷薄膜。
借助形成半导体封装的方法，至少可以部分实现上述优点和其它优点，该方法包括下列步骤：在多根引线的第一表面的预定部分上形成一种易去除薄膜；在多根引线的第二表面上安装芯片；连接多根引线与芯片的多个焊盘；用模制管座封装芯片和多根引线，使所述易去除薄膜暴露于模制管座的外表面上；以及除去易去除薄膜和形成在一次性薄膜上的溢料，使多根引线的第一表面的预定部分暴露于外表面上。
下面的说明会部分地表现出本发明的其它优点、目的和其它特点，而且本领域的技术人员通过下面的试验或通过实践本发明会更清楚本发明的这些优点、目的和特点。所附权利要求书所特别指出的方案，可以实现本发明的目的和取得本发明的优点。
附图说明
下面将参照附图详细说明本发明，各附图中相同的标记表示相同的部件。
图1是常规BLP的剖面图；
图2是常规BLP引线框架的平面图；
图3是沿图2中线A-A所取的剖面图；
图4A至图4D是按照本的一个实施例的BLP制造步骤的剖面图。
具体实施方式
图2是常规BLP引线框架的平面图。引线包括边轨11、空腔12、用于与PCB连接的多根底部引线13a和用于引线连接的多根内引线13b。图3是沿图2中线A-A所取的剖面图，其中具体示出了底部引线13a和内引线13b。
图4A至4D是BLP制造步骤的剖面图。如图4A所示，在引线框架的底部引线13的下表面上形成镀敷薄膜或一种易去除膜14，在模塑工艺后，将会在其下表面上产生引线溢料。镀敷薄膜14由Sn-Ag(锡-银)化合物制成。Sn和Ag的重量比最好为八十比二十到八十五比十五(80∶20-85∶15)。也可用Sn-Sb化合物作镀敷薄膜。然而，Sb比Ag贵，最好还是用Sn-Ag化合物。Sn-Ag化合物的熔点在330-380℃。最好用溅射技术来形成镀敷薄膜14。
如图4B所示，用双面绝缘带16，把半导体芯片15安装到底部引线13a的上表面上，所述双面绝缘带选自聚酰胺粘合带，且其玻璃转换温度(Tg)为约150℃。要求管芯连接工艺中的最高温度约为300℃，以防止在管芯连接工艺中镀敷薄膜14熔化，但使其粘附力下降。而且，可以获得镀敷薄膜14的剥离特性。
在用常规双面粘合带进行管芯连接工艺时，管芯连接工艺的最高温度保持在400℃3至4秒。因此，Sn-Ag化合物中Ag与Sn的重量比可以增至40％，以把其熔点提高至要求温度。然而，由于Ag材料的成本高于Sn材料，所以可把玻璃转换温度(Tg)低的双面粘合带用于管芯连接工艺。
在管芯连接工艺后，如图4C所示，进行引线连接，用导线17连接芯片15与每根内引线13b。如图4D所示，进行树脂模塑工艺，用模制树脂18封装芯片，但露出每根底部引线13a的下表面。然后，进行固化工艺，固化模制树脂18。在上述模塑工艺期间，溢料19粘附在镀敷薄膜14的表面上。
在随后的成型固化工艺期间，在180℃的温度持续约5小时，且无需任何特殊模具腔设计，其上有溢料的镀敷薄膜逐渐开始失去其自身的粘附力。通过将水介质化合物剧烈地喷射到封装底部或底部引线13a的下部，进行湿法腐蚀引线去边工艺。结果，可以容易而干净地从底部引线13a的底表面上除去形成于溢料19下且连接在底部引线13a的底表面上的镀敷薄膜14，从而实现完全去边。
如上所述，根据本发明的半导体封装引线去边方法，可完全去除BLP制造过程中产生的引线溢料，并且通过采用无化学去边法，可防止污染。上述实施例仅是例证性的，并不限制本发明。可以容易地将本发明的方案用于引线暴露且需要去除溢料的其它类型的封装。例如，本发明可以用于公开于美国专利5363279、5428248、5326932、5444301和5471088中的封装，这些申请一般归于与本申请相同的受让者，且可通过引证把它们所公开的内容结合进去。而且，本发明公开了用模制树脂完全封装的芯片。显然，本发明也可用于不完全包封半导体芯片的封装，即，模制树脂封装半导体芯片。本发明的说明只是说明性的，并不限制要求书的范围。本领域的技术人员可以对本发明作出许多替换、改型和变化。

Claims (24)

1.一种半导体封装引线去边方法，包括下列步骤；
在多根引线上形成镀敷薄膜；
减弱所述镀敷薄膜与所述多根引线的粘附力；以及
分别从多根引线上去除引线溢料和形成于其下的所述镀敷薄膜。
2.如权利要求1所述的方法，其特征在于：所述镀敷薄膜由Sn-Ag制成。
3.如权利要求1所述的方法，其特征在于：所述镀敷薄膜由Sn-Sb制成。
4.如权利要求1所述的方法，其特征在于：形成所述镀敷薄膜的所述步骤包括溅射所述镀敷薄膜的步骤。
5.如权利要求1所述的方法，具特征在于：去除步骤包括湿法腐蚀技术。
6.如权利要求5所述的方法，其特征在于：通过将水介质化合物剧烈地喷射到多根引线的产生溢料的部分，进行湿法腐蚀，从而，分别除去所产溢料和所述镀敷薄膜。
7.如权利要求2所述的方法，其特征在于：把所述Sn-Ag化合物的熔点调节至高于形成所述镀敷薄膜工艺的最高温度，从而只减弱粘附力，防止所述镀敷薄膜熔化。
8.如权利要求7所述的方法还包括连接管芯和固化的步骤。
9.如权利要求3所述的方法，其特征在于：把所述Sn-Sb化合物的熔点调节至高于形成所述镀敷薄膜工艺的最高温度，从而只减弱粘附力，防止所述镀敷薄膜熔化。
10.如权利要求9所述的方法还包括连接管芯和固化的步骤。
11.如权利要求10所述的方法，其特征在于：在所述管芯连接过程中用聚酰胺粘合剂。
12.如权利要求10所述的方法，其特征在于：在所述连接管芯和固化过程所用温度下，逐渐减弱所述镀敷薄膜的粘附力。
13.一种形成半导体封装的方法，包括下列步骤：
在多根引线的第一表面的预定部分上形成一种易去除薄膜；
在所述多根引线的第二表面上安装芯片；
连接所述多根引线与所述芯片的多个焊盘；
用模制管座封装所述芯片和所述多根引线，使所述易去除薄膜暴露于所述模制管座的外表面上；以及
除去所述易去除薄膜和形成在所述易去除薄膜上的溢料，使所述多根引线的第一表面的所述预定部分暴露于外表面上。
14.如权利要求13所述的方法，其特征在于：所述易去除薄膜包括从下面的组中选择的一种物质：Sn-Ag化合物、Sn-Sb化合物以及它们的混合物。
15.如权利要求14所述的方法，其特征在于：所述Sn-Ag化合物的重量比约为80∶20至85∶15。
16.如权利要求13所述的方法，其特征在于：把所述易去除薄膜溅射到所述预定部位。
17.如权利要求13所述的方法，其特征在于：用粘结剂将所述芯片安装到所述多根引线上。
18.如权利要求13所述的方法，其特征在于：所述连接步骤包括引线连接步骤。
19.如权利要求13所述的方法，其特征在于：所述封装步骤包括：用树脂模塑所述芯片和引线；及
固化模制树脂。
20.如权利要求19所述的方法，其特征在于：所述模制树脂包封半导体芯片。
21.如权利要求13所述的方法，其特征在于：所述易去除薄膜在安装工艺过程中变得易于剥落。
22.如权利要求13所述的方法，其特征在于：所述易去除薄膜在封装过程中失去粘附性。
23.如权利要求13所述的方法，其特征在于：所述去除步骤包括湿法腐蚀引线去边工艺。
24.如权利要求23所述的方法，其特征在于：所述湿法腐蚀引线去边工艺包括将水介质化合物喷射到所述预定部位。
CN96120831A 1996-06-14 1996-11-22 半导体封装引线去边方法 Expired - Fee Related CN1106689C (zh)

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Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR940007757Y1 (ko) * 1991-11-14 1994-10-24 금성일렉트론 주식회사 반도체 패키지
JPH09270488A (ja) * 1996-01-29 1997-10-14 Fujitsu Ltd 半導体装置の製造方法
US6230719B1 (en) 1998-02-27 2001-05-15 Micron Technology, Inc. Apparatus for removing contaminants on electronic devices
JP3169919B2 (ja) * 1998-12-21 2001-05-28 九州日本電気株式会社 ボールグリッドアレイ型半導体装置及びその製造方法
NL1011929C2 (nl) * 1999-04-29 2000-10-31 3P Licensing Bv Werkwijze voor het inkapselen van elektronische componenten, in het bijzonder geintegreerde schakelingen.
US6476471B1 (en) * 2000-03-14 2002-11-05 Analog Devices, Inc. Microelectronic-device assemblies and methods that exclude extraneous elements from sensitive areas
JP2002093831A (ja) * 2000-09-14 2002-03-29 Shinko Electric Ind Co Ltd 半導体装置およびその製造方法
KR100374629B1 (ko) 2000-12-19 2003-03-04 페어차일드코리아반도체 주식회사 얇고 작은 크기의 전력용 반도체 패키지
KR100490680B1 (ko) * 2003-05-12 2005-05-19 주식회사 젯텍 사이드플래시에 절취홈을 갖는 반도체 패키지 및 그형성방법, 그리고 이를 이용한 디플래시 방법
US7060535B1 (en) * 2003-10-29 2006-06-13 Ns Electronics Bangkok (1993) Ltd. Flat no-lead semiconductor die package including stud terminals
US7202112B2 (en) * 2004-10-22 2007-04-10 Tessera, Inc. Micro lead frame packages and methods of manufacturing the same
US20070163109A1 (en) * 2005-12-29 2007-07-19 Hem Takiar Strip for integrated circuit packages having a maximized usable area
CN101465333B (zh) * 2007-12-17 2011-04-20 三星电子株式会社 引线框架及其制造方法
US8269244B2 (en) * 2010-06-28 2012-09-18 Cree, Inc. LED package with efficient, isolated thermal path
KR102430431B1 (ko) * 2017-12-27 2022-08-08 한미반도체 주식회사 반도체 패키지 처리장치 및 반도체 패키지 처리방법

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3689991A (en) * 1968-03-01 1972-09-12 Gen Electric A method of manufacturing a semiconductor device utilizing a flexible carrier
US4874722A (en) * 1987-04-16 1989-10-17 Texas Instruments Incorporated Process of packaging a semiconductor device with reduced stress forces
US5106784A (en) * 1987-04-16 1992-04-21 Texas Instruments Incorporated Method of making a post molded cavity package with internal dam bar for integrated circuit
US5233220A (en) * 1989-06-30 1993-08-03 Texas Instruments Incorporated Balanced capacitance lead frame for integrated circuits and integrated circuit device with separate conductive layer
KR940007757Y1 (ko) * 1991-11-14 1994-10-24 금성일렉트론 주식회사 반도체 패키지
KR0157857B1 (ko) * 1992-01-14 1998-12-01 문정환 반도체 패키지
NL9200898A (nl) * 1992-05-21 1993-12-16 Meco Equip Eng Werkwijze voor het middels elektrolyse verwijderen van kunststofuitbloedingen afgezet op metalen aansluitbenen van halfgeleidercomponenten en dergelijke en de bij deze werkwijze gebruikte samenstelling.
KR0128251Y1 (ko) * 1992-08-21 1998-10-15 문정환 리드 노출형 반도체 조립장치
KR960005042B1 (ko) * 1992-11-07 1996-04-18 금성일렉트론주식회사 반도체 펙케지
KR0152901B1 (ko) * 1993-06-23 1998-10-01 문정환 플라스틱 반도체 패키지 및 그 제조방법

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KR980006168A (ko) 1998-03-30
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US5693573A (en) 1997-12-02
JPH1065086A (ja) 1998-03-06

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